1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bitops.h>
3 #include <linux/types.h>
4 #include <linux/slab.h>
5
6 #include <asm/cpu_entry_area.h>
7 #include <asm/perf_event.h>
8 #include <asm/tlbflush.h>
9 #include <asm/insn.h>
10
11 #include "../perf_event.h"
12
13 /* Waste a full page so it can be mapped into the cpu_entry_area */
14 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
15
16 /* The size of a BTS record in bytes: */
17 #define BTS_RECORD_SIZE 24
18
19 #define PEBS_FIXUP_SIZE PAGE_SIZE
20
21 /*
22 * pebs_record_32 for p4 and core not supported
23
24 struct pebs_record_32 {
25 u32 flags, ip;
26 u32 ax, bc, cx, dx;
27 u32 si, di, bp, sp;
28 };
29
30 */
31
32 union intel_x86_pebs_dse {
33 u64 val;
34 struct {
35 unsigned int ld_dse:4;
36 unsigned int ld_stlb_miss:1;
37 unsigned int ld_locked:1;
38 unsigned int ld_reserved:26;
39 };
40 struct {
41 unsigned int st_l1d_hit:1;
42 unsigned int st_reserved1:3;
43 unsigned int st_stlb_miss:1;
44 unsigned int st_locked:1;
45 unsigned int st_reserved2:26;
46 };
47 };
48
49
50 /*
51 * Map PEBS Load Latency Data Source encodings to generic
52 * memory data source information
53 */
54 #define P(a, b) PERF_MEM_S(a, b)
55 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
56 #define LEVEL(x) P(LVLNUM, x)
57 #define REM P(REMOTE, REMOTE)
58 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
59
60 /* Version for Sandy Bridge and later */
61 static u64 pebs_data_source[] = {
62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
63 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
64 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
65 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
72 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
74 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
75 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
76 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
77 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
78 };
79
80 /* Patch up minor differences in the bits */
intel_pmu_pebs_data_source_nhm(void)81 void __init intel_pmu_pebs_data_source_nhm(void)
82 {
83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
85 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
86 }
87
intel_pmu_pebs_data_source_skl(bool pmem)88 void __init intel_pmu_pebs_data_source_skl(bool pmem)
89 {
90 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
91
92 pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
93 pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
94 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
95 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
96 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
97 }
98
precise_store_data(u64 status)99 static u64 precise_store_data(u64 status)
100 {
101 union intel_x86_pebs_dse dse;
102 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
103
104 dse.val = status;
105
106 /*
107 * bit 4: TLB access
108 * 1 = stored missed 2nd level TLB
109 *
110 * so it either hit the walker or the OS
111 * otherwise hit 2nd level TLB
112 */
113 if (dse.st_stlb_miss)
114 val |= P(TLB, MISS);
115 else
116 val |= P(TLB, HIT);
117
118 /*
119 * bit 0: hit L1 data cache
120 * if not set, then all we know is that
121 * it missed L1D
122 */
123 if (dse.st_l1d_hit)
124 val |= P(LVL, HIT);
125 else
126 val |= P(LVL, MISS);
127
128 /*
129 * bit 5: Locked prefix
130 */
131 if (dse.st_locked)
132 val |= P(LOCK, LOCKED);
133
134 return val;
135 }
136
precise_datala_hsw(struct perf_event * event,u64 status)137 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
138 {
139 union perf_mem_data_src dse;
140
141 dse.val = PERF_MEM_NA;
142
143 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
144 dse.mem_op = PERF_MEM_OP_STORE;
145 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
146 dse.mem_op = PERF_MEM_OP_LOAD;
147
148 /*
149 * L1 info only valid for following events:
150 *
151 * MEM_UOPS_RETIRED.STLB_MISS_STORES
152 * MEM_UOPS_RETIRED.LOCK_STORES
153 * MEM_UOPS_RETIRED.SPLIT_STORES
154 * MEM_UOPS_RETIRED.ALL_STORES
155 */
156 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
157 if (status & 1)
158 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
159 else
160 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
161 }
162 return dse.val;
163 }
164
load_latency_data(u64 status)165 static u64 load_latency_data(u64 status)
166 {
167 union intel_x86_pebs_dse dse;
168 u64 val;
169
170 dse.val = status;
171
172 /*
173 * use the mapping table for bit 0-3
174 */
175 val = pebs_data_source[dse.ld_dse];
176
177 /*
178 * Nehalem models do not support TLB, Lock infos
179 */
180 if (x86_pmu.pebs_no_tlb) {
181 val |= P(TLB, NA) | P(LOCK, NA);
182 return val;
183 }
184 /*
185 * bit 4: TLB access
186 * 0 = did not miss 2nd level TLB
187 * 1 = missed 2nd level TLB
188 */
189 if (dse.ld_stlb_miss)
190 val |= P(TLB, MISS) | P(TLB, L2);
191 else
192 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
193
194 /*
195 * bit 5: locked prefix
196 */
197 if (dse.ld_locked)
198 val |= P(LOCK, LOCKED);
199
200 return val;
201 }
202
203 struct pebs_record_core {
204 u64 flags, ip;
205 u64 ax, bx, cx, dx;
206 u64 si, di, bp, sp;
207 u64 r8, r9, r10, r11;
208 u64 r12, r13, r14, r15;
209 };
210
211 struct pebs_record_nhm {
212 u64 flags, ip;
213 u64 ax, bx, cx, dx;
214 u64 si, di, bp, sp;
215 u64 r8, r9, r10, r11;
216 u64 r12, r13, r14, r15;
217 u64 status, dla, dse, lat;
218 };
219
220 /*
221 * Same as pebs_record_nhm, with two additional fields.
222 */
223 struct pebs_record_hsw {
224 u64 flags, ip;
225 u64 ax, bx, cx, dx;
226 u64 si, di, bp, sp;
227 u64 r8, r9, r10, r11;
228 u64 r12, r13, r14, r15;
229 u64 status, dla, dse, lat;
230 u64 real_ip, tsx_tuning;
231 };
232
233 union hsw_tsx_tuning {
234 struct {
235 u32 cycles_last_block : 32,
236 hle_abort : 1,
237 rtm_abort : 1,
238 instruction_abort : 1,
239 non_instruction_abort : 1,
240 retry : 1,
241 data_conflict : 1,
242 capacity_writes : 1,
243 capacity_reads : 1;
244 };
245 u64 value;
246 };
247
248 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
249
250 /* Same as HSW, plus TSC */
251
252 struct pebs_record_skl {
253 u64 flags, ip;
254 u64 ax, bx, cx, dx;
255 u64 si, di, bp, sp;
256 u64 r8, r9, r10, r11;
257 u64 r12, r13, r14, r15;
258 u64 status, dla, dse, lat;
259 u64 real_ip, tsx_tuning;
260 u64 tsc;
261 };
262
init_debug_store_on_cpu(int cpu)263 void init_debug_store_on_cpu(int cpu)
264 {
265 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
266
267 if (!ds)
268 return;
269
270 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
271 (u32)((u64)(unsigned long)ds),
272 (u32)((u64)(unsigned long)ds >> 32));
273 }
274
fini_debug_store_on_cpu(int cpu)275 void fini_debug_store_on_cpu(int cpu)
276 {
277 if (!per_cpu(cpu_hw_events, cpu).ds)
278 return;
279
280 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
281 }
282
283 static DEFINE_PER_CPU(void *, insn_buffer);
284
ds_update_cea(void * cea,void * addr,size_t size,pgprot_t prot)285 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
286 {
287 unsigned long start = (unsigned long)cea;
288 phys_addr_t pa;
289 size_t msz = 0;
290
291 pa = virt_to_phys(addr);
292
293 preempt_disable();
294 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
295 cea_set_pte(cea, pa, prot);
296
297 /*
298 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
299 * all TLB entries for it.
300 */
301 flush_tlb_kernel_range(start, start + size);
302 preempt_enable();
303 }
304
ds_clear_cea(void * cea,size_t size)305 static void ds_clear_cea(void *cea, size_t size)
306 {
307 unsigned long start = (unsigned long)cea;
308 size_t msz = 0;
309
310 preempt_disable();
311 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
312 cea_set_pte(cea, 0, PAGE_NONE);
313
314 flush_tlb_kernel_range(start, start + size);
315 preempt_enable();
316 }
317
dsalloc_pages(size_t size,gfp_t flags,int cpu)318 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
319 {
320 unsigned int order = get_order(size);
321 int node = cpu_to_node(cpu);
322 struct page *page;
323
324 page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
325 return page ? page_address(page) : NULL;
326 }
327
dsfree_pages(const void * buffer,size_t size)328 static void dsfree_pages(const void *buffer, size_t size)
329 {
330 if (buffer)
331 free_pages((unsigned long)buffer, get_order(size));
332 }
333
alloc_pebs_buffer(int cpu)334 static int alloc_pebs_buffer(int cpu)
335 {
336 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
337 struct debug_store *ds = hwev->ds;
338 size_t bsiz = x86_pmu.pebs_buffer_size;
339 int max, node = cpu_to_node(cpu);
340 void *buffer, *ibuffer, *cea;
341
342 if (!x86_pmu.pebs)
343 return 0;
344
345 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
346 if (unlikely(!buffer))
347 return -ENOMEM;
348
349 /*
350 * HSW+ already provides us the eventing ip; no need to allocate this
351 * buffer then.
352 */
353 if (x86_pmu.intel_cap.pebs_format < 2) {
354 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
355 if (!ibuffer) {
356 dsfree_pages(buffer, bsiz);
357 return -ENOMEM;
358 }
359 per_cpu(insn_buffer, cpu) = ibuffer;
360 }
361 hwev->ds_pebs_vaddr = buffer;
362 /* Update the cpu entry area mapping */
363 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
364 ds->pebs_buffer_base = (unsigned long) cea;
365 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
366 ds->pebs_index = ds->pebs_buffer_base;
367 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
368 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
369 return 0;
370 }
371
release_pebs_buffer(int cpu)372 static void release_pebs_buffer(int cpu)
373 {
374 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
375 struct debug_store *ds = hwev->ds;
376 void *cea;
377
378 if (!ds || !x86_pmu.pebs)
379 return;
380
381 kfree(per_cpu(insn_buffer, cpu));
382 per_cpu(insn_buffer, cpu) = NULL;
383
384 /* Clear the fixmap */
385 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
386 ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
387 ds->pebs_buffer_base = 0;
388 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
389 hwev->ds_pebs_vaddr = NULL;
390 }
391
alloc_bts_buffer(int cpu)392 static int alloc_bts_buffer(int cpu)
393 {
394 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
395 struct debug_store *ds = hwev->ds;
396 void *buffer, *cea;
397 int max;
398
399 if (!x86_pmu.bts)
400 return 0;
401
402 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
403 if (unlikely(!buffer)) {
404 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
405 return -ENOMEM;
406 }
407 hwev->ds_bts_vaddr = buffer;
408 /* Update the fixmap */
409 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
410 ds->bts_buffer_base = (unsigned long) cea;
411 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
412 ds->bts_index = ds->bts_buffer_base;
413 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
414 ds->bts_absolute_maximum = ds->bts_buffer_base +
415 max * BTS_RECORD_SIZE;
416 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
417 (max / 16) * BTS_RECORD_SIZE;
418 return 0;
419 }
420
release_bts_buffer(int cpu)421 static void release_bts_buffer(int cpu)
422 {
423 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
424 struct debug_store *ds = hwev->ds;
425 void *cea;
426
427 if (!ds || !x86_pmu.bts)
428 return;
429
430 /* Clear the fixmap */
431 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
432 ds_clear_cea(cea, BTS_BUFFER_SIZE);
433 ds->bts_buffer_base = 0;
434 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
435 hwev->ds_bts_vaddr = NULL;
436 }
437
alloc_ds_buffer(int cpu)438 static int alloc_ds_buffer(int cpu)
439 {
440 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
441
442 memset(ds, 0, sizeof(*ds));
443 per_cpu(cpu_hw_events, cpu).ds = ds;
444 return 0;
445 }
446
release_ds_buffer(int cpu)447 static void release_ds_buffer(int cpu)
448 {
449 per_cpu(cpu_hw_events, cpu).ds = NULL;
450 }
451
release_ds_buffers(void)452 void release_ds_buffers(void)
453 {
454 int cpu;
455
456 if (!x86_pmu.bts && !x86_pmu.pebs)
457 return;
458
459 get_online_cpus();
460 for_each_online_cpu(cpu)
461 fini_debug_store_on_cpu(cpu);
462
463 for_each_possible_cpu(cpu) {
464 release_pebs_buffer(cpu);
465 release_bts_buffer(cpu);
466 release_ds_buffer(cpu);
467 }
468 put_online_cpus();
469 }
470
reserve_ds_buffers(void)471 void reserve_ds_buffers(void)
472 {
473 int bts_err = 0, pebs_err = 0;
474 int cpu;
475
476 x86_pmu.bts_active = 0;
477 x86_pmu.pebs_active = 0;
478
479 if (!x86_pmu.bts && !x86_pmu.pebs)
480 return;
481
482 if (!x86_pmu.bts)
483 bts_err = 1;
484
485 if (!x86_pmu.pebs)
486 pebs_err = 1;
487
488 get_online_cpus();
489
490 for_each_possible_cpu(cpu) {
491 if (alloc_ds_buffer(cpu)) {
492 bts_err = 1;
493 pebs_err = 1;
494 }
495
496 if (!bts_err && alloc_bts_buffer(cpu))
497 bts_err = 1;
498
499 if (!pebs_err && alloc_pebs_buffer(cpu))
500 pebs_err = 1;
501
502 if (bts_err && pebs_err)
503 break;
504 }
505
506 if (bts_err) {
507 for_each_possible_cpu(cpu)
508 release_bts_buffer(cpu);
509 }
510
511 if (pebs_err) {
512 for_each_possible_cpu(cpu)
513 release_pebs_buffer(cpu);
514 }
515
516 if (bts_err && pebs_err) {
517 for_each_possible_cpu(cpu)
518 release_ds_buffer(cpu);
519 } else {
520 if (x86_pmu.bts && !bts_err)
521 x86_pmu.bts_active = 1;
522
523 if (x86_pmu.pebs && !pebs_err)
524 x86_pmu.pebs_active = 1;
525
526 for_each_online_cpu(cpu)
527 init_debug_store_on_cpu(cpu);
528 }
529
530 put_online_cpus();
531 }
532
533 /*
534 * BTS
535 */
536
537 struct event_constraint bts_constraint =
538 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
539
intel_pmu_enable_bts(u64 config)540 void intel_pmu_enable_bts(u64 config)
541 {
542 unsigned long debugctlmsr;
543
544 debugctlmsr = get_debugctlmsr();
545
546 debugctlmsr |= DEBUGCTLMSR_TR;
547 debugctlmsr |= DEBUGCTLMSR_BTS;
548 if (config & ARCH_PERFMON_EVENTSEL_INT)
549 debugctlmsr |= DEBUGCTLMSR_BTINT;
550
551 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
552 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
553
554 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
555 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
556
557 update_debugctlmsr(debugctlmsr);
558 }
559
intel_pmu_disable_bts(void)560 void intel_pmu_disable_bts(void)
561 {
562 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
563 unsigned long debugctlmsr;
564
565 if (!cpuc->ds)
566 return;
567
568 debugctlmsr = get_debugctlmsr();
569
570 debugctlmsr &=
571 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
572 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
573
574 update_debugctlmsr(debugctlmsr);
575 }
576
intel_pmu_drain_bts_buffer(void)577 int intel_pmu_drain_bts_buffer(void)
578 {
579 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
580 struct debug_store *ds = cpuc->ds;
581 struct bts_record {
582 u64 from;
583 u64 to;
584 u64 flags;
585 };
586 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
587 struct bts_record *at, *base, *top;
588 struct perf_output_handle handle;
589 struct perf_event_header header;
590 struct perf_sample_data data;
591 unsigned long skip = 0;
592 struct pt_regs regs;
593
594 if (!event)
595 return 0;
596
597 if (!x86_pmu.bts_active)
598 return 0;
599
600 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
601 top = (struct bts_record *)(unsigned long)ds->bts_index;
602
603 if (top <= base)
604 return 0;
605
606 memset(®s, 0, sizeof(regs));
607
608 ds->bts_index = ds->bts_buffer_base;
609
610 perf_sample_data_init(&data, 0, event->hw.last_period);
611
612 /*
613 * BTS leaks kernel addresses in branches across the cpl boundary,
614 * such as traps or system calls, so unless the user is asking for
615 * kernel tracing (and right now it's not possible), we'd need to
616 * filter them out. But first we need to count how many of those we
617 * have in the current batch. This is an extra O(n) pass, however,
618 * it's much faster than the other one especially considering that
619 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
620 * alloc_bts_buffer()).
621 */
622 for (at = base; at < top; at++) {
623 /*
624 * Note that right now *this* BTS code only works if
625 * attr::exclude_kernel is set, but let's keep this extra
626 * check here in case that changes.
627 */
628 if (event->attr.exclude_kernel &&
629 (kernel_ip(at->from) || kernel_ip(at->to)))
630 skip++;
631 }
632
633 /*
634 * Prepare a generic sample, i.e. fill in the invariant fields.
635 * We will overwrite the from and to address before we output
636 * the sample.
637 */
638 rcu_read_lock();
639 perf_prepare_sample(&header, &data, event, ®s);
640
641 if (perf_output_begin(&handle, event, header.size *
642 (top - base - skip)))
643 goto unlock;
644
645 for (at = base; at < top; at++) {
646 /* Filter out any records that contain kernel addresses. */
647 if (event->attr.exclude_kernel &&
648 (kernel_ip(at->from) || kernel_ip(at->to)))
649 continue;
650
651 data.ip = at->from;
652 data.addr = at->to;
653
654 perf_output_sample(&handle, &header, &data, event);
655 }
656
657 perf_output_end(&handle);
658
659 /* There's new data available. */
660 event->hw.interrupts++;
661 event->pending_kill = POLL_IN;
662 unlock:
663 rcu_read_unlock();
664 return 1;
665 }
666
intel_pmu_drain_pebs_buffer(void)667 static inline void intel_pmu_drain_pebs_buffer(void)
668 {
669 struct pt_regs regs;
670
671 x86_pmu.drain_pebs(®s);
672 }
673
674 /*
675 * PEBS
676 */
677 struct event_constraint intel_core2_pebs_event_constraints[] = {
678 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
679 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
680 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
681 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
683 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
684 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
685 EVENT_CONSTRAINT_END
686 };
687
688 struct event_constraint intel_atom_pebs_event_constraints[] = {
689 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
690 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
691 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
692 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
693 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
694 /* Allow all events as PEBS with no flags */
695 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
696 EVENT_CONSTRAINT_END
697 };
698
699 struct event_constraint intel_slm_pebs_event_constraints[] = {
700 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
701 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
702 /* Allow all events as PEBS with no flags */
703 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
704 EVENT_CONSTRAINT_END
705 };
706
707 struct event_constraint intel_glm_pebs_event_constraints[] = {
708 /* Allow all events as PEBS with no flags */
709 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
710 EVENT_CONSTRAINT_END
711 };
712
713 struct event_constraint intel_glp_pebs_event_constraints[] = {
714 /* Allow all events as PEBS with no flags */
715 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
716 EVENT_CONSTRAINT_END
717 };
718
719 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
720 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
721 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
722 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
723 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
724 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
725 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
726 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
727 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
728 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
729 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
730 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
731 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
732 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
733 EVENT_CONSTRAINT_END
734 };
735
736 struct event_constraint intel_westmere_pebs_event_constraints[] = {
737 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
738 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
739 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
740 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
741 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
742 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
743 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
744 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
745 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
746 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
747 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
748 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
749 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
750 EVENT_CONSTRAINT_END
751 };
752
753 struct event_constraint intel_snb_pebs_event_constraints[] = {
754 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
755 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
756 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
757 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
758 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
759 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
760 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
761 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
762 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
763 /* Allow all events as PEBS with no flags */
764 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
765 EVENT_CONSTRAINT_END
766 };
767
768 struct event_constraint intel_ivb_pebs_event_constraints[] = {
769 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
770 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
771 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
772 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
773 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
774 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
775 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
776 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
777 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
778 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
779 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
780 /* Allow all events as PEBS with no flags */
781 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
782 EVENT_CONSTRAINT_END
783 };
784
785 struct event_constraint intel_hsw_pebs_event_constraints[] = {
786 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
787 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
788 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
789 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
790 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
791 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
792 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
793 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
794 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
795 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
796 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
797 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
798 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
799 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
800 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
801 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
802 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
803 /* Allow all events as PEBS with no flags */
804 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
805 EVENT_CONSTRAINT_END
806 };
807
808 struct event_constraint intel_bdw_pebs_event_constraints[] = {
809 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
810 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
811 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
812 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
813 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
814 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
815 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
816 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
817 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
818 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
819 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
820 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
821 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
822 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
823 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
824 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
825 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
826 /* Allow all events as PEBS with no flags */
827 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
828 EVENT_CONSTRAINT_END
829 };
830
831
832 struct event_constraint intel_skl_pebs_event_constraints[] = {
833 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
834 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
835 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
836 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
837 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
838 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
839 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
840 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
841 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
842 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
843 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
844 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
845 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
846 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
847 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
848 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
849 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
850 /* Allow all events as PEBS with no flags */
851 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
852 EVENT_CONSTRAINT_END
853 };
854
intel_pebs_constraints(struct perf_event * event)855 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
856 {
857 struct event_constraint *c;
858
859 if (!event->attr.precise_ip)
860 return NULL;
861
862 if (x86_pmu.pebs_constraints) {
863 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
864 if ((event->hw.config & c->cmask) == c->code) {
865 event->hw.flags |= c->flags;
866 return c;
867 }
868 }
869 }
870
871 return &emptyconstraint;
872 }
873
874 /*
875 * We need the sched_task callback even for per-cpu events when we use
876 * the large interrupt threshold, such that we can provide PID and TID
877 * to PEBS samples.
878 */
pebs_needs_sched_cb(struct cpu_hw_events * cpuc)879 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
880 {
881 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
882 }
883
intel_pmu_pebs_sched_task(struct perf_event_context * ctx,bool sched_in)884 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
885 {
886 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
887
888 if (!sched_in && pebs_needs_sched_cb(cpuc))
889 intel_pmu_drain_pebs_buffer();
890 }
891
pebs_update_threshold(struct cpu_hw_events * cpuc)892 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
893 {
894 struct debug_store *ds = cpuc->ds;
895 u64 threshold;
896
897 if (cpuc->n_pebs == cpuc->n_large_pebs) {
898 threshold = ds->pebs_absolute_maximum -
899 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
900 } else {
901 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
902 }
903
904 ds->pebs_interrupt_threshold = threshold;
905 }
906
907 static void
pebs_update_state(bool needed_cb,struct cpu_hw_events * cpuc,struct pmu * pmu)908 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu)
909 {
910 /*
911 * Make sure we get updated with the first PEBS
912 * event. It will trigger also during removal, but
913 * that does not hurt:
914 */
915 bool update = cpuc->n_pebs == 1;
916
917 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
918 if (!needed_cb)
919 perf_sched_cb_inc(pmu);
920 else
921 perf_sched_cb_dec(pmu);
922
923 update = true;
924 }
925
926 if (update)
927 pebs_update_threshold(cpuc);
928 }
929
intel_pmu_pebs_add(struct perf_event * event)930 void intel_pmu_pebs_add(struct perf_event *event)
931 {
932 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
933 struct hw_perf_event *hwc = &event->hw;
934 bool needed_cb = pebs_needs_sched_cb(cpuc);
935
936 cpuc->n_pebs++;
937 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
938 cpuc->n_large_pebs++;
939
940 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
941 }
942
intel_pmu_pebs_enable(struct perf_event * event)943 void intel_pmu_pebs_enable(struct perf_event *event)
944 {
945 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
946 struct hw_perf_event *hwc = &event->hw;
947 struct debug_store *ds = cpuc->ds;
948
949 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
950
951 cpuc->pebs_enabled |= 1ULL << hwc->idx;
952
953 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
954 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
955 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
956 cpuc->pebs_enabled |= 1ULL << 63;
957
958 /*
959 * Use auto-reload if possible to save a MSR write in the PMI.
960 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
961 */
962 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
963 ds->pebs_event_reset[hwc->idx] =
964 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
965 } else {
966 ds->pebs_event_reset[hwc->idx] = 0;
967 }
968 }
969
intel_pmu_pebs_del(struct perf_event * event)970 void intel_pmu_pebs_del(struct perf_event *event)
971 {
972 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
973 struct hw_perf_event *hwc = &event->hw;
974 bool needed_cb = pebs_needs_sched_cb(cpuc);
975
976 cpuc->n_pebs--;
977 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
978 cpuc->n_large_pebs--;
979
980 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
981 }
982
intel_pmu_pebs_disable(struct perf_event * event)983 void intel_pmu_pebs_disable(struct perf_event *event)
984 {
985 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
986 struct hw_perf_event *hwc = &event->hw;
987
988 if (cpuc->n_pebs == cpuc->n_large_pebs)
989 intel_pmu_drain_pebs_buffer();
990
991 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
992
993 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
994 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
995 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
996 cpuc->pebs_enabled &= ~(1ULL << 63);
997
998 if (cpuc->enabled)
999 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1000
1001 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1002 }
1003
intel_pmu_pebs_enable_all(void)1004 void intel_pmu_pebs_enable_all(void)
1005 {
1006 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1007
1008 if (cpuc->pebs_enabled)
1009 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1010 }
1011
intel_pmu_pebs_disable_all(void)1012 void intel_pmu_pebs_disable_all(void)
1013 {
1014 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1015
1016 if (cpuc->pebs_enabled)
1017 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1018 }
1019
intel_pmu_pebs_fixup_ip(struct pt_regs * regs)1020 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1021 {
1022 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1023 unsigned long from = cpuc->lbr_entries[0].from;
1024 unsigned long old_to, to = cpuc->lbr_entries[0].to;
1025 unsigned long ip = regs->ip;
1026 int is_64bit = 0;
1027 void *kaddr;
1028 int size;
1029
1030 /*
1031 * We don't need to fixup if the PEBS assist is fault like
1032 */
1033 if (!x86_pmu.intel_cap.pebs_trap)
1034 return 1;
1035
1036 /*
1037 * No LBR entry, no basic block, no rewinding
1038 */
1039 if (!cpuc->lbr_stack.nr || !from || !to)
1040 return 0;
1041
1042 /*
1043 * Basic blocks should never cross user/kernel boundaries
1044 */
1045 if (kernel_ip(ip) != kernel_ip(to))
1046 return 0;
1047
1048 /*
1049 * unsigned math, either ip is before the start (impossible) or
1050 * the basic block is larger than 1 page (sanity)
1051 */
1052 if ((ip - to) > PEBS_FIXUP_SIZE)
1053 return 0;
1054
1055 /*
1056 * We sampled a branch insn, rewind using the LBR stack
1057 */
1058 if (ip == to) {
1059 set_linear_ip(regs, from);
1060 return 1;
1061 }
1062
1063 size = ip - to;
1064 if (!kernel_ip(ip)) {
1065 int bytes;
1066 u8 *buf = this_cpu_read(insn_buffer);
1067
1068 /* 'size' must fit our buffer, see above */
1069 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1070 if (bytes != 0)
1071 return 0;
1072
1073 kaddr = buf;
1074 } else {
1075 kaddr = (void *)to;
1076 }
1077
1078 do {
1079 struct insn insn;
1080
1081 old_to = to;
1082
1083 #ifdef CONFIG_X86_64
1084 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
1085 #endif
1086 insn_init(&insn, kaddr, size, is_64bit);
1087 insn_get_length(&insn);
1088 /*
1089 * Make sure there was not a problem decoding the
1090 * instruction and getting the length. This is
1091 * doubly important because we have an infinite
1092 * loop if insn.length=0.
1093 */
1094 if (!insn.length)
1095 break;
1096
1097 to += insn.length;
1098 kaddr += insn.length;
1099 size -= insn.length;
1100 } while (to < ip);
1101
1102 if (to == ip) {
1103 set_linear_ip(regs, old_to);
1104 return 1;
1105 }
1106
1107 /*
1108 * Even though we decoded the basic block, the instruction stream
1109 * never matched the given IP, either the TO or the IP got corrupted.
1110 */
1111 return 0;
1112 }
1113
intel_hsw_weight(struct pebs_record_skl * pebs)1114 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
1115 {
1116 if (pebs->tsx_tuning) {
1117 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
1118 return tsx.cycles_last_block;
1119 }
1120 return 0;
1121 }
1122
intel_hsw_transaction(struct pebs_record_skl * pebs)1123 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1124 {
1125 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1126
1127 /* For RTM XABORTs also log the abort code from AX */
1128 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1129 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1130 return txn;
1131 }
1132
setup_pebs_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1133 static void setup_pebs_sample_data(struct perf_event *event,
1134 struct pt_regs *iregs, void *__pebs,
1135 struct perf_sample_data *data,
1136 struct pt_regs *regs)
1137 {
1138 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1139 (PERF_X86_EVENT_PEBS_ST_HSW | \
1140 PERF_X86_EVENT_PEBS_LD_HSW | \
1141 PERF_X86_EVENT_PEBS_NA_HSW)
1142 /*
1143 * We cast to the biggest pebs_record but are careful not to
1144 * unconditionally access the 'extra' entries.
1145 */
1146 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1147 struct pebs_record_skl *pebs = __pebs;
1148 u64 sample_type;
1149 int fll, fst, dsrc;
1150 int fl = event->hw.flags;
1151
1152 if (pebs == NULL)
1153 return;
1154
1155 regs->flags &= ~PERF_EFLAGS_EXACT;
1156 sample_type = event->attr.sample_type;
1157 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1158
1159 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1160 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1161
1162 perf_sample_data_init(data, 0, event->hw.last_period);
1163
1164 data->period = event->hw.last_period;
1165
1166 /*
1167 * Use latency for weight (only avail with PEBS-LL)
1168 */
1169 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1170 data->weight = pebs->lat;
1171
1172 /*
1173 * data.data_src encodes the data source
1174 */
1175 if (dsrc) {
1176 u64 val = PERF_MEM_NA;
1177 if (fll)
1178 val = load_latency_data(pebs->dse);
1179 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1180 val = precise_datala_hsw(event, pebs->dse);
1181 else if (fst)
1182 val = precise_store_data(pebs->dse);
1183 data->data_src.val = val;
1184 }
1185
1186 /*
1187 * We use the interrupt regs as a base because the PEBS record does not
1188 * contain a full regs set, specifically it seems to lack segment
1189 * descriptors, which get used by things like user_mode().
1190 *
1191 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1192 *
1193 * We must however always use BP,SP from iregs for the unwinder to stay
1194 * sane; the record BP,SP can point into thin air when the record is
1195 * from a previous PMI context or an (I)RET happend between the record
1196 * and PMI.
1197 */
1198 *regs = *iregs;
1199 regs->flags = pebs->flags;
1200
1201 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1202 regs->ax = pebs->ax;
1203 regs->bx = pebs->bx;
1204 regs->cx = pebs->cx;
1205 regs->dx = pebs->dx;
1206 regs->si = pebs->si;
1207 regs->di = pebs->di;
1208
1209 /*
1210 * Per the above; only set BP,SP if we don't need callchains.
1211 *
1212 * XXX: does this make sense?
1213 */
1214 if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) {
1215 regs->bp = pebs->bp;
1216 regs->sp = pebs->sp;
1217 }
1218
1219 /*
1220 * Preserve PERF_EFLAGS_VM from set_linear_ip().
1221 */
1222 regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM);
1223 #ifndef CONFIG_X86_32
1224 regs->r8 = pebs->r8;
1225 regs->r9 = pebs->r9;
1226 regs->r10 = pebs->r10;
1227 regs->r11 = pebs->r11;
1228 regs->r12 = pebs->r12;
1229 regs->r13 = pebs->r13;
1230 regs->r14 = pebs->r14;
1231 regs->r15 = pebs->r15;
1232 #endif
1233 }
1234
1235 if (event->attr.precise_ip > 1) {
1236 /* Haswell and later have the eventing IP, so use it: */
1237 if (x86_pmu.intel_cap.pebs_format >= 2) {
1238 set_linear_ip(regs, pebs->real_ip);
1239 regs->flags |= PERF_EFLAGS_EXACT;
1240 } else {
1241 /* Otherwise use PEBS off-by-1 IP: */
1242 set_linear_ip(regs, pebs->ip);
1243
1244 /* ... and try to fix it up using the LBR entries: */
1245 if (intel_pmu_pebs_fixup_ip(regs))
1246 regs->flags |= PERF_EFLAGS_EXACT;
1247 }
1248 } else
1249 set_linear_ip(regs, pebs->ip);
1250
1251
1252 if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) &&
1253 x86_pmu.intel_cap.pebs_format >= 1)
1254 data->addr = pebs->dla;
1255
1256 if (x86_pmu.intel_cap.pebs_format >= 2) {
1257 /* Only set the TSX weight when no memory weight. */
1258 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1259 data->weight = intel_hsw_weight(pebs);
1260
1261 if (sample_type & PERF_SAMPLE_TRANSACTION)
1262 data->txn = intel_hsw_transaction(pebs);
1263 }
1264
1265 /*
1266 * v3 supplies an accurate time stamp, so we use that
1267 * for the time stamp.
1268 *
1269 * We can only do this for the default trace clock.
1270 */
1271 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1272 event->attr.use_clockid == 0)
1273 data->time = native_sched_clock_from_tsc(pebs->tsc);
1274
1275 if (has_branch_stack(event))
1276 data->br_stack = &cpuc->lbr_stack;
1277 }
1278
1279 static inline void *
get_next_pebs_record_by_bit(void * base,void * top,int bit)1280 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1281 {
1282 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1283 void *at;
1284 u64 pebs_status;
1285
1286 /*
1287 * fmt0 does not have a status bitfield (does not use
1288 * perf_record_nhm format)
1289 */
1290 if (x86_pmu.intel_cap.pebs_format < 1)
1291 return base;
1292
1293 if (base == NULL)
1294 return NULL;
1295
1296 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1297 struct pebs_record_nhm *p = at;
1298
1299 if (test_bit(bit, (unsigned long *)&p->status)) {
1300 /* PEBS v3 has accurate status bits */
1301 if (x86_pmu.intel_cap.pebs_format >= 3)
1302 return at;
1303
1304 if (p->status == (1 << bit))
1305 return at;
1306
1307 /* clear non-PEBS bit and re-check */
1308 pebs_status = p->status & cpuc->pebs_enabled;
1309 pebs_status &= PEBS_COUNTER_MASK;
1310 if (pebs_status == (1 << bit))
1311 return at;
1312 }
1313 }
1314 return NULL;
1315 }
1316
1317 /*
1318 * Special variant of intel_pmu_save_and_restart() for auto-reload.
1319 */
1320 static int
intel_pmu_save_and_restart_reload(struct perf_event * event,int count)1321 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1322 {
1323 struct hw_perf_event *hwc = &event->hw;
1324 int shift = 64 - x86_pmu.cntval_bits;
1325 u64 period = hwc->sample_period;
1326 u64 prev_raw_count, new_raw_count;
1327 s64 new, old;
1328
1329 WARN_ON(!period);
1330
1331 /*
1332 * drain_pebs() only happens when the PMU is disabled.
1333 */
1334 WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1335
1336 prev_raw_count = local64_read(&hwc->prev_count);
1337 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1338 local64_set(&hwc->prev_count, new_raw_count);
1339
1340 /*
1341 * Since the counter increments a negative counter value and
1342 * overflows on the sign switch, giving the interval:
1343 *
1344 * [-period, 0]
1345 *
1346 * the difference between two consequtive reads is:
1347 *
1348 * A) value2 - value1;
1349 * when no overflows have happened in between,
1350 *
1351 * B) (0 - value1) + (value2 - (-period));
1352 * when one overflow happened in between,
1353 *
1354 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1355 * when @n overflows happened in between.
1356 *
1357 * Here A) is the obvious difference, B) is the extension to the
1358 * discrete interval, where the first term is to the top of the
1359 * interval and the second term is from the bottom of the next
1360 * interval and C) the extension to multiple intervals, where the
1361 * middle term is the whole intervals covered.
1362 *
1363 * An equivalent of C, by reduction, is:
1364 *
1365 * value2 - value1 + n * period
1366 */
1367 new = ((s64)(new_raw_count << shift) >> shift);
1368 old = ((s64)(prev_raw_count << shift) >> shift);
1369 local64_add(new - old + count * period, &event->count);
1370
1371 local64_set(&hwc->period_left, -new);
1372
1373 perf_event_update_userpage(event);
1374
1375 return 0;
1376 }
1377
__intel_pmu_pebs_event(struct perf_event * event,struct pt_regs * iregs,void * base,void * top,int bit,int count)1378 static void __intel_pmu_pebs_event(struct perf_event *event,
1379 struct pt_regs *iregs,
1380 void *base, void *top,
1381 int bit, int count)
1382 {
1383 struct hw_perf_event *hwc = &event->hw;
1384 struct perf_sample_data data;
1385 struct pt_regs regs;
1386 void *at = get_next_pebs_record_by_bit(base, top, bit);
1387
1388 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1389 /*
1390 * Now, auto-reload is only enabled in fixed period mode.
1391 * The reload value is always hwc->sample_period.
1392 * May need to change it, if auto-reload is enabled in
1393 * freq mode later.
1394 */
1395 intel_pmu_save_and_restart_reload(event, count);
1396 } else if (!intel_pmu_save_and_restart(event))
1397 return;
1398
1399 while (count > 1) {
1400 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1401 perf_event_output(event, &data, ®s);
1402 at += x86_pmu.pebs_record_size;
1403 at = get_next_pebs_record_by_bit(at, top, bit);
1404 count--;
1405 }
1406
1407 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1408
1409 /*
1410 * All but the last records are processed.
1411 * The last one is left to be able to call the overflow handler.
1412 */
1413 if (perf_event_overflow(event, &data, ®s)) {
1414 x86_pmu_stop(event, 0);
1415 return;
1416 }
1417
1418 }
1419
intel_pmu_drain_pebs_core(struct pt_regs * iregs)1420 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1421 {
1422 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1423 struct debug_store *ds = cpuc->ds;
1424 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1425 struct pebs_record_core *at, *top;
1426 int n;
1427
1428 if (!x86_pmu.pebs_active)
1429 return;
1430
1431 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1432 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1433
1434 /*
1435 * Whatever else happens, drain the thing
1436 */
1437 ds->pebs_index = ds->pebs_buffer_base;
1438
1439 if (!test_bit(0, cpuc->active_mask))
1440 return;
1441
1442 WARN_ON_ONCE(!event);
1443
1444 if (!event->attr.precise_ip)
1445 return;
1446
1447 n = top - at;
1448 if (n <= 0) {
1449 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1450 intel_pmu_save_and_restart_reload(event, 0);
1451 return;
1452 }
1453
1454 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1455 }
1456
intel_pmu_drain_pebs_nhm(struct pt_regs * iregs)1457 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1458 {
1459 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1460 struct debug_store *ds = cpuc->ds;
1461 struct perf_event *event;
1462 void *base, *at, *top;
1463 short counts[MAX_PEBS_EVENTS] = {};
1464 short error[MAX_PEBS_EVENTS] = {};
1465 int bit, i;
1466
1467 if (!x86_pmu.pebs_active)
1468 return;
1469
1470 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1471 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1472
1473 ds->pebs_index = ds->pebs_buffer_base;
1474
1475 if (unlikely(base >= top)) {
1476 /*
1477 * The drain_pebs() could be called twice in a short period
1478 * for auto-reload event in pmu::read(). There are no
1479 * overflows have happened in between.
1480 * It needs to call intel_pmu_save_and_restart_reload() to
1481 * update the event->count for this case.
1482 */
1483 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled,
1484 x86_pmu.max_pebs_events) {
1485 event = cpuc->events[bit];
1486 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1487 intel_pmu_save_and_restart_reload(event, 0);
1488 }
1489 return;
1490 }
1491
1492 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1493 struct pebs_record_nhm *p = at;
1494 u64 pebs_status;
1495
1496 pebs_status = p->status & cpuc->pebs_enabled;
1497 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1498
1499 /* PEBS v3 has more accurate status bits */
1500 if (x86_pmu.intel_cap.pebs_format >= 3) {
1501 for_each_set_bit(bit, (unsigned long *)&pebs_status,
1502 x86_pmu.max_pebs_events)
1503 counts[bit]++;
1504
1505 continue;
1506 }
1507
1508 /*
1509 * On some CPUs the PEBS status can be zero when PEBS is
1510 * racing with clearing of GLOBAL_STATUS.
1511 *
1512 * Normally we would drop that record, but in the
1513 * case when there is only a single active PEBS event
1514 * we can assume it's for that event.
1515 */
1516 if (!pebs_status && cpuc->pebs_enabled &&
1517 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1518 pebs_status = cpuc->pebs_enabled;
1519
1520 bit = find_first_bit((unsigned long *)&pebs_status,
1521 x86_pmu.max_pebs_events);
1522 if (bit >= x86_pmu.max_pebs_events)
1523 continue;
1524
1525 /*
1526 * The PEBS hardware does not deal well with the situation
1527 * when events happen near to each other and multiple bits
1528 * are set. But it should happen rarely.
1529 *
1530 * If these events include one PEBS and multiple non-PEBS
1531 * events, it doesn't impact PEBS record. The record will
1532 * be handled normally. (slow path)
1533 *
1534 * If these events include two or more PEBS events, the
1535 * records for the events can be collapsed into a single
1536 * one, and it's not possible to reconstruct all events
1537 * that caused the PEBS record. It's called collision.
1538 * If collision happened, the record will be dropped.
1539 */
1540 if (p->status != (1ULL << bit)) {
1541 for_each_set_bit(i, (unsigned long *)&pebs_status,
1542 x86_pmu.max_pebs_events)
1543 error[i]++;
1544 continue;
1545 }
1546
1547 counts[bit]++;
1548 }
1549
1550 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1551 if ((counts[bit] == 0) && (error[bit] == 0))
1552 continue;
1553
1554 event = cpuc->events[bit];
1555 if (WARN_ON_ONCE(!event))
1556 continue;
1557
1558 if (WARN_ON_ONCE(!event->attr.precise_ip))
1559 continue;
1560
1561 /* log dropped samples number */
1562 if (error[bit]) {
1563 perf_log_lost_samples(event, error[bit]);
1564
1565 if (perf_event_account_interrupt(event))
1566 x86_pmu_stop(event, 0);
1567 }
1568
1569 if (counts[bit]) {
1570 __intel_pmu_pebs_event(event, iregs, base,
1571 top, bit, counts[bit]);
1572 }
1573 }
1574 }
1575
1576 /*
1577 * BTS, PEBS probe and setup
1578 */
1579
intel_ds_init(void)1580 void __init intel_ds_init(void)
1581 {
1582 /*
1583 * No support for 32bit formats
1584 */
1585 if (!boot_cpu_has(X86_FEATURE_DTES64))
1586 return;
1587
1588 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1589 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1590 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1591 if (x86_pmu.pebs) {
1592 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1593 int format = x86_pmu.intel_cap.pebs_format;
1594
1595 switch (format) {
1596 case 0:
1597 pr_cont("PEBS fmt0%c, ", pebs_type);
1598 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1599 /*
1600 * Using >PAGE_SIZE buffers makes the WRMSR to
1601 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1602 * mysteriously hang on Core2.
1603 *
1604 * As a workaround, we don't do this.
1605 */
1606 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1607 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1608 break;
1609
1610 case 1:
1611 pr_cont("PEBS fmt1%c, ", pebs_type);
1612 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1613 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1614 break;
1615
1616 case 2:
1617 pr_cont("PEBS fmt2%c, ", pebs_type);
1618 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1619 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1620 break;
1621
1622 case 3:
1623 pr_cont("PEBS fmt3%c, ", pebs_type);
1624 x86_pmu.pebs_record_size =
1625 sizeof(struct pebs_record_skl);
1626 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1627 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1628 break;
1629
1630 default:
1631 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1632 x86_pmu.pebs = 0;
1633 }
1634 }
1635 }
1636
perf_restore_debug_store(void)1637 void perf_restore_debug_store(void)
1638 {
1639 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1640
1641 if (!x86_pmu.bts && !x86_pmu.pebs)
1642 return;
1643
1644 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1645 }
1646