1 /* 2 * vsp1_regs.h -- R-Car VSP1 Registers Definitions 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 10 * as published by the Free Software Foundation. 11 */ 12 13 #ifndef __VSP1_REGS_H__ 14 #define __VSP1_REGS_H__ 15 16 /* ----------------------------------------------------------------------------- 17 * General Control Registers 18 */ 19 20 #define VI6_CMD(n) (0x0000 + (n) * 4) 21 #define VI6_CMD_UPDHDR (1 << 4) 22 #define VI6_CMD_STRCMD (1 << 0) 23 24 #define VI6_CLK_DCSWT 0x0018 25 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8) 26 #define VI6_CLK_DCSWT_CSTPW_SHIFT 8 27 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0) 28 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0 29 30 #define VI6_SRESET 0x0028 31 #define VI6_SRESET_SRTS(n) (1 << (n)) 32 33 #define VI6_STATUS 0x0038 34 #define VI6_STATUS_SYS_ACT(n) (1 << ((n) + 8)) 35 36 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) 37 #define VI6_WFP_IRQ_ENB_DFEE (1 << 1) 38 #define VI6_WFP_IRQ_ENB_FREE (1 << 0) 39 40 #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12) 41 #define VI6_WFP_IRQ_STA_DFE (1 << 1) 42 #define VI6_WFP_IRQ_STA_FRE (1 << 0) 43 44 #define VI6_DISP_IRQ_ENB 0x0078 45 #define VI6_DISP_IRQ_ENB_DSTE (1 << 8) 46 #define VI6_DISP_IRQ_ENB_MAEE (1 << 5) 47 #define VI6_DISP_IRQ_ENB_LNEE(n) (1 << (n)) 48 49 #define VI6_DISP_IRQ_STA 0x007c 50 #define VI6_DISP_IRQ_STA_DST (1 << 8) 51 #define VI6_DISP_IRQ_STA_MAE (1 << 5) 52 #define VI6_DISP_IRQ_STA_LNE(n) (1 << (n)) 53 54 #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4) 55 #define VI6_WPF_LINE_COUNT_MASK (0x1fffff << 0) 56 57 /* ----------------------------------------------------------------------------- 58 * Display List Control Registers 59 */ 60 61 #define VI6_DL_CTRL 0x0100 62 #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16) 63 #define VI6_DL_CTRL_AR_WAIT_SHIFT 16 64 #define VI6_DL_CTRL_DC2 (1 << 12) 65 #define VI6_DL_CTRL_DC1 (1 << 8) 66 #define VI6_DL_CTRL_DC0 (1 << 4) 67 #define VI6_DL_CTRL_CFM0 (1 << 2) 68 #define VI6_DL_CTRL_NH0 (1 << 1) 69 #define VI6_DL_CTRL_DLE (1 << 0) 70 71 #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4) 72 73 #define VI6_DL_SWAP 0x0114 74 #define VI6_DL_SWAP_LWS (1 << 2) 75 #define VI6_DL_SWAP_WDS (1 << 1) 76 #define VI6_DL_SWAP_BTS (1 << 0) 77 78 #define VI6_DL_EXT_CTRL 0x011c 79 #define VI6_DL_EXT_CTRL_NWE (1 << 16) 80 #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8) 81 #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8 82 #define VI6_DL_EXT_CTRL_DLPRI (1 << 5) 83 #define VI6_DL_EXT_CTRL_EXPRI (1 << 4) 84 #define VI6_DL_EXT_CTRL_EXT (1 << 0) 85 86 #define VI6_DL_BODY_SIZE 0x0120 87 #define VI6_DL_BODY_SIZE_UPD (1 << 24) 88 #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0) 89 #define VI6_DL_BODY_SIZE_BS_SHIFT 0 90 91 /* ----------------------------------------------------------------------------- 92 * RPF Control Registers 93 */ 94 95 #define VI6_RPF_OFFSET 0x100 96 97 #define VI6_RPF_SRC_BSIZE 0x0300 98 #define VI6_RPF_SRC_BSIZE_BHSIZE_MASK (0x1fff << 16) 99 #define VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT 16 100 #define VI6_RPF_SRC_BSIZE_BVSIZE_MASK (0x1fff << 0) 101 #define VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT 0 102 103 #define VI6_RPF_SRC_ESIZE 0x0304 104 #define VI6_RPF_SRC_ESIZE_EHSIZE_MASK (0x1fff << 16) 105 #define VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT 16 106 #define VI6_RPF_SRC_ESIZE_EVSIZE_MASK (0x1fff << 0) 107 #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0 108 109 #define VI6_RPF_INFMT 0x0308 110 #define VI6_RPF_INFMT_VIR (1 << 28) 111 #define VI6_RPF_INFMT_CIPM (1 << 16) 112 #define VI6_RPF_INFMT_SPYCS (1 << 15) 113 #define VI6_RPF_INFMT_SPUVS (1 << 14) 114 #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12) 115 #define VI6_RPF_INFMT_CEXT_EXT (1 << 12) 116 #define VI6_RPF_INFMT_CEXT_ONE (2 << 12) 117 #define VI6_RPF_INFMT_CEXT_MASK (3 << 12) 118 #define VI6_RPF_INFMT_RDTM_BT601 (0 << 9) 119 #define VI6_RPF_INFMT_RDTM_BT601_EXT (1 << 9) 120 #define VI6_RPF_INFMT_RDTM_BT709 (2 << 9) 121 #define VI6_RPF_INFMT_RDTM_BT709_EXT (3 << 9) 122 #define VI6_RPF_INFMT_RDTM_MASK (7 << 9) 123 #define VI6_RPF_INFMT_CSC (1 << 8) 124 #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0) 125 #define VI6_RPF_INFMT_RDFMT_SHIFT 0 126 127 #define VI6_RPF_DSWAP 0x030c 128 #define VI6_RPF_DSWAP_A_LLS (1 << 11) 129 #define VI6_RPF_DSWAP_A_LWS (1 << 10) 130 #define VI6_RPF_DSWAP_A_WDS (1 << 9) 131 #define VI6_RPF_DSWAP_A_BTS (1 << 8) 132 #define VI6_RPF_DSWAP_P_LLS (1 << 3) 133 #define VI6_RPF_DSWAP_P_LWS (1 << 2) 134 #define VI6_RPF_DSWAP_P_WDS (1 << 1) 135 #define VI6_RPF_DSWAP_P_BTS (1 << 0) 136 137 #define VI6_RPF_LOC 0x0310 138 #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16) 139 #define VI6_RPF_LOC_HCOORD_SHIFT 16 140 #define VI6_RPF_LOC_VCOORD_MASK (0x1fff << 0) 141 #define VI6_RPF_LOC_VCOORD_SHIFT 0 142 143 #define VI6_RPF_ALPH_SEL 0x0314 144 #define VI6_RPF_ALPH_SEL_ASEL_PACKED (0 << 28) 145 #define VI6_RPF_ALPH_SEL_ASEL_8B_PLANE (1 << 28) 146 #define VI6_RPF_ALPH_SEL_ASEL_SELECT (2 << 28) 147 #define VI6_RPF_ALPH_SEL_ASEL_1B_PLANE (3 << 28) 148 #define VI6_RPF_ALPH_SEL_ASEL_FIXED (4 << 28) 149 #define VI6_RPF_ALPH_SEL_ASEL_MASK (7 << 28) 150 #define VI6_RPF_ALPH_SEL_ASEL_SHIFT 28 151 #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24) 152 #define VI6_RPF_ALPH_SEL_IROP_SHIFT 24 153 #define VI6_RPF_ALPH_SEL_BSEL (1 << 23) 154 #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18) 155 #define VI6_RPF_ALPH_SEL_AEXT_EXT (1 << 18) 156 #define VI6_RPF_ALPH_SEL_AEXT_ONE (2 << 18) 157 #define VI6_RPF_ALPH_SEL_AEXT_MASK (3 << 18) 158 #define VI6_RPF_ALPH_SEL_ALPHA1_MASK (0xff << 8) 159 #define VI6_RPF_ALPH_SEL_ALPHA1_SHIFT 8 160 #define VI6_RPF_ALPH_SEL_ALPHA0_MASK (0xff << 0) 161 #define VI6_RPF_ALPH_SEL_ALPHA0_SHIFT 0 162 163 #define VI6_RPF_VRTCOL_SET 0x0318 164 #define VI6_RPF_VRTCOL_SET_LAYA_MASK (0xff << 24) 165 #define VI6_RPF_VRTCOL_SET_LAYA_SHIFT 24 166 #define VI6_RPF_VRTCOL_SET_LAYR_MASK (0xff << 16) 167 #define VI6_RPF_VRTCOL_SET_LAYR_SHIFT 16 168 #define VI6_RPF_VRTCOL_SET_LAYG_MASK (0xff << 8) 169 #define VI6_RPF_VRTCOL_SET_LAYG_SHIFT 8 170 #define VI6_RPF_VRTCOL_SET_LAYB_MASK (0xff << 0) 171 #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0 172 173 #define VI6_RPF_MSK_CTRL 0x031c 174 #define VI6_RPF_MSK_CTRL_MSK_EN (1 << 24) 175 #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16) 176 #define VI6_RPF_MSK_CTRL_MGR_SHIFT 16 177 #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8) 178 #define VI6_RPF_MSK_CTRL_MGG_SHIFT 8 179 #define VI6_RPF_MSK_CTRL_MGB_MASK (0xff << 0) 180 #define VI6_RPF_MSK_CTRL_MGB_SHIFT 0 181 182 #define VI6_RPF_MSK_SET0 0x0320 183 #define VI6_RPF_MSK_SET1 0x0324 184 #define VI6_RPF_MSK_SET_MSA_MASK (0xff << 24) 185 #define VI6_RPF_MSK_SET_MSA_SHIFT 24 186 #define VI6_RPF_MSK_SET_MSR_MASK (0xff << 16) 187 #define VI6_RPF_MSK_SET_MSR_SHIFT 16 188 #define VI6_RPF_MSK_SET_MSG_MASK (0xff << 8) 189 #define VI6_RPF_MSK_SET_MSG_SHIFT 8 190 #define VI6_RPF_MSK_SET_MSB_MASK (0xff << 0) 191 #define VI6_RPF_MSK_SET_MSB_SHIFT 0 192 193 #define VI6_RPF_CKEY_CTRL 0x0328 194 #define VI6_RPF_CKEY_CTRL_CV (1 << 4) 195 #define VI6_RPF_CKEY_CTRL_SAPE1 (1 << 1) 196 #define VI6_RPF_CKEY_CTRL_SAPE0 (1 << 0) 197 198 #define VI6_RPF_CKEY_SET0 0x032c 199 #define VI6_RPF_CKEY_SET1 0x0330 200 #define VI6_RPF_CKEY_SET_AP_MASK (0xff << 24) 201 #define VI6_RPF_CKEY_SET_AP_SHIFT 24 202 #define VI6_RPF_CKEY_SET_R_MASK (0xff << 16) 203 #define VI6_RPF_CKEY_SET_R_SHIFT 16 204 #define VI6_RPF_CKEY_SET_GY_MASK (0xff << 8) 205 #define VI6_RPF_CKEY_SET_GY_SHIFT 8 206 #define VI6_RPF_CKEY_SET_B_MASK (0xff << 0) 207 #define VI6_RPF_CKEY_SET_B_SHIFT 0 208 209 #define VI6_RPF_SRCM_PSTRIDE 0x0334 210 #define VI6_RPF_SRCM_PSTRIDE_Y_SHIFT 16 211 #define VI6_RPF_SRCM_PSTRIDE_C_SHIFT 0 212 213 #define VI6_RPF_SRCM_ASTRIDE 0x0338 214 #define VI6_RPF_SRCM_PSTRIDE_A_SHIFT 0 215 216 #define VI6_RPF_SRCM_ADDR_Y 0x033c 217 #define VI6_RPF_SRCM_ADDR_C0 0x0340 218 #define VI6_RPF_SRCM_ADDR_C1 0x0344 219 #define VI6_RPF_SRCM_ADDR_AI 0x0348 220 221 #define VI6_RPF_MULT_ALPHA 0x036c 222 #define VI6_RPF_MULT_ALPHA_A_MMD_NONE (0 << 12) 223 #define VI6_RPF_MULT_ALPHA_A_MMD_RATIO (1 << 12) 224 #define VI6_RPF_MULT_ALPHA_P_MMD_NONE (0 << 8) 225 #define VI6_RPF_MULT_ALPHA_P_MMD_RATIO (1 << 8) 226 #define VI6_RPF_MULT_ALPHA_P_MMD_IMAGE (2 << 8) 227 #define VI6_RPF_MULT_ALPHA_P_MMD_BOTH (3 << 8) 228 #define VI6_RPF_MULT_ALPHA_RATIO_MASK (0xff < 0) 229 #define VI6_RPF_MULT_ALPHA_RATIO_SHIFT 0 230 231 /* ----------------------------------------------------------------------------- 232 * WPF Control Registers 233 */ 234 235 #define VI6_WPF_OFFSET 0x100 236 237 #define VI6_WPF_SRCRPF 0x1000 238 #define VI6_WPF_SRCRPF_VIRACT_DIS (0 << 28) 239 #define VI6_WPF_SRCRPF_VIRACT_SUB (1 << 28) 240 #define VI6_WPF_SRCRPF_VIRACT_MST (2 << 28) 241 #define VI6_WPF_SRCRPF_VIRACT_MASK (3 << 28) 242 #define VI6_WPF_SRCRPF_VIRACT2_DIS (0 << 24) 243 #define VI6_WPF_SRCRPF_VIRACT2_SUB (1 << 24) 244 #define VI6_WPF_SRCRPF_VIRACT2_MST (2 << 24) 245 #define VI6_WPF_SRCRPF_VIRACT2_MASK (3 << 24) 246 #define VI6_WPF_SRCRPF_RPF_ACT_DIS(n) (0 << ((n) * 2)) 247 #define VI6_WPF_SRCRPF_RPF_ACT_SUB(n) (1 << ((n) * 2)) 248 #define VI6_WPF_SRCRPF_RPF_ACT_MST(n) (2 << ((n) * 2)) 249 #define VI6_WPF_SRCRPF_RPF_ACT_MASK(n) (3 << ((n) * 2)) 250 251 #define VI6_WPF_HSZCLIP 0x1004 252 #define VI6_WPF_VSZCLIP 0x1008 253 #define VI6_WPF_SZCLIP_EN (1 << 28) 254 #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16) 255 #define VI6_WPF_SZCLIP_OFST_SHIFT 16 256 #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0) 257 #define VI6_WPF_SZCLIP_SIZE_SHIFT 0 258 259 #define VI6_WPF_OUTFMT 0x100c 260 #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24) 261 #define VI6_WPF_OUTFMT_PDV_SHIFT 24 262 #define VI6_WPF_OUTFMT_PXA (1 << 23) 263 #define VI6_WPF_OUTFMT_ROT (1 << 18) 264 #define VI6_WPF_OUTFMT_HFLP (1 << 17) 265 #define VI6_WPF_OUTFMT_FLP (1 << 16) 266 #define VI6_WPF_OUTFMT_SPYCS (1 << 15) 267 #define VI6_WPF_OUTFMT_SPUVS (1 << 14) 268 #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12) 269 #define VI6_WPF_OUTFMT_DITH_EN (3 << 12) 270 #define VI6_WPF_OUTFMT_DITH_MASK (3 << 12) 271 #define VI6_WPF_OUTFMT_WRTM_BT601 (0 << 9) 272 #define VI6_WPF_OUTFMT_WRTM_BT601_EXT (1 << 9) 273 #define VI6_WPF_OUTFMT_WRTM_BT709 (2 << 9) 274 #define VI6_WPF_OUTFMT_WRTM_BT709_EXT (3 << 9) 275 #define VI6_WPF_OUTFMT_WRTM_MASK (7 << 9) 276 #define VI6_WPF_OUTFMT_CSC (1 << 8) 277 #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0) 278 #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0 279 280 #define VI6_WPF_DSWAP 0x1010 281 #define VI6_WPF_DSWAP_P_LLS (1 << 3) 282 #define VI6_WPF_DSWAP_P_LWS (1 << 2) 283 #define VI6_WPF_DSWAP_P_WDS (1 << 1) 284 #define VI6_WPF_DSWAP_P_BTS (1 << 0) 285 286 #define VI6_WPF_RNDCTRL 0x1014 287 #define VI6_WPF_RNDCTRL_CBRM (1 << 28) 288 #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24) 289 #define VI6_WPF_RNDCTRL_ABRM_ROUND (1 << 24) 290 #define VI6_WPF_RNDCTRL_ABRM_THRESH (2 << 24) 291 #define VI6_WPF_RNDCTRL_ABRM_MASK (3 << 24) 292 #define VI6_WPF_RNDCTRL_ATHRESH_MASK (0xff << 16) 293 #define VI6_WPF_RNDCTRL_ATHRESH_SHIFT 16 294 #define VI6_WPF_RNDCTRL_CLMD_FULL (0 << 12) 295 #define VI6_WPF_RNDCTRL_CLMD_CLIP (1 << 12) 296 #define VI6_WPF_RNDCTRL_CLMD_EXT (2 << 12) 297 #define VI6_WPF_RNDCTRL_CLMD_MASK (3 << 12) 298 299 #define VI6_WPF_ROT_CTRL 0x1018 300 #define VI6_WPF_ROT_CTRL_LN16 (1 << 17) 301 #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0) 302 #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0 303 304 #define VI6_WPF_DSTM_STRIDE_Y 0x101c 305 #define VI6_WPF_DSTM_STRIDE_C 0x1020 306 #define VI6_WPF_DSTM_ADDR_Y 0x1024 307 #define VI6_WPF_DSTM_ADDR_C0 0x1028 308 #define VI6_WPF_DSTM_ADDR_C1 0x102c 309 310 #define VI6_WPF_WRBCK_CTRL 0x1034 311 #define VI6_WPF_WRBCK_CTRL_WBMD (1 << 0) 312 313 /* ----------------------------------------------------------------------------- 314 * DPR Control Registers 315 */ 316 317 #define VI6_DPR_RPF_ROUTE(n) (0x2000 + (n) * 4) 318 319 #define VI6_DPR_WPF_FPORCH(n) (0x2014 + (n) * 4) 320 #define VI6_DPR_WPF_FPORCH_FP_WPFN (5 << 8) 321 322 #define VI6_DPR_SRU_ROUTE 0x2024 323 #define VI6_DPR_UDS_ROUTE(n) (0x2028 + (n) * 4) 324 #define VI6_DPR_LUT_ROUTE 0x203c 325 #define VI6_DPR_CLU_ROUTE 0x2040 326 #define VI6_DPR_HST_ROUTE 0x2044 327 #define VI6_DPR_HSI_ROUTE 0x2048 328 #define VI6_DPR_BRU_ROUTE 0x204c 329 #define VI6_DPR_ILV_BRS_ROUTE 0x2050 330 #define VI6_DPR_ROUTE_BRSSEL (1 << 28) 331 #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16) 332 #define VI6_DPR_ROUTE_FXA_SHIFT 16 333 #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8) 334 #define VI6_DPR_ROUTE_FP_SHIFT 8 335 #define VI6_DPR_ROUTE_RT_MASK (0x3f << 0) 336 #define VI6_DPR_ROUTE_RT_SHIFT 0 337 338 #define VI6_DPR_HGO_SMPPT 0x2054 339 #define VI6_DPR_HGT_SMPPT 0x2058 340 #define VI6_DPR_SMPPT_TGW_MASK (7 << 8) 341 #define VI6_DPR_SMPPT_TGW_SHIFT 8 342 #define VI6_DPR_SMPPT_PT_MASK (0x3f << 0) 343 #define VI6_DPR_SMPPT_PT_SHIFT 0 344 345 #define VI6_DPR_NODE_RPF(n) (n) 346 #define VI6_DPR_NODE_SRU 16 347 #define VI6_DPR_NODE_UDS(n) (17 + (n)) 348 #define VI6_DPR_NODE_LUT 22 349 #define VI6_DPR_NODE_BRU_IN(n) (((n) <= 3) ? 23 + (n) : 49) 350 #define VI6_DPR_NODE_BRU_OUT 27 351 #define VI6_DPR_NODE_CLU 29 352 #define VI6_DPR_NODE_HST 30 353 #define VI6_DPR_NODE_HSI 31 354 #define VI6_DPR_NODE_BRS_IN(n) (38 + (n)) 355 #define VI6_DPR_NODE_LIF 55 /* Gen2 only */ 356 #define VI6_DPR_NODE_WPF(n) (56 + (n)) 357 #define VI6_DPR_NODE_UNUSED 63 358 359 /* ----------------------------------------------------------------------------- 360 * SRU Control Registers 361 */ 362 363 #define VI6_SRU_CTRL0 0x2200 364 #define VI6_SRU_CTRL0_PARAM0_MASK (0x1ff << 16) 365 #define VI6_SRU_CTRL0_PARAM0_SHIFT 16 366 #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8) 367 #define VI6_SRU_CTRL0_PARAM1_SHIFT 8 368 #define VI6_SRU_CTRL0_MODE_UPSCALE (4 << 4) 369 #define VI6_SRU_CTRL0_PARAM2 (1 << 3) 370 #define VI6_SRU_CTRL0_PARAM3 (1 << 2) 371 #define VI6_SRU_CTRL0_PARAM4 (1 << 1) 372 #define VI6_SRU_CTRL0_EN (1 << 0) 373 374 #define VI6_SRU_CTRL1 0x2204 375 #define VI6_SRU_CTRL1_PARAM5 0x7ff 376 377 #define VI6_SRU_CTRL2 0x2208 378 #define VI6_SRU_CTRL2_PARAM6_SHIFT 16 379 #define VI6_SRU_CTRL2_PARAM7_SHIFT 8 380 #define VI6_SRU_CTRL2_PARAM8_SHIFT 0 381 382 /* ----------------------------------------------------------------------------- 383 * UDS Control Registers 384 */ 385 386 #define VI6_UDS_OFFSET 0x100 387 388 #define VI6_UDS_CTRL 0x2300 389 #define VI6_UDS_CTRL_AMD (1 << 30) 390 #define VI6_UDS_CTRL_FMD (1 << 29) 391 #define VI6_UDS_CTRL_BLADV (1 << 28) 392 #define VI6_UDS_CTRL_AON (1 << 25) 393 #define VI6_UDS_CTRL_ATHON (1 << 24) 394 #define VI6_UDS_CTRL_BC (1 << 20) 395 #define VI6_UDS_CTRL_NE_A (1 << 19) 396 #define VI6_UDS_CTRL_NE_RCR (1 << 18) 397 #define VI6_UDS_CTRL_NE_GY (1 << 17) 398 #define VI6_UDS_CTRL_NE_BCB (1 << 16) 399 #define VI6_UDS_CTRL_AMDSLH (1 << 2) 400 #define VI6_UDS_CTRL_TDIPC (1 << 1) 401 402 #define VI6_UDS_SCALE 0x2304 403 #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28) 404 #define VI6_UDS_SCALE_HMANT_SHIFT 28 405 #define VI6_UDS_SCALE_HFRAC_MASK (0xfff << 16) 406 #define VI6_UDS_SCALE_HFRAC_SHIFT 16 407 #define VI6_UDS_SCALE_VMANT_MASK (0xf << 12) 408 #define VI6_UDS_SCALE_VMANT_SHIFT 12 409 #define VI6_UDS_SCALE_VFRAC_MASK (0xfff << 0) 410 #define VI6_UDS_SCALE_VFRAC_SHIFT 0 411 412 #define VI6_UDS_ALPTH 0x2308 413 #define VI6_UDS_ALPTH_TH1_MASK (0xff << 8) 414 #define VI6_UDS_ALPTH_TH1_SHIFT 8 415 #define VI6_UDS_ALPTH_TH0_MASK (0xff << 0) 416 #define VI6_UDS_ALPTH_TH0_SHIFT 0 417 418 #define VI6_UDS_ALPVAL 0x230c 419 #define VI6_UDS_ALPVAL_VAL2_MASK (0xff << 16) 420 #define VI6_UDS_ALPVAL_VAL2_SHIFT 16 421 #define VI6_UDS_ALPVAL_VAL1_MASK (0xff << 8) 422 #define VI6_UDS_ALPVAL_VAL1_SHIFT 8 423 #define VI6_UDS_ALPVAL_VAL0_MASK (0xff << 0) 424 #define VI6_UDS_ALPVAL_VAL0_SHIFT 0 425 426 #define VI6_UDS_PASS_BWIDTH 0x2310 427 #define VI6_UDS_PASS_BWIDTH_H_MASK (0x7f << 16) 428 #define VI6_UDS_PASS_BWIDTH_H_SHIFT 16 429 #define VI6_UDS_PASS_BWIDTH_V_MASK (0x7f << 0) 430 #define VI6_UDS_PASS_BWIDTH_V_SHIFT 0 431 432 #define VI6_UDS_HPHASE 0x2314 433 #define VI6_UDS_HPHASE_HSTP_MASK (0xfff << 16) 434 #define VI6_UDS_HPHASE_HSTP_SHIFT 16 435 #define VI6_UDS_HPHASE_HEDP_MASK (0xfff << 0) 436 #define VI6_UDS_HPHASE_HEDP_SHIFT 0 437 438 #define VI6_UDS_IPC 0x2318 439 #define VI6_UDS_IPC_FIELD (1 << 27) 440 #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0) 441 #define VI6_UDS_IPC_VEDP_SHIFT 0 442 443 #define VI6_UDS_HSZCLIP 0x231c 444 #define VI6_UDS_HSZCLIP_HCEN (1 << 28) 445 #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16) 446 #define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT 16 447 #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK (0x1fff << 0) 448 #define VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT 0 449 450 #define VI6_UDS_CLIP_SIZE 0x2324 451 #define VI6_UDS_CLIP_SIZE_HSIZE_MASK (0x1fff << 16) 452 #define VI6_UDS_CLIP_SIZE_HSIZE_SHIFT 16 453 #define VI6_UDS_CLIP_SIZE_VSIZE_MASK (0x1fff << 0) 454 #define VI6_UDS_CLIP_SIZE_VSIZE_SHIFT 0 455 456 #define VI6_UDS_FILL_COLOR 0x2328 457 #define VI6_UDS_FILL_COLOR_RFILC_MASK (0xff << 16) 458 #define VI6_UDS_FILL_COLOR_RFILC_SHIFT 16 459 #define VI6_UDS_FILL_COLOR_GFILC_MASK (0xff << 8) 460 #define VI6_UDS_FILL_COLOR_GFILC_SHIFT 8 461 #define VI6_UDS_FILL_COLOR_BFILC_MASK (0xff << 0) 462 #define VI6_UDS_FILL_COLOR_BFILC_SHIFT 0 463 464 /* ----------------------------------------------------------------------------- 465 * LUT Control Registers 466 */ 467 468 #define VI6_LUT_CTRL 0x2800 469 #define VI6_LUT_CTRL_EN (1 << 0) 470 471 /* ----------------------------------------------------------------------------- 472 * CLU Control Registers 473 */ 474 475 #define VI6_CLU_CTRL 0x2900 476 #define VI6_CLU_CTRL_AAI (1 << 28) 477 #define VI6_CLU_CTRL_MVS (1 << 24) 478 #define VI6_CLU_CTRL_AX1I_2D (3 << 14) 479 #define VI6_CLU_CTRL_AX2I_2D (1 << 12) 480 #define VI6_CLU_CTRL_OS0_2D (3 << 8) 481 #define VI6_CLU_CTRL_OS1_2D (1 << 6) 482 #define VI6_CLU_CTRL_OS2_2D (3 << 4) 483 #define VI6_CLU_CTRL_M2D (1 << 1) 484 #define VI6_CLU_CTRL_EN (1 << 0) 485 486 /* ----------------------------------------------------------------------------- 487 * HST Control Registers 488 */ 489 490 #define VI6_HST_CTRL 0x2a00 491 #define VI6_HST_CTRL_EN (1 << 0) 492 493 /* ----------------------------------------------------------------------------- 494 * HSI Control Registers 495 */ 496 497 #define VI6_HSI_CTRL 0x2b00 498 #define VI6_HSI_CTRL_EN (1 << 0) 499 500 /* ----------------------------------------------------------------------------- 501 * BRS and BRU Control Registers 502 */ 503 504 #define VI6_ROP_NOP 0 505 #define VI6_ROP_AND 1 506 #define VI6_ROP_AND_REV 2 507 #define VI6_ROP_COPY 3 508 #define VI6_ROP_AND_INV 4 509 #define VI6_ROP_CLEAR 5 510 #define VI6_ROP_XOR 6 511 #define VI6_ROP_OR 7 512 #define VI6_ROP_NOR 8 513 #define VI6_ROP_EQUIV 9 514 #define VI6_ROP_INVERT 10 515 #define VI6_ROP_OR_REV 11 516 #define VI6_ROP_COPY_INV 12 517 #define VI6_ROP_OR_INV 13 518 #define VI6_ROP_NAND 14 519 #define VI6_ROP_SET 15 520 521 #define VI6_BRU_BASE 0x2c00 522 #define VI6_BRS_BASE 0x3900 523 524 #define VI6_BRU_INCTRL 0x0000 525 #define VI6_BRU_INCTRL_NRM (1 << 28) 526 #define VI6_BRU_INCTRL_DnON (1 << (16 + (n))) 527 #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4)) 528 #define VI6_BRU_INCTRL_DITHn_18BPP (1 << ((n) * 4)) 529 #define VI6_BRU_INCTRL_DITHn_16BPP (2 << ((n) * 4)) 530 #define VI6_BRU_INCTRL_DITHn_15BPP (3 << ((n) * 4)) 531 #define VI6_BRU_INCTRL_DITHn_12BPP (4 << ((n) * 4)) 532 #define VI6_BRU_INCTRL_DITHn_8BPP (5 << ((n) * 4)) 533 #define VI6_BRU_INCTRL_DITHn_MASK (7 << ((n) * 4)) 534 #define VI6_BRU_INCTRL_DITHn_SHIFT ((n) * 4) 535 536 #define VI6_BRU_VIRRPF_SIZE 0x0004 537 #define VI6_BRU_VIRRPF_SIZE_HSIZE_MASK (0x1fff << 16) 538 #define VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT 16 539 #define VI6_BRU_VIRRPF_SIZE_VSIZE_MASK (0x1fff << 0) 540 #define VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT 0 541 542 #define VI6_BRU_VIRRPF_LOC 0x0008 543 #define VI6_BRU_VIRRPF_LOC_HCOORD_MASK (0x1fff << 16) 544 #define VI6_BRU_VIRRPF_LOC_HCOORD_SHIFT 16 545 #define VI6_BRU_VIRRPF_LOC_VCOORD_MASK (0x1fff << 0) 546 #define VI6_BRU_VIRRPF_LOC_VCOORD_SHIFT 0 547 548 #define VI6_BRU_VIRRPF_COL 0x000c 549 #define VI6_BRU_VIRRPF_COL_A_MASK (0xff << 24) 550 #define VI6_BRU_VIRRPF_COL_A_SHIFT 24 551 #define VI6_BRU_VIRRPF_COL_RCR_MASK (0xff << 16) 552 #define VI6_BRU_VIRRPF_COL_RCR_SHIFT 16 553 #define VI6_BRU_VIRRPF_COL_GY_MASK (0xff << 8) 554 #define VI6_BRU_VIRRPF_COL_GY_SHIFT 8 555 #define VI6_BRU_VIRRPF_COL_BCB_MASK (0xff << 0) 556 #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0 557 558 #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4)) 559 #define VI6_BRU_CTRL_RBC (1 << 31) 560 #define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) 561 #define VI6_BRU_CTRL_DSTSEL_VRPF (4 << 20) 562 #define VI6_BRU_CTRL_DSTSEL_MASK (7 << 20) 563 #define VI6_BRU_CTRL_SRCSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 16) 564 #define VI6_BRU_CTRL_SRCSEL_VRPF (4 << 16) 565 #define VI6_BRU_CTRL_SRCSEL_MASK (7 << 16) 566 #define VI6_BRU_CTRL_CROP(rop) ((rop) << 4) 567 #define VI6_BRU_CTRL_CROP_MASK (0xf << 4) 568 #define VI6_BRU_CTRL_AROP(rop) ((rop) << 0) 569 #define VI6_BRU_CTRL_AROP_MASK (0xf << 0) 570 571 #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4)) 572 #define VI6_BRU_BLD_CBES (1 << 31) 573 #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28) 574 #define VI6_BRU_BLD_CCMDX_255_DST_A (1 << 28) 575 #define VI6_BRU_BLD_CCMDX_SRC_A (2 << 28) 576 #define VI6_BRU_BLD_CCMDX_255_SRC_A (3 << 28) 577 #define VI6_BRU_BLD_CCMDX_COEFX (4 << 28) 578 #define VI6_BRU_BLD_CCMDX_MASK (7 << 28) 579 #define VI6_BRU_BLD_CCMDY_DST_A (0 << 24) 580 #define VI6_BRU_BLD_CCMDY_255_DST_A (1 << 24) 581 #define VI6_BRU_BLD_CCMDY_SRC_A (2 << 24) 582 #define VI6_BRU_BLD_CCMDY_255_SRC_A (3 << 24) 583 #define VI6_BRU_BLD_CCMDY_COEFY (4 << 24) 584 #define VI6_BRU_BLD_CCMDY_MASK (7 << 24) 585 #define VI6_BRU_BLD_CCMDY_SHIFT 24 586 #define VI6_BRU_BLD_ABES (1 << 23) 587 #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20) 588 #define VI6_BRU_BLD_ACMDX_255_DST_A (1 << 20) 589 #define VI6_BRU_BLD_ACMDX_SRC_A (2 << 20) 590 #define VI6_BRU_BLD_ACMDX_255_SRC_A (3 << 20) 591 #define VI6_BRU_BLD_ACMDX_COEFX (4 << 20) 592 #define VI6_BRU_BLD_ACMDX_MASK (7 << 20) 593 #define VI6_BRU_BLD_ACMDY_DST_A (0 << 16) 594 #define VI6_BRU_BLD_ACMDY_255_DST_A (1 << 16) 595 #define VI6_BRU_BLD_ACMDY_SRC_A (2 << 16) 596 #define VI6_BRU_BLD_ACMDY_255_SRC_A (3 << 16) 597 #define VI6_BRU_BLD_ACMDY_COEFY (4 << 16) 598 #define VI6_BRU_BLD_ACMDY_MASK (7 << 16) 599 #define VI6_BRU_BLD_COEFX_MASK (0xff << 8) 600 #define VI6_BRU_BLD_COEFX_SHIFT 8 601 #define VI6_BRU_BLD_COEFY_MASK (0xff << 0) 602 #define VI6_BRU_BLD_COEFY_SHIFT 0 603 604 #define VI6_BRU_ROP 0x0030 /* Only available on BRU */ 605 #define VI6_BRU_ROP_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) 606 #define VI6_BRU_ROP_DSTSEL_VRPF (4 << 20) 607 #define VI6_BRU_ROP_DSTSEL_MASK (7 << 20) 608 #define VI6_BRU_ROP_CROP(rop) ((rop) << 4) 609 #define VI6_BRU_ROP_CROP_MASK (0xf << 4) 610 #define VI6_BRU_ROP_AROP(rop) ((rop) << 0) 611 #define VI6_BRU_ROP_AROP_MASK (0xf << 0) 612 613 /* ----------------------------------------------------------------------------- 614 * HGO Control Registers 615 */ 616 617 #define VI6_HGO_OFFSET 0x3000 618 #define VI6_HGO_OFFSET_HOFFSET_SHIFT 16 619 #define VI6_HGO_OFFSET_VOFFSET_SHIFT 0 620 #define VI6_HGO_SIZE 0x3004 621 #define VI6_HGO_SIZE_HSIZE_SHIFT 16 622 #define VI6_HGO_SIZE_VSIZE_SHIFT 0 623 #define VI6_HGO_MODE 0x3008 624 #define VI6_HGO_MODE_STEP (1 << 10) 625 #define VI6_HGO_MODE_MAXRGB (1 << 7) 626 #define VI6_HGO_MODE_OFSB_R (1 << 6) 627 #define VI6_HGO_MODE_OFSB_G (1 << 5) 628 #define VI6_HGO_MODE_OFSB_B (1 << 4) 629 #define VI6_HGO_MODE_HRATIO_SHIFT 2 630 #define VI6_HGO_MODE_VRATIO_SHIFT 0 631 #define VI6_HGO_LB_TH 0x300c 632 #define VI6_HGO_LBn_H(n) (0x3010 + (n) * 8) 633 #define VI6_HGO_LBn_V(n) (0x3014 + (n) * 8) 634 #define VI6_HGO_R_HISTO(n) (0x3030 + (n) * 4) 635 #define VI6_HGO_R_MAXMIN 0x3130 636 #define VI6_HGO_R_SUM 0x3134 637 #define VI6_HGO_R_LB_DET 0x3138 638 #define VI6_HGO_G_HISTO(n) (0x3140 + (n) * 4) 639 #define VI6_HGO_G_MAXMIN 0x3240 640 #define VI6_HGO_G_SUM 0x3244 641 #define VI6_HGO_G_LB_DET 0x3248 642 #define VI6_HGO_B_HISTO(n) (0x3250 + (n) * 4) 643 #define VI6_HGO_B_MAXMIN 0x3350 644 #define VI6_HGO_B_SUM 0x3354 645 #define VI6_HGO_B_LB_DET 0x3358 646 #define VI6_HGO_EXT_HIST_ADDR 0x335c 647 #define VI6_HGO_EXT_HIST_DATA 0x3360 648 #define VI6_HGO_REGRST 0x33fc 649 #define VI6_HGO_REGRST_RCLEA (1 << 0) 650 651 /* ----------------------------------------------------------------------------- 652 * HGT Control Registers 653 */ 654 655 #define VI6_HGT_OFFSET 0x3400 656 #define VI6_HGT_OFFSET_HOFFSET_SHIFT 16 657 #define VI6_HGT_OFFSET_VOFFSET_SHIFT 0 658 #define VI6_HGT_SIZE 0x3404 659 #define VI6_HGT_SIZE_HSIZE_SHIFT 16 660 #define VI6_HGT_SIZE_VSIZE_SHIFT 0 661 #define VI6_HGT_MODE 0x3408 662 #define VI6_HGT_MODE_HRATIO_SHIFT 2 663 #define VI6_HGT_MODE_VRATIO_SHIFT 0 664 #define VI6_HGT_HUE_AREA(n) (0x340c + (n) * 4) 665 #define VI6_HGT_HUE_AREA_LOWER_SHIFT 16 666 #define VI6_HGT_HUE_AREA_UPPER_SHIFT 0 667 #define VI6_HGT_LB_TH 0x3424 668 #define VI6_HGT_LBn_H(n) (0x3438 + (n) * 8) 669 #define VI6_HGT_LBn_V(n) (0x342c + (n) * 8) 670 #define VI6_HGT_HISTO(m, n) (0x3450 + (m) * 128 + (n) * 4) 671 #define VI6_HGT_MAXMIN 0x3750 672 #define VI6_HGT_SUM 0x3754 673 #define VI6_HGT_LB_DET 0x3758 674 #define VI6_HGT_REGRST 0x37fc 675 #define VI6_HGT_REGRST_RCLEA (1 << 0) 676 677 /* ----------------------------------------------------------------------------- 678 * LIF Control Registers 679 */ 680 681 #define VI6_LIF_OFFSET (-0x100) 682 683 #define VI6_LIF_CTRL 0x3b00 684 #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16) 685 #define VI6_LIF_CTRL_OBTH_SHIFT 16 686 #define VI6_LIF_CTRL_CFMT (1 << 4) 687 #define VI6_LIF_CTRL_REQSEL (1 << 1) 688 #define VI6_LIF_CTRL_LIF_EN (1 << 0) 689 690 #define VI6_LIF_CSBTH 0x3b04 691 #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16) 692 #define VI6_LIF_CSBTH_HBTH_SHIFT 16 693 #define VI6_LIF_CSBTH_LBTH_MASK (0x7ff << 0) 694 #define VI6_LIF_CSBTH_LBTH_SHIFT 0 695 696 /* ----------------------------------------------------------------------------- 697 * Security Control Registers 698 */ 699 700 #define VI6_SECURITY_CTRL0 0x3d00 701 #define VI6_SECURITY_CTRL1 0x3d04 702 703 /* ----------------------------------------------------------------------------- 704 * IP Version Registers 705 */ 706 707 #define VI6_IP_VERSION 0x3f00 708 #define VI6_IP_VERSION_MODEL_MASK (0xff << 8) 709 #define VI6_IP_VERSION_MODEL_VSPS_H2 (0x09 << 8) 710 #define VI6_IP_VERSION_MODEL_VSPR_H2 (0x0a << 8) 711 #define VI6_IP_VERSION_MODEL_VSPD_GEN2 (0x0b << 8) 712 #define VI6_IP_VERSION_MODEL_VSPS_M2 (0x0c << 8) 713 #define VI6_IP_VERSION_MODEL_VSPS_V2H (0x12 << 8) 714 #define VI6_IP_VERSION_MODEL_VSPD_V2H (0x13 << 8) 715 #define VI6_IP_VERSION_MODEL_VSPI_GEN3 (0x14 << 8) 716 #define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8) 717 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8) 718 #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8) 719 #define VI6_IP_VERSION_MODEL_VSPD_V3 (0x18 << 8) 720 #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8) 721 #define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8) 722 #define VI6_IP_VERSION_SOC_MASK (0xff << 0) 723 #define VI6_IP_VERSION_SOC_H2 (0x01 << 0) 724 #define VI6_IP_VERSION_SOC_V2H (0x01 << 0) 725 #define VI6_IP_VERSION_SOC_V3M (0x01 << 0) 726 #define VI6_IP_VERSION_SOC_M2 (0x02 << 0) 727 #define VI6_IP_VERSION_SOC_M3W (0x02 << 0) 728 #define VI6_IP_VERSION_SOC_V3H (0x02 << 0) 729 #define VI6_IP_VERSION_SOC_H3 (0x03 << 0) 730 #define VI6_IP_VERSION_SOC_D3 (0x04 << 0) 731 #define VI6_IP_VERSION_SOC_M3N (0x04 << 0) 732 #define VI6_IP_VERSION_SOC_E3 (0x04 << 0) 733 734 /* ----------------------------------------------------------------------------- 735 * RPF CLUT Registers 736 */ 737 738 #define VI6_CLUT_TABLE 0x4000 739 740 /* ----------------------------------------------------------------------------- 741 * 1D LUT Registers 742 */ 743 744 #define VI6_LUT_TABLE 0x7000 745 746 /* ----------------------------------------------------------------------------- 747 * 3D LUT Registers 748 */ 749 750 #define VI6_CLU_ADDR 0x7400 751 #define VI6_CLU_DATA 0x7404 752 753 /* ----------------------------------------------------------------------------- 754 * Formats 755 */ 756 757 #define VI6_FMT_RGB_332 0x00 758 #define VI6_FMT_XRGB_4444 0x01 759 #define VI6_FMT_RGBX_4444 0x02 760 #define VI6_FMT_XRGB_1555 0x04 761 #define VI6_FMT_RGBX_5551 0x05 762 #define VI6_FMT_RGB_565 0x06 763 #define VI6_FMT_AXRGB_86666 0x07 764 #define VI6_FMT_RGBXA_66668 0x08 765 #define VI6_FMT_XRGBA_66668 0x09 766 #define VI6_FMT_ARGBX_86666 0x0a 767 #define VI6_FMT_AXRXGXB_8262626 0x0b 768 #define VI6_FMT_XRXGXBA_2626268 0x0c 769 #define VI6_FMT_ARXGXBX_8626262 0x0d 770 #define VI6_FMT_RXGXBXA_6262628 0x0e 771 #define VI6_FMT_XRGB_6666 0x0f 772 #define VI6_FMT_RGBX_6666 0x10 773 #define VI6_FMT_XRXGXB_262626 0x11 774 #define VI6_FMT_RXGXBX_626262 0x12 775 #define VI6_FMT_ARGB_8888 0x13 776 #define VI6_FMT_RGBA_8888 0x14 777 #define VI6_FMT_RGB_888 0x15 778 #define VI6_FMT_XRGXGB_763763 0x16 779 #define VI6_FMT_XXRGB_86666 0x17 780 #define VI6_FMT_BGR_888 0x18 781 #define VI6_FMT_ARGB_4444 0x19 782 #define VI6_FMT_RGBA_4444 0x1a 783 #define VI6_FMT_ARGB_1555 0x1b 784 #define VI6_FMT_RGBA_5551 0x1c 785 #define VI6_FMT_ABGR_4444 0x1d 786 #define VI6_FMT_BGRA_4444 0x1e 787 #define VI6_FMT_ABGR_1555 0x1f 788 #define VI6_FMT_BGRA_5551 0x20 789 #define VI6_FMT_XBXGXR_262626 0x21 790 #define VI6_FMT_ABGR_8888 0x22 791 #define VI6_FMT_XXRGB_88565 0x23 792 793 #define VI6_FMT_Y_UV_444 0x40 794 #define VI6_FMT_Y_UV_422 0x41 795 #define VI6_FMT_Y_UV_420 0x42 796 #define VI6_FMT_YUV_444 0x46 797 #define VI6_FMT_YUYV_422 0x47 798 #define VI6_FMT_YYUV_422 0x48 799 #define VI6_FMT_YUV_420 0x49 800 #define VI6_FMT_Y_U_V_444 0x4a 801 #define VI6_FMT_Y_U_V_422 0x4b 802 #define VI6_FMT_Y_U_V_420 0x4c 803 804 #endif /* __VSP1_REGS_H__ */ 805