| /drivers/clk/sunxi-ng/ |
| D | ccu_mp.h | 39 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
58 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
87 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
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| D | ccu_mux.h | 50 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
65 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
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| D | ccu_div.h | 120 _parents, _table, \ argument
138 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
147 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
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| D | ccu_nkm.h | 42 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
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| D | ccu_common.h | 42 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 147 #define MUX(_name, _parents, _offset, \ argument
154 #define MUX_FLAGS(_name, _parents, _offset,\ argument
161 #define MUX8(_name, _parents, _offset, \ argument
168 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
174 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
180 #define INT(_name, _parents, _offset, \ argument
187 #define INT_FLAGS(_name, _parents, _offset,\ argument
194 #define INT8(_name, _parents, _offset,\ argument
201 #define UART(_name, _parents, _offset,\ argument
208 #define UART8(_name, _parents, _offset,\ argument
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| D | clk-tegra30.c | 167 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
173 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
179 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
186 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
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| D | clk-tegra20.c | 144 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
151 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
158 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
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| D | clk-tegra114.c | 126 #define MUX8(_name, _parents, _offset, \ argument
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
109 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
113 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
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| /drivers/clk/ |
| D | clk-oxnas.c | 100 #define OXNAS_GATE(_name, _bit, _parents) \ argument
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| D | clk-stm32h7.c | 580 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\ argument
591 #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\ argument
1191 #define M_MCO_F(_name, _parents, _mux_offset, _mux_shift, _mux_width,\ argument
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| /drivers/clk/zte/ |
| D | clk.h | 26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
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