| /drivers/clk/sunxi-ng/ |
| D | ccu_div.h | 51 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
59 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
97 _table, _gate, _flags) \ argument
114 _table, _flags) \ argument
120 _parents, _table, \ argument
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| D | ccu_mux.h | 32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
50 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
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| /drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 114 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
129 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
134 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
138 #define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \ argument
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| /drivers/clk/zte/ |
| D | clk.h | 58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
73 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
143 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
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| /drivers/iio/health/ |
| D | afe440x.h | 125 #define AFE440X_TABLE_ATTR(_name, _table) \ argument
153 #define AFE440X_ATTR(_name, _field, _table) \ argument
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| /drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 171 #define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \ argument
205 #define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \ argument
271 #define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \ argument
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| D | clk-lpc32xx.c | 1114 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ argument
1135 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ argument
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| /drivers/regulator/ |
| D | bcm590xx-regulator.c | 157 #define BCM590XX_REG_TABLE(_name, _table) \ argument
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| /drivers/clk/tegra/ |
| D | clk.h | 594 _gate_flags, _table, _lock) \ argument
637 _clk_num, _gate_flags, _clk_id, _table, \ argument
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