1 /*
2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
4 *
5 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <linux/bitops.h>
20 #include <linux/bug.h>
21 #include <linux/compiler.h>
22 #include <linux/kernel.h>
23 #include <linux/mm.h>
24 #include <linux/smp.h>
25 #include <linux/spinlock.h>
26 #include <linux/stop_machine.h>
27 #include <linux/types.h>
28 #include <linux/uaccess.h>
29
30 #include <asm/cacheflush.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/fixmap.h>
33 #include <asm/insn.h>
34 #include <asm/kprobes.h>
35
36 #define AARCH64_INSN_SF_BIT BIT(31)
37 #define AARCH64_INSN_N_BIT BIT(22)
38
39 static int aarch64_insn_encoding_class[] = {
40 AARCH64_INSN_CLS_UNKNOWN,
41 AARCH64_INSN_CLS_UNKNOWN,
42 AARCH64_INSN_CLS_UNKNOWN,
43 AARCH64_INSN_CLS_UNKNOWN,
44 AARCH64_INSN_CLS_LDST,
45 AARCH64_INSN_CLS_DP_REG,
46 AARCH64_INSN_CLS_LDST,
47 AARCH64_INSN_CLS_DP_FPSIMD,
48 AARCH64_INSN_CLS_DP_IMM,
49 AARCH64_INSN_CLS_DP_IMM,
50 AARCH64_INSN_CLS_BR_SYS,
51 AARCH64_INSN_CLS_BR_SYS,
52 AARCH64_INSN_CLS_LDST,
53 AARCH64_INSN_CLS_DP_REG,
54 AARCH64_INSN_CLS_LDST,
55 AARCH64_INSN_CLS_DP_FPSIMD,
56 };
57
aarch64_get_insn_class(u32 insn)58 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
59 {
60 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
61 }
62
63 /* NOP is an alias of HINT */
aarch64_insn_is_nop(u32 insn)64 bool __kprobes aarch64_insn_is_nop(u32 insn)
65 {
66 if (!aarch64_insn_is_hint(insn))
67 return false;
68
69 switch (insn & 0xFE0) {
70 case AARCH64_INSN_HINT_YIELD:
71 case AARCH64_INSN_HINT_WFE:
72 case AARCH64_INSN_HINT_WFI:
73 case AARCH64_INSN_HINT_SEV:
74 case AARCH64_INSN_HINT_SEVL:
75 return false;
76 default:
77 return true;
78 }
79 }
80
aarch64_insn_is_branch_imm(u32 insn)81 bool aarch64_insn_is_branch_imm(u32 insn)
82 {
83 return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
84 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
85 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
86 aarch64_insn_is_bcond(insn));
87 }
88
89 static DEFINE_RAW_SPINLOCK(patch_lock);
90
patch_map(void * addr,int fixmap)91 static void __kprobes *patch_map(void *addr, int fixmap)
92 {
93 unsigned long uintaddr = (uintptr_t) addr;
94 bool module = !core_kernel_text(uintaddr);
95 struct page *page;
96
97 if (module && IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
98 page = vmalloc_to_page(addr);
99 else if (!module)
100 page = phys_to_page(__pa_symbol(addr));
101 else
102 return addr;
103
104 BUG_ON(!page);
105 return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
106 (uintaddr & ~PAGE_MASK));
107 }
108
patch_unmap(int fixmap)109 static void __kprobes patch_unmap(int fixmap)
110 {
111 clear_fixmap(fixmap);
112 }
113 /*
114 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
115 * little-endian.
116 */
aarch64_insn_read(void * addr,u32 * insnp)117 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
118 {
119 int ret;
120 __le32 val;
121
122 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
123 if (!ret)
124 *insnp = le32_to_cpu(val);
125
126 return ret;
127 }
128
__aarch64_insn_write(void * addr,__le32 insn)129 static int __kprobes __aarch64_insn_write(void *addr, __le32 insn)
130 {
131 void *waddr = addr;
132 unsigned long flags = 0;
133 int ret;
134
135 raw_spin_lock_irqsave(&patch_lock, flags);
136 waddr = patch_map(addr, FIX_TEXT_POKE0);
137
138 ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
139
140 patch_unmap(FIX_TEXT_POKE0);
141 raw_spin_unlock_irqrestore(&patch_lock, flags);
142
143 return ret;
144 }
145
aarch64_insn_write(void * addr,u32 insn)146 int __kprobes aarch64_insn_write(void *addr, u32 insn)
147 {
148 return __aarch64_insn_write(addr, cpu_to_le32(insn));
149 }
150
__aarch64_insn_hotpatch_safe(u32 insn)151 static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
152 {
153 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
154 return false;
155
156 return aarch64_insn_is_b(insn) ||
157 aarch64_insn_is_bl(insn) ||
158 aarch64_insn_is_svc(insn) ||
159 aarch64_insn_is_hvc(insn) ||
160 aarch64_insn_is_smc(insn) ||
161 aarch64_insn_is_brk(insn) ||
162 aarch64_insn_is_nop(insn);
163 }
164
aarch64_insn_uses_literal(u32 insn)165 bool __kprobes aarch64_insn_uses_literal(u32 insn)
166 {
167 /* ldr/ldrsw (literal), prfm */
168
169 return aarch64_insn_is_ldr_lit(insn) ||
170 aarch64_insn_is_ldrsw_lit(insn) ||
171 aarch64_insn_is_adr_adrp(insn) ||
172 aarch64_insn_is_prfm_lit(insn);
173 }
174
aarch64_insn_is_branch(u32 insn)175 bool __kprobes aarch64_insn_is_branch(u32 insn)
176 {
177 /* b, bl, cb*, tb*, b.cond, br, blr */
178
179 return aarch64_insn_is_b(insn) ||
180 aarch64_insn_is_bl(insn) ||
181 aarch64_insn_is_cbz(insn) ||
182 aarch64_insn_is_cbnz(insn) ||
183 aarch64_insn_is_tbz(insn) ||
184 aarch64_insn_is_tbnz(insn) ||
185 aarch64_insn_is_ret(insn) ||
186 aarch64_insn_is_br(insn) ||
187 aarch64_insn_is_blr(insn) ||
188 aarch64_insn_is_bcond(insn);
189 }
190
191 /*
192 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
193 * Section B2.6.5 "Concurrent modification and execution of instructions":
194 * Concurrent modification and execution of instructions can lead to the
195 * resulting instruction performing any behavior that can be achieved by
196 * executing any sequence of instructions that can be executed from the
197 * same Exception level, except where the instruction before modification
198 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
199 * or SMC instruction.
200 */
aarch64_insn_hotpatch_safe(u32 old_insn,u32 new_insn)201 bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
202 {
203 return __aarch64_insn_hotpatch_safe(old_insn) &&
204 __aarch64_insn_hotpatch_safe(new_insn);
205 }
206
aarch64_insn_patch_text_nosync(void * addr,u32 insn)207 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
208 {
209 u32 *tp = addr;
210 int ret;
211
212 /* A64 instructions must be word aligned */
213 if ((uintptr_t)tp & 0x3)
214 return -EINVAL;
215
216 ret = aarch64_insn_write(tp, insn);
217 if (ret == 0)
218 flush_icache_range((uintptr_t)tp,
219 (uintptr_t)tp + AARCH64_INSN_SIZE);
220
221 return ret;
222 }
223
224 struct aarch64_insn_patch {
225 void **text_addrs;
226 u32 *new_insns;
227 int insn_cnt;
228 atomic_t cpu_count;
229 };
230
aarch64_insn_patch_text_cb(void * arg)231 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
232 {
233 int i, ret = 0;
234 struct aarch64_insn_patch *pp = arg;
235
236 /* The first CPU becomes master */
237 if (atomic_inc_return(&pp->cpu_count) == 1) {
238 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
239 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
240 pp->new_insns[i]);
241 /*
242 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
243 * which ends with "dsb; isb" pair guaranteeing global
244 * visibility.
245 */
246 /* Notify other processors with an additional increment. */
247 atomic_inc(&pp->cpu_count);
248 } else {
249 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
250 cpu_relax();
251 isb();
252 }
253
254 return ret;
255 }
256
257 static
aarch64_insn_patch_text_sync(void * addrs[],u32 insns[],int cnt)258 int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
259 {
260 struct aarch64_insn_patch patch = {
261 .text_addrs = addrs,
262 .new_insns = insns,
263 .insn_cnt = cnt,
264 .cpu_count = ATOMIC_INIT(0),
265 };
266
267 if (cnt <= 0)
268 return -EINVAL;
269
270 return stop_machine_cpuslocked(aarch64_insn_patch_text_cb, &patch,
271 cpu_online_mask);
272 }
273
aarch64_insn_patch_text(void * addrs[],u32 insns[],int cnt)274 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
275 {
276 int ret;
277 u32 insn;
278
279 /* Unsafe to patch multiple instructions without synchronizaiton */
280 if (cnt == 1) {
281 ret = aarch64_insn_read(addrs[0], &insn);
282 if (ret)
283 return ret;
284
285 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
286 /*
287 * ARMv8 architecture doesn't guarantee all CPUs see
288 * the new instruction after returning from function
289 * aarch64_insn_patch_text_nosync(). So send IPIs to
290 * all other CPUs to achieve instruction
291 * synchronization.
292 */
293 ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
294 kick_all_cpus_sync();
295 return ret;
296 }
297 }
298
299 return aarch64_insn_patch_text_sync(addrs, insns, cnt);
300 }
301
aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,u32 * maskp,int * shiftp)302 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
303 u32 *maskp, int *shiftp)
304 {
305 u32 mask;
306 int shift;
307
308 switch (type) {
309 case AARCH64_INSN_IMM_26:
310 mask = BIT(26) - 1;
311 shift = 0;
312 break;
313 case AARCH64_INSN_IMM_19:
314 mask = BIT(19) - 1;
315 shift = 5;
316 break;
317 case AARCH64_INSN_IMM_16:
318 mask = BIT(16) - 1;
319 shift = 5;
320 break;
321 case AARCH64_INSN_IMM_14:
322 mask = BIT(14) - 1;
323 shift = 5;
324 break;
325 case AARCH64_INSN_IMM_12:
326 mask = BIT(12) - 1;
327 shift = 10;
328 break;
329 case AARCH64_INSN_IMM_9:
330 mask = BIT(9) - 1;
331 shift = 12;
332 break;
333 case AARCH64_INSN_IMM_7:
334 mask = BIT(7) - 1;
335 shift = 15;
336 break;
337 case AARCH64_INSN_IMM_6:
338 case AARCH64_INSN_IMM_S:
339 mask = BIT(6) - 1;
340 shift = 10;
341 break;
342 case AARCH64_INSN_IMM_R:
343 mask = BIT(6) - 1;
344 shift = 16;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 *maskp = mask;
351 *shiftp = shift;
352
353 return 0;
354 }
355
356 #define ADR_IMM_HILOSPLIT 2
357 #define ADR_IMM_SIZE SZ_2M
358 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
359 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
360 #define ADR_IMM_LOSHIFT 29
361 #define ADR_IMM_HISHIFT 5
362
aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type,u32 insn)363 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
364 {
365 u32 immlo, immhi, mask;
366 int shift;
367
368 switch (type) {
369 case AARCH64_INSN_IMM_ADR:
370 shift = 0;
371 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
372 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
373 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
374 mask = ADR_IMM_SIZE - 1;
375 break;
376 default:
377 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
378 pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
379 type);
380 return 0;
381 }
382 }
383
384 return (insn >> shift) & mask;
385 }
386
aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,u32 insn,u64 imm)387 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
388 u32 insn, u64 imm)
389 {
390 u32 immlo, immhi, mask;
391 int shift;
392
393 if (insn == AARCH64_BREAK_FAULT)
394 return AARCH64_BREAK_FAULT;
395
396 switch (type) {
397 case AARCH64_INSN_IMM_ADR:
398 shift = 0;
399 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
400 imm >>= ADR_IMM_HILOSPLIT;
401 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
402 imm = immlo | immhi;
403 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
404 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
405 break;
406 default:
407 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
408 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
409 type);
410 return AARCH64_BREAK_FAULT;
411 }
412 }
413
414 /* Update the immediate field. */
415 insn &= ~(mask << shift);
416 insn |= (imm & mask) << shift;
417
418 return insn;
419 }
420
aarch64_insn_decode_register(enum aarch64_insn_register_type type,u32 insn)421 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
422 u32 insn)
423 {
424 int shift;
425
426 switch (type) {
427 case AARCH64_INSN_REGTYPE_RT:
428 case AARCH64_INSN_REGTYPE_RD:
429 shift = 0;
430 break;
431 case AARCH64_INSN_REGTYPE_RN:
432 shift = 5;
433 break;
434 case AARCH64_INSN_REGTYPE_RT2:
435 case AARCH64_INSN_REGTYPE_RA:
436 shift = 10;
437 break;
438 case AARCH64_INSN_REGTYPE_RM:
439 shift = 16;
440 break;
441 default:
442 pr_err("%s: unknown register type encoding %d\n", __func__,
443 type);
444 return 0;
445 }
446
447 return (insn >> shift) & GENMASK(4, 0);
448 }
449
aarch64_insn_encode_register(enum aarch64_insn_register_type type,u32 insn,enum aarch64_insn_register reg)450 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
451 u32 insn,
452 enum aarch64_insn_register reg)
453 {
454 int shift;
455
456 if (insn == AARCH64_BREAK_FAULT)
457 return AARCH64_BREAK_FAULT;
458
459 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
460 pr_err("%s: unknown register encoding %d\n", __func__, reg);
461 return AARCH64_BREAK_FAULT;
462 }
463
464 switch (type) {
465 case AARCH64_INSN_REGTYPE_RT:
466 case AARCH64_INSN_REGTYPE_RD:
467 shift = 0;
468 break;
469 case AARCH64_INSN_REGTYPE_RN:
470 shift = 5;
471 break;
472 case AARCH64_INSN_REGTYPE_RT2:
473 case AARCH64_INSN_REGTYPE_RA:
474 shift = 10;
475 break;
476 case AARCH64_INSN_REGTYPE_RM:
477 case AARCH64_INSN_REGTYPE_RS:
478 shift = 16;
479 break;
480 default:
481 pr_err("%s: unknown register type encoding %d\n", __func__,
482 type);
483 return AARCH64_BREAK_FAULT;
484 }
485
486 insn &= ~(GENMASK(4, 0) << shift);
487 insn |= reg << shift;
488
489 return insn;
490 }
491
aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,u32 insn)492 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
493 u32 insn)
494 {
495 u32 size;
496
497 switch (type) {
498 case AARCH64_INSN_SIZE_8:
499 size = 0;
500 break;
501 case AARCH64_INSN_SIZE_16:
502 size = 1;
503 break;
504 case AARCH64_INSN_SIZE_32:
505 size = 2;
506 break;
507 case AARCH64_INSN_SIZE_64:
508 size = 3;
509 break;
510 default:
511 pr_err("%s: unknown size encoding %d\n", __func__, type);
512 return AARCH64_BREAK_FAULT;
513 }
514
515 insn &= ~GENMASK(31, 30);
516 insn |= size << 30;
517
518 return insn;
519 }
520
branch_imm_common(unsigned long pc,unsigned long addr,long range)521 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
522 long range)
523 {
524 long offset;
525
526 if ((pc & 0x3) || (addr & 0x3)) {
527 pr_err("%s: A64 instructions must be word aligned\n", __func__);
528 return range;
529 }
530
531 offset = ((long)addr - (long)pc);
532
533 if (offset < -range || offset >= range) {
534 pr_err("%s: offset out of range\n", __func__);
535 return range;
536 }
537
538 return offset;
539 }
540
aarch64_insn_gen_branch_imm(unsigned long pc,unsigned long addr,enum aarch64_insn_branch_type type)541 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
542 enum aarch64_insn_branch_type type)
543 {
544 u32 insn;
545 long offset;
546
547 /*
548 * B/BL support [-128M, 128M) offset
549 * ARM64 virtual address arrangement guarantees all kernel and module
550 * texts are within +/-128M.
551 */
552 offset = branch_imm_common(pc, addr, SZ_128M);
553 if (offset >= SZ_128M)
554 return AARCH64_BREAK_FAULT;
555
556 switch (type) {
557 case AARCH64_INSN_BRANCH_LINK:
558 insn = aarch64_insn_get_bl_value();
559 break;
560 case AARCH64_INSN_BRANCH_NOLINK:
561 insn = aarch64_insn_get_b_value();
562 break;
563 default:
564 pr_err("%s: unknown branch encoding %d\n", __func__, type);
565 return AARCH64_BREAK_FAULT;
566 }
567
568 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
569 offset >> 2);
570 }
571
aarch64_insn_gen_comp_branch_imm(unsigned long pc,unsigned long addr,enum aarch64_insn_register reg,enum aarch64_insn_variant variant,enum aarch64_insn_branch_type type)572 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
573 enum aarch64_insn_register reg,
574 enum aarch64_insn_variant variant,
575 enum aarch64_insn_branch_type type)
576 {
577 u32 insn;
578 long offset;
579
580 offset = branch_imm_common(pc, addr, SZ_1M);
581 if (offset >= SZ_1M)
582 return AARCH64_BREAK_FAULT;
583
584 switch (type) {
585 case AARCH64_INSN_BRANCH_COMP_ZERO:
586 insn = aarch64_insn_get_cbz_value();
587 break;
588 case AARCH64_INSN_BRANCH_COMP_NONZERO:
589 insn = aarch64_insn_get_cbnz_value();
590 break;
591 default:
592 pr_err("%s: unknown branch encoding %d\n", __func__, type);
593 return AARCH64_BREAK_FAULT;
594 }
595
596 switch (variant) {
597 case AARCH64_INSN_VARIANT_32BIT:
598 break;
599 case AARCH64_INSN_VARIANT_64BIT:
600 insn |= AARCH64_INSN_SF_BIT;
601 break;
602 default:
603 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
604 return AARCH64_BREAK_FAULT;
605 }
606
607 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
608
609 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
610 offset >> 2);
611 }
612
aarch64_insn_gen_cond_branch_imm(unsigned long pc,unsigned long addr,enum aarch64_insn_condition cond)613 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
614 enum aarch64_insn_condition cond)
615 {
616 u32 insn;
617 long offset;
618
619 offset = branch_imm_common(pc, addr, SZ_1M);
620
621 insn = aarch64_insn_get_bcond_value();
622
623 if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
624 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
625 return AARCH64_BREAK_FAULT;
626 }
627 insn |= cond;
628
629 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
630 offset >> 2);
631 }
632
aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)633 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
634 {
635 return aarch64_insn_get_hint_value() | op;
636 }
637
aarch64_insn_gen_nop(void)638 u32 __kprobes aarch64_insn_gen_nop(void)
639 {
640 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
641 }
642
aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,enum aarch64_insn_branch_type type)643 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
644 enum aarch64_insn_branch_type type)
645 {
646 u32 insn;
647
648 switch (type) {
649 case AARCH64_INSN_BRANCH_NOLINK:
650 insn = aarch64_insn_get_br_value();
651 break;
652 case AARCH64_INSN_BRANCH_LINK:
653 insn = aarch64_insn_get_blr_value();
654 break;
655 case AARCH64_INSN_BRANCH_RETURN:
656 insn = aarch64_insn_get_ret_value();
657 break;
658 default:
659 pr_err("%s: unknown branch encoding %d\n", __func__, type);
660 return AARCH64_BREAK_FAULT;
661 }
662
663 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
664 }
665
aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,enum aarch64_insn_register base,enum aarch64_insn_register offset,enum aarch64_insn_size_type size,enum aarch64_insn_ldst_type type)666 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
667 enum aarch64_insn_register base,
668 enum aarch64_insn_register offset,
669 enum aarch64_insn_size_type size,
670 enum aarch64_insn_ldst_type type)
671 {
672 u32 insn;
673
674 switch (type) {
675 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
676 insn = aarch64_insn_get_ldr_reg_value();
677 break;
678 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
679 insn = aarch64_insn_get_str_reg_value();
680 break;
681 default:
682 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
683 return AARCH64_BREAK_FAULT;
684 }
685
686 insn = aarch64_insn_encode_ldst_size(size, insn);
687
688 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
689
690 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
691 base);
692
693 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
694 offset);
695 }
696
aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,enum aarch64_insn_register reg2,enum aarch64_insn_register base,int offset,enum aarch64_insn_variant variant,enum aarch64_insn_ldst_type type)697 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
698 enum aarch64_insn_register reg2,
699 enum aarch64_insn_register base,
700 int offset,
701 enum aarch64_insn_variant variant,
702 enum aarch64_insn_ldst_type type)
703 {
704 u32 insn;
705 int shift;
706
707 switch (type) {
708 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
709 insn = aarch64_insn_get_ldp_pre_value();
710 break;
711 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
712 insn = aarch64_insn_get_stp_pre_value();
713 break;
714 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
715 insn = aarch64_insn_get_ldp_post_value();
716 break;
717 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
718 insn = aarch64_insn_get_stp_post_value();
719 break;
720 default:
721 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
722 return AARCH64_BREAK_FAULT;
723 }
724
725 switch (variant) {
726 case AARCH64_INSN_VARIANT_32BIT:
727 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
728 pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
729 __func__, offset);
730 return AARCH64_BREAK_FAULT;
731 }
732 shift = 2;
733 break;
734 case AARCH64_INSN_VARIANT_64BIT:
735 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
736 pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
737 __func__, offset);
738 return AARCH64_BREAK_FAULT;
739 }
740 shift = 3;
741 insn |= AARCH64_INSN_SF_BIT;
742 break;
743 default:
744 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
745 return AARCH64_BREAK_FAULT;
746 }
747
748 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
749 reg1);
750
751 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
752 reg2);
753
754 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
755 base);
756
757 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
758 offset >> shift);
759 }
760
aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,enum aarch64_insn_register base,enum aarch64_insn_register state,enum aarch64_insn_size_type size,enum aarch64_insn_ldst_type type)761 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
762 enum aarch64_insn_register base,
763 enum aarch64_insn_register state,
764 enum aarch64_insn_size_type size,
765 enum aarch64_insn_ldst_type type)
766 {
767 u32 insn;
768
769 switch (type) {
770 case AARCH64_INSN_LDST_LOAD_EX:
771 insn = aarch64_insn_get_load_ex_value();
772 break;
773 case AARCH64_INSN_LDST_STORE_EX:
774 insn = aarch64_insn_get_store_ex_value();
775 break;
776 default:
777 pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
778 return AARCH64_BREAK_FAULT;
779 }
780
781 insn = aarch64_insn_encode_ldst_size(size, insn);
782
783 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
784 reg);
785
786 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
787 base);
788
789 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
790 AARCH64_INSN_REG_ZR);
791
792 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
793 state);
794 }
795
aarch64_insn_gen_ldadd(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size)796 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
797 enum aarch64_insn_register address,
798 enum aarch64_insn_register value,
799 enum aarch64_insn_size_type size)
800 {
801 u32 insn = aarch64_insn_get_ldadd_value();
802
803 switch (size) {
804 case AARCH64_INSN_SIZE_32:
805 case AARCH64_INSN_SIZE_64:
806 break;
807 default:
808 pr_err("%s: unimplemented size encoding %d\n", __func__, size);
809 return AARCH64_BREAK_FAULT;
810 }
811
812 insn = aarch64_insn_encode_ldst_size(size, insn);
813
814 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
815 result);
816
817 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
818 address);
819
820 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
821 value);
822 }
823
aarch64_insn_gen_stadd(enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size)824 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
825 enum aarch64_insn_register value,
826 enum aarch64_insn_size_type size)
827 {
828 /*
829 * STADD is simply encoded as an alias for LDADD with XZR as
830 * the destination register.
831 */
832 return aarch64_insn_gen_ldadd(AARCH64_INSN_REG_ZR, address,
833 value, size);
834 }
835
aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,enum aarch64_insn_prfm_target target,enum aarch64_insn_prfm_policy policy,u32 insn)836 static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
837 enum aarch64_insn_prfm_target target,
838 enum aarch64_insn_prfm_policy policy,
839 u32 insn)
840 {
841 u32 imm_type = 0, imm_target = 0, imm_policy = 0;
842
843 switch (type) {
844 case AARCH64_INSN_PRFM_TYPE_PLD:
845 break;
846 case AARCH64_INSN_PRFM_TYPE_PLI:
847 imm_type = BIT(0);
848 break;
849 case AARCH64_INSN_PRFM_TYPE_PST:
850 imm_type = BIT(1);
851 break;
852 default:
853 pr_err("%s: unknown prfm type encoding %d\n", __func__, type);
854 return AARCH64_BREAK_FAULT;
855 }
856
857 switch (target) {
858 case AARCH64_INSN_PRFM_TARGET_L1:
859 break;
860 case AARCH64_INSN_PRFM_TARGET_L2:
861 imm_target = BIT(0);
862 break;
863 case AARCH64_INSN_PRFM_TARGET_L3:
864 imm_target = BIT(1);
865 break;
866 default:
867 pr_err("%s: unknown prfm target encoding %d\n", __func__, target);
868 return AARCH64_BREAK_FAULT;
869 }
870
871 switch (policy) {
872 case AARCH64_INSN_PRFM_POLICY_KEEP:
873 break;
874 case AARCH64_INSN_PRFM_POLICY_STRM:
875 imm_policy = BIT(0);
876 break;
877 default:
878 pr_err("%s: unknown prfm policy encoding %d\n", __func__, policy);
879 return AARCH64_BREAK_FAULT;
880 }
881
882 /* In this case, imm5 is encoded into Rt field. */
883 insn &= ~GENMASK(4, 0);
884 insn |= imm_policy | (imm_target << 1) | (imm_type << 3);
885
886 return insn;
887 }
888
aarch64_insn_gen_prefetch(enum aarch64_insn_register base,enum aarch64_insn_prfm_type type,enum aarch64_insn_prfm_target target,enum aarch64_insn_prfm_policy policy)889 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
890 enum aarch64_insn_prfm_type type,
891 enum aarch64_insn_prfm_target target,
892 enum aarch64_insn_prfm_policy policy)
893 {
894 u32 insn = aarch64_insn_get_prfm_value();
895
896 insn = aarch64_insn_encode_ldst_size(AARCH64_INSN_SIZE_64, insn);
897
898 insn = aarch64_insn_encode_prfm_imm(type, target, policy, insn);
899
900 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
901 base);
902
903 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, 0);
904 }
905
aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,enum aarch64_insn_register src,int imm,enum aarch64_insn_variant variant,enum aarch64_insn_adsb_type type)906 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
907 enum aarch64_insn_register src,
908 int imm, enum aarch64_insn_variant variant,
909 enum aarch64_insn_adsb_type type)
910 {
911 u32 insn;
912
913 switch (type) {
914 case AARCH64_INSN_ADSB_ADD:
915 insn = aarch64_insn_get_add_imm_value();
916 break;
917 case AARCH64_INSN_ADSB_SUB:
918 insn = aarch64_insn_get_sub_imm_value();
919 break;
920 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
921 insn = aarch64_insn_get_adds_imm_value();
922 break;
923 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
924 insn = aarch64_insn_get_subs_imm_value();
925 break;
926 default:
927 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
928 return AARCH64_BREAK_FAULT;
929 }
930
931 switch (variant) {
932 case AARCH64_INSN_VARIANT_32BIT:
933 break;
934 case AARCH64_INSN_VARIANT_64BIT:
935 insn |= AARCH64_INSN_SF_BIT;
936 break;
937 default:
938 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
939 return AARCH64_BREAK_FAULT;
940 }
941
942 if (imm & ~(SZ_4K - 1)) {
943 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
944 return AARCH64_BREAK_FAULT;
945 }
946
947 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
948
949 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
950
951 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
952 }
953
aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,enum aarch64_insn_register src,int immr,int imms,enum aarch64_insn_variant variant,enum aarch64_insn_bitfield_type type)954 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
955 enum aarch64_insn_register src,
956 int immr, int imms,
957 enum aarch64_insn_variant variant,
958 enum aarch64_insn_bitfield_type type)
959 {
960 u32 insn;
961 u32 mask;
962
963 switch (type) {
964 case AARCH64_INSN_BITFIELD_MOVE:
965 insn = aarch64_insn_get_bfm_value();
966 break;
967 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
968 insn = aarch64_insn_get_ubfm_value();
969 break;
970 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
971 insn = aarch64_insn_get_sbfm_value();
972 break;
973 default:
974 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
975 return AARCH64_BREAK_FAULT;
976 }
977
978 switch (variant) {
979 case AARCH64_INSN_VARIANT_32BIT:
980 mask = GENMASK(4, 0);
981 break;
982 case AARCH64_INSN_VARIANT_64BIT:
983 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
984 mask = GENMASK(5, 0);
985 break;
986 default:
987 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
988 return AARCH64_BREAK_FAULT;
989 }
990
991 if (immr & ~mask) {
992 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
993 return AARCH64_BREAK_FAULT;
994 }
995 if (imms & ~mask) {
996 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
997 return AARCH64_BREAK_FAULT;
998 }
999
1000 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1001
1002 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1003
1004 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
1005
1006 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
1007 }
1008
aarch64_insn_gen_movewide(enum aarch64_insn_register dst,int imm,int shift,enum aarch64_insn_variant variant,enum aarch64_insn_movewide_type type)1009 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
1010 int imm, int shift,
1011 enum aarch64_insn_variant variant,
1012 enum aarch64_insn_movewide_type type)
1013 {
1014 u32 insn;
1015
1016 switch (type) {
1017 case AARCH64_INSN_MOVEWIDE_ZERO:
1018 insn = aarch64_insn_get_movz_value();
1019 break;
1020 case AARCH64_INSN_MOVEWIDE_KEEP:
1021 insn = aarch64_insn_get_movk_value();
1022 break;
1023 case AARCH64_INSN_MOVEWIDE_INVERSE:
1024 insn = aarch64_insn_get_movn_value();
1025 break;
1026 default:
1027 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
1028 return AARCH64_BREAK_FAULT;
1029 }
1030
1031 if (imm & ~(SZ_64K - 1)) {
1032 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
1033 return AARCH64_BREAK_FAULT;
1034 }
1035
1036 switch (variant) {
1037 case AARCH64_INSN_VARIANT_32BIT:
1038 if (shift != 0 && shift != 16) {
1039 pr_err("%s: invalid shift encoding %d\n", __func__,
1040 shift);
1041 return AARCH64_BREAK_FAULT;
1042 }
1043 break;
1044 case AARCH64_INSN_VARIANT_64BIT:
1045 insn |= AARCH64_INSN_SF_BIT;
1046 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
1047 pr_err("%s: invalid shift encoding %d\n", __func__,
1048 shift);
1049 return AARCH64_BREAK_FAULT;
1050 }
1051 break;
1052 default:
1053 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1054 return AARCH64_BREAK_FAULT;
1055 }
1056
1057 insn |= (shift >> 4) << 21;
1058
1059 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1060
1061 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
1062 }
1063
aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg,int shift,enum aarch64_insn_variant variant,enum aarch64_insn_adsb_type type)1064 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
1065 enum aarch64_insn_register src,
1066 enum aarch64_insn_register reg,
1067 int shift,
1068 enum aarch64_insn_variant variant,
1069 enum aarch64_insn_adsb_type type)
1070 {
1071 u32 insn;
1072
1073 switch (type) {
1074 case AARCH64_INSN_ADSB_ADD:
1075 insn = aarch64_insn_get_add_value();
1076 break;
1077 case AARCH64_INSN_ADSB_SUB:
1078 insn = aarch64_insn_get_sub_value();
1079 break;
1080 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
1081 insn = aarch64_insn_get_adds_value();
1082 break;
1083 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
1084 insn = aarch64_insn_get_subs_value();
1085 break;
1086 default:
1087 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
1088 return AARCH64_BREAK_FAULT;
1089 }
1090
1091 switch (variant) {
1092 case AARCH64_INSN_VARIANT_32BIT:
1093 if (shift & ~(SZ_32 - 1)) {
1094 pr_err("%s: invalid shift encoding %d\n", __func__,
1095 shift);
1096 return AARCH64_BREAK_FAULT;
1097 }
1098 break;
1099 case AARCH64_INSN_VARIANT_64BIT:
1100 insn |= AARCH64_INSN_SF_BIT;
1101 if (shift & ~(SZ_64 - 1)) {
1102 pr_err("%s: invalid shift encoding %d\n", __func__,
1103 shift);
1104 return AARCH64_BREAK_FAULT;
1105 }
1106 break;
1107 default:
1108 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1109 return AARCH64_BREAK_FAULT;
1110 }
1111
1112
1113 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1114
1115 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1116
1117 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1118
1119 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1120 }
1121
aarch64_insn_gen_data1(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_variant variant,enum aarch64_insn_data1_type type)1122 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
1123 enum aarch64_insn_register src,
1124 enum aarch64_insn_variant variant,
1125 enum aarch64_insn_data1_type type)
1126 {
1127 u32 insn;
1128
1129 switch (type) {
1130 case AARCH64_INSN_DATA1_REVERSE_16:
1131 insn = aarch64_insn_get_rev16_value();
1132 break;
1133 case AARCH64_INSN_DATA1_REVERSE_32:
1134 insn = aarch64_insn_get_rev32_value();
1135 break;
1136 case AARCH64_INSN_DATA1_REVERSE_64:
1137 if (variant != AARCH64_INSN_VARIANT_64BIT) {
1138 pr_err("%s: invalid variant for reverse64 %d\n",
1139 __func__, variant);
1140 return AARCH64_BREAK_FAULT;
1141 }
1142 insn = aarch64_insn_get_rev64_value();
1143 break;
1144 default:
1145 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
1146 return AARCH64_BREAK_FAULT;
1147 }
1148
1149 switch (variant) {
1150 case AARCH64_INSN_VARIANT_32BIT:
1151 break;
1152 case AARCH64_INSN_VARIANT_64BIT:
1153 insn |= AARCH64_INSN_SF_BIT;
1154 break;
1155 default:
1156 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1157 return AARCH64_BREAK_FAULT;
1158 }
1159
1160 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1161
1162 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1163 }
1164
aarch64_insn_gen_data2(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg,enum aarch64_insn_variant variant,enum aarch64_insn_data2_type type)1165 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
1166 enum aarch64_insn_register src,
1167 enum aarch64_insn_register reg,
1168 enum aarch64_insn_variant variant,
1169 enum aarch64_insn_data2_type type)
1170 {
1171 u32 insn;
1172
1173 switch (type) {
1174 case AARCH64_INSN_DATA2_UDIV:
1175 insn = aarch64_insn_get_udiv_value();
1176 break;
1177 case AARCH64_INSN_DATA2_SDIV:
1178 insn = aarch64_insn_get_sdiv_value();
1179 break;
1180 case AARCH64_INSN_DATA2_LSLV:
1181 insn = aarch64_insn_get_lslv_value();
1182 break;
1183 case AARCH64_INSN_DATA2_LSRV:
1184 insn = aarch64_insn_get_lsrv_value();
1185 break;
1186 case AARCH64_INSN_DATA2_ASRV:
1187 insn = aarch64_insn_get_asrv_value();
1188 break;
1189 case AARCH64_INSN_DATA2_RORV:
1190 insn = aarch64_insn_get_rorv_value();
1191 break;
1192 default:
1193 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1194 return AARCH64_BREAK_FAULT;
1195 }
1196
1197 switch (variant) {
1198 case AARCH64_INSN_VARIANT_32BIT:
1199 break;
1200 case AARCH64_INSN_VARIANT_64BIT:
1201 insn |= AARCH64_INSN_SF_BIT;
1202 break;
1203 default:
1204 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1205 return AARCH64_BREAK_FAULT;
1206 }
1207
1208 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1209
1210 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1211
1212 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1213 }
1214
aarch64_insn_gen_data3(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg1,enum aarch64_insn_register reg2,enum aarch64_insn_variant variant,enum aarch64_insn_data3_type type)1215 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1216 enum aarch64_insn_register src,
1217 enum aarch64_insn_register reg1,
1218 enum aarch64_insn_register reg2,
1219 enum aarch64_insn_variant variant,
1220 enum aarch64_insn_data3_type type)
1221 {
1222 u32 insn;
1223
1224 switch (type) {
1225 case AARCH64_INSN_DATA3_MADD:
1226 insn = aarch64_insn_get_madd_value();
1227 break;
1228 case AARCH64_INSN_DATA3_MSUB:
1229 insn = aarch64_insn_get_msub_value();
1230 break;
1231 default:
1232 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1233 return AARCH64_BREAK_FAULT;
1234 }
1235
1236 switch (variant) {
1237 case AARCH64_INSN_VARIANT_32BIT:
1238 break;
1239 case AARCH64_INSN_VARIANT_64BIT:
1240 insn |= AARCH64_INSN_SF_BIT;
1241 break;
1242 default:
1243 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1244 return AARCH64_BREAK_FAULT;
1245 }
1246
1247 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1248
1249 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1250
1251 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1252 reg1);
1253
1254 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1255 reg2);
1256 }
1257
aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg,int shift,enum aarch64_insn_variant variant,enum aarch64_insn_logic_type type)1258 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1259 enum aarch64_insn_register src,
1260 enum aarch64_insn_register reg,
1261 int shift,
1262 enum aarch64_insn_variant variant,
1263 enum aarch64_insn_logic_type type)
1264 {
1265 u32 insn;
1266
1267 switch (type) {
1268 case AARCH64_INSN_LOGIC_AND:
1269 insn = aarch64_insn_get_and_value();
1270 break;
1271 case AARCH64_INSN_LOGIC_BIC:
1272 insn = aarch64_insn_get_bic_value();
1273 break;
1274 case AARCH64_INSN_LOGIC_ORR:
1275 insn = aarch64_insn_get_orr_value();
1276 break;
1277 case AARCH64_INSN_LOGIC_ORN:
1278 insn = aarch64_insn_get_orn_value();
1279 break;
1280 case AARCH64_INSN_LOGIC_EOR:
1281 insn = aarch64_insn_get_eor_value();
1282 break;
1283 case AARCH64_INSN_LOGIC_EON:
1284 insn = aarch64_insn_get_eon_value();
1285 break;
1286 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1287 insn = aarch64_insn_get_ands_value();
1288 break;
1289 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1290 insn = aarch64_insn_get_bics_value();
1291 break;
1292 default:
1293 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1294 return AARCH64_BREAK_FAULT;
1295 }
1296
1297 switch (variant) {
1298 case AARCH64_INSN_VARIANT_32BIT:
1299 if (shift & ~(SZ_32 - 1)) {
1300 pr_err("%s: invalid shift encoding %d\n", __func__,
1301 shift);
1302 return AARCH64_BREAK_FAULT;
1303 }
1304 break;
1305 case AARCH64_INSN_VARIANT_64BIT:
1306 insn |= AARCH64_INSN_SF_BIT;
1307 if (shift & ~(SZ_64 - 1)) {
1308 pr_err("%s: invalid shift encoding %d\n", __func__,
1309 shift);
1310 return AARCH64_BREAK_FAULT;
1311 }
1312 break;
1313 default:
1314 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1315 return AARCH64_BREAK_FAULT;
1316 }
1317
1318
1319 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1320
1321 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1322
1323 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1324
1325 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1326 }
1327
1328 /*
1329 * Decode the imm field of a branch, and return the byte offset as a
1330 * signed value (so it can be used when computing a new branch
1331 * target).
1332 */
aarch64_get_branch_offset(u32 insn)1333 s32 aarch64_get_branch_offset(u32 insn)
1334 {
1335 s32 imm;
1336
1337 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1338 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1339 return (imm << 6) >> 4;
1340 }
1341
1342 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1343 aarch64_insn_is_bcond(insn)) {
1344 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1345 return (imm << 13) >> 11;
1346 }
1347
1348 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1349 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1350 return (imm << 18) >> 16;
1351 }
1352
1353 /* Unhandled instruction */
1354 BUG();
1355 }
1356
1357 /*
1358 * Encode the displacement of a branch in the imm field and return the
1359 * updated instruction.
1360 */
aarch64_set_branch_offset(u32 insn,s32 offset)1361 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1362 {
1363 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1364 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1365 offset >> 2);
1366
1367 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1368 aarch64_insn_is_bcond(insn))
1369 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1370 offset >> 2);
1371
1372 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1373 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1374 offset >> 2);
1375
1376 /* Unhandled instruction */
1377 BUG();
1378 }
1379
aarch64_insn_adrp_get_offset(u32 insn)1380 s32 aarch64_insn_adrp_get_offset(u32 insn)
1381 {
1382 BUG_ON(!aarch64_insn_is_adrp(insn));
1383 return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1384 }
1385
aarch64_insn_adrp_set_offset(u32 insn,s32 offset)1386 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1387 {
1388 BUG_ON(!aarch64_insn_is_adrp(insn));
1389 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1390 offset >> 12);
1391 }
1392
1393 /*
1394 * Extract the Op/CR data from a msr/mrs instruction.
1395 */
aarch64_insn_extract_system_reg(u32 insn)1396 u32 aarch64_insn_extract_system_reg(u32 insn)
1397 {
1398 return (insn & 0x1FFFE0) >> 5;
1399 }
1400
aarch32_insn_is_wide(u32 insn)1401 bool aarch32_insn_is_wide(u32 insn)
1402 {
1403 return insn >= 0xe800;
1404 }
1405
1406 /*
1407 * Macros/defines for extracting register numbers from instruction.
1408 */
aarch32_insn_extract_reg_num(u32 insn,int offset)1409 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1410 {
1411 return (insn & (0xf << offset)) >> offset;
1412 }
1413
1414 #define OPC2_MASK 0x7
1415 #define OPC2_OFFSET 5
aarch32_insn_mcr_extract_opc2(u32 insn)1416 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1417 {
1418 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1419 }
1420
1421 #define CRM_MASK 0xf
aarch32_insn_mcr_extract_crm(u32 insn)1422 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1423 {
1424 return insn & CRM_MASK;
1425 }
1426
__check_eq(unsigned long pstate)1427 static bool __kprobes __check_eq(unsigned long pstate)
1428 {
1429 return (pstate & PSR_Z_BIT) != 0;
1430 }
1431
__check_ne(unsigned long pstate)1432 static bool __kprobes __check_ne(unsigned long pstate)
1433 {
1434 return (pstate & PSR_Z_BIT) == 0;
1435 }
1436
__check_cs(unsigned long pstate)1437 static bool __kprobes __check_cs(unsigned long pstate)
1438 {
1439 return (pstate & PSR_C_BIT) != 0;
1440 }
1441
__check_cc(unsigned long pstate)1442 static bool __kprobes __check_cc(unsigned long pstate)
1443 {
1444 return (pstate & PSR_C_BIT) == 0;
1445 }
1446
__check_mi(unsigned long pstate)1447 static bool __kprobes __check_mi(unsigned long pstate)
1448 {
1449 return (pstate & PSR_N_BIT) != 0;
1450 }
1451
__check_pl(unsigned long pstate)1452 static bool __kprobes __check_pl(unsigned long pstate)
1453 {
1454 return (pstate & PSR_N_BIT) == 0;
1455 }
1456
__check_vs(unsigned long pstate)1457 static bool __kprobes __check_vs(unsigned long pstate)
1458 {
1459 return (pstate & PSR_V_BIT) != 0;
1460 }
1461
__check_vc(unsigned long pstate)1462 static bool __kprobes __check_vc(unsigned long pstate)
1463 {
1464 return (pstate & PSR_V_BIT) == 0;
1465 }
1466
__check_hi(unsigned long pstate)1467 static bool __kprobes __check_hi(unsigned long pstate)
1468 {
1469 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1470 return (pstate & PSR_C_BIT) != 0;
1471 }
1472
__check_ls(unsigned long pstate)1473 static bool __kprobes __check_ls(unsigned long pstate)
1474 {
1475 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1476 return (pstate & PSR_C_BIT) == 0;
1477 }
1478
__check_ge(unsigned long pstate)1479 static bool __kprobes __check_ge(unsigned long pstate)
1480 {
1481 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1482 return (pstate & PSR_N_BIT) == 0;
1483 }
1484
__check_lt(unsigned long pstate)1485 static bool __kprobes __check_lt(unsigned long pstate)
1486 {
1487 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1488 return (pstate & PSR_N_BIT) != 0;
1489 }
1490
__check_gt(unsigned long pstate)1491 static bool __kprobes __check_gt(unsigned long pstate)
1492 {
1493 /*PSR_N_BIT ^= PSR_V_BIT */
1494 unsigned long temp = pstate ^ (pstate << 3);
1495
1496 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1497 return (temp & PSR_N_BIT) == 0;
1498 }
1499
__check_le(unsigned long pstate)1500 static bool __kprobes __check_le(unsigned long pstate)
1501 {
1502 /*PSR_N_BIT ^= PSR_V_BIT */
1503 unsigned long temp = pstate ^ (pstate << 3);
1504
1505 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1506 return (temp & PSR_N_BIT) != 0;
1507 }
1508
__check_al(unsigned long pstate)1509 static bool __kprobes __check_al(unsigned long pstate)
1510 {
1511 return true;
1512 }
1513
1514 /*
1515 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
1516 * it behaves identically to 0b1110 ("al").
1517 */
1518 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
1519 __check_eq, __check_ne, __check_cs, __check_cc,
1520 __check_mi, __check_pl, __check_vs, __check_vc,
1521 __check_hi, __check_ls, __check_ge, __check_lt,
1522 __check_gt, __check_le, __check_al, __check_al
1523 };
1524