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1 /*
2  *  libahci.c - Common AHCI SATA low-level routines
3  *
4  *  Maintained by:  Tejun Heo <tj@kernel.org>
5  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
6  *		    on emails.
7  *
8  *  Copyright 2004-2005 Red Hat, Inc.
9  *
10  *
11  *  This program is free software; you can redistribute it and/or modify
12  *  it under the terms of the GNU General Public License as published by
13  *  the Free Software Foundation; either version 2, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful,
17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *  GNU General Public License for more details.
20  *
21  *  You should have received a copy of the GNU General Public License
22  *  along with this program; see the file COPYING.  If not, write to
23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24  *
25  *
26  * libata documentation is available via 'make {ps|pdf}docs',
27  * as Documentation/driver-api/libata.rst
28  *
29  * AHCI hardware documentation:
30  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32  *
33  */
34 
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/nospec.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include <linux/pci.h>
48 #include "ahci.h"
49 #include "libata.h"
50 
51 static int ahci_skip_host_reset;
52 int ahci_ignore_sss;
53 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54 
55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57 
58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60 
61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 			unsigned hints);
63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 			      size_t size);
66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
67 					ssize_t size);
68 
69 
70 
71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 			  unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 			  unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 			  unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
94 #ifdef CONFIG_PM
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 #endif
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 				   enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
101 
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 				   struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 				   struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 				      struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 				  struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 				   struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 				    struct device_attribute *attr,
114 				    const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 				      struct device_attribute *attr, char *buf);
117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
118 
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 		   ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126 
127 struct device_attribute *ahci_shost_attrs[] = {
128 	&dev_attr_link_power_management_policy,
129 	&dev_attr_em_message_type,
130 	&dev_attr_em_message,
131 	&dev_attr_ahci_host_caps,
132 	&dev_attr_ahci_host_cap2,
133 	&dev_attr_ahci_host_version,
134 	&dev_attr_ahci_port_cmd,
135 	&dev_attr_em_buffer,
136 	&dev_attr_em_message_supported,
137 	NULL
138 };
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140 
141 struct device_attribute *ahci_sdev_attrs[] = {
142 	&dev_attr_sw_activity,
143 	&dev_attr_unload_heads,
144 	&dev_attr_ncq_prio_enable,
145 	NULL
146 };
147 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148 
149 struct ata_port_operations ahci_ops = {
150 	.inherits		= &sata_pmp_port_ops,
151 
152 	.qc_defer		= ahci_pmp_qc_defer,
153 	.qc_prep		= ahci_qc_prep,
154 	.qc_issue		= ahci_qc_issue,
155 	.qc_fill_rtf		= ahci_qc_fill_rtf,
156 
157 	.freeze			= ahci_freeze,
158 	.thaw			= ahci_thaw,
159 	.softreset		= ahci_softreset,
160 	.hardreset		= ahci_hardreset,
161 	.postreset		= ahci_postreset,
162 	.pmp_softreset		= ahci_softreset,
163 	.error_handler		= ahci_error_handler,
164 	.post_internal_cmd	= ahci_post_internal_cmd,
165 	.dev_config		= ahci_dev_config,
166 
167 	.scr_read		= ahci_scr_read,
168 	.scr_write		= ahci_scr_write,
169 	.pmp_attach		= ahci_pmp_attach,
170 	.pmp_detach		= ahci_pmp_detach,
171 
172 	.set_lpm		= ahci_set_lpm,
173 	.em_show		= ahci_led_show,
174 	.em_store		= ahci_led_store,
175 	.sw_activity_show	= ahci_activity_show,
176 	.sw_activity_store	= ahci_activity_store,
177 	.transmit_led_message	= ahci_transmit_led_message,
178 #ifdef CONFIG_PM
179 	.port_suspend		= ahci_port_suspend,
180 	.port_resume		= ahci_port_resume,
181 #endif
182 	.port_start		= ahci_port_start,
183 	.port_stop		= ahci_port_stop,
184 };
185 EXPORT_SYMBOL_GPL(ahci_ops);
186 
187 struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 	.inherits		= &ahci_ops,
189 	.softreset		= ahci_pmp_retry_softreset,
190 };
191 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192 
193 static bool ahci_em_messages __read_mostly = true;
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 	"AHCI Enclosure Management Message control (0 = off, 1 = on)");
198 
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203 
ahci_enable_ahci(void __iomem * mmio)204 static void ahci_enable_ahci(void __iomem *mmio)
205 {
206 	int i;
207 	u32 tmp;
208 
209 	/* turn on AHCI_EN */
210 	tmp = readl(mmio + HOST_CTL);
211 	if (tmp & HOST_AHCI_EN)
212 		return;
213 
214 	/* Some controllers need AHCI_EN to be written multiple times.
215 	 * Try a few times before giving up.
216 	 */
217 	for (i = 0; i < 5; i++) {
218 		tmp |= HOST_AHCI_EN;
219 		writel(tmp, mmio + HOST_CTL);
220 		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
221 		if (tmp & HOST_AHCI_EN)
222 			return;
223 		msleep(10);
224 	}
225 
226 	WARN_ON(1);
227 }
228 
229 /**
230  *	ahci_rpm_get_port - Make sure the port is powered on
231  *	@ap: Port to power on
232  *
233  *	Whenever there is need to access the AHCI host registers outside of
234  *	normal execution paths, call this function to make sure the host is
235  *	actually powered on.
236  */
ahci_rpm_get_port(struct ata_port * ap)237 static int ahci_rpm_get_port(struct ata_port *ap)
238 {
239 	return pm_runtime_get_sync(ap->dev);
240 }
241 
242 /**
243  *	ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244  *	@ap: Port to power down
245  *
246  *	Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247  *	if it has no more active users.
248  */
ahci_rpm_put_port(struct ata_port * ap)249 static void ahci_rpm_put_port(struct ata_port *ap)
250 {
251 	pm_runtime_put(ap->dev);
252 }
253 
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)254 static ssize_t ahci_show_host_caps(struct device *dev,
255 				   struct device_attribute *attr, char *buf)
256 {
257 	struct Scsi_Host *shost = class_to_shost(dev);
258 	struct ata_port *ap = ata_shost_to_port(shost);
259 	struct ahci_host_priv *hpriv = ap->host->private_data;
260 
261 	return sprintf(buf, "%x\n", hpriv->cap);
262 }
263 
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 				   struct device_attribute *attr, char *buf)
266 {
267 	struct Scsi_Host *shost = class_to_shost(dev);
268 	struct ata_port *ap = ata_shost_to_port(shost);
269 	struct ahci_host_priv *hpriv = ap->host->private_data;
270 
271 	return sprintf(buf, "%x\n", hpriv->cap2);
272 }
273 
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)274 static ssize_t ahci_show_host_version(struct device *dev,
275 				   struct device_attribute *attr, char *buf)
276 {
277 	struct Scsi_Host *shost = class_to_shost(dev);
278 	struct ata_port *ap = ata_shost_to_port(shost);
279 	struct ahci_host_priv *hpriv = ap->host->private_data;
280 
281 	return sprintf(buf, "%x\n", hpriv->version);
282 }
283 
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 				  struct device_attribute *attr, char *buf)
286 {
287 	struct Scsi_Host *shost = class_to_shost(dev);
288 	struct ata_port *ap = ata_shost_to_port(shost);
289 	void __iomem *port_mmio = ahci_port_base(ap);
290 	ssize_t ret;
291 
292 	ahci_rpm_get_port(ap);
293 	ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 	ahci_rpm_put_port(ap);
295 
296 	return ret;
297 }
298 
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 				   struct device_attribute *attr, char *buf)
301 {
302 	struct Scsi_Host *shost = class_to_shost(dev);
303 	struct ata_port *ap = ata_shost_to_port(shost);
304 	struct ahci_host_priv *hpriv = ap->host->private_data;
305 	void __iomem *mmio = hpriv->mmio;
306 	void __iomem *em_mmio = mmio + hpriv->em_loc;
307 	u32 em_ctl, msg;
308 	unsigned long flags;
309 	size_t count;
310 	int i;
311 
312 	ahci_rpm_get_port(ap);
313 	spin_lock_irqsave(ap->lock, flags);
314 
315 	em_ctl = readl(mmio + HOST_EM_CTL);
316 	if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 	    !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 		spin_unlock_irqrestore(ap->lock, flags);
319 		ahci_rpm_put_port(ap);
320 		return -EINVAL;
321 	}
322 
323 	if (!(em_ctl & EM_CTL_MR)) {
324 		spin_unlock_irqrestore(ap->lock, flags);
325 		ahci_rpm_put_port(ap);
326 		return -EAGAIN;
327 	}
328 
329 	if (!(em_ctl & EM_CTL_SMB))
330 		em_mmio += hpriv->em_buf_sz;
331 
332 	count = hpriv->em_buf_sz;
333 
334 	/* the count should not be larger than PAGE_SIZE */
335 	if (count > PAGE_SIZE) {
336 		if (printk_ratelimit())
337 			ata_port_warn(ap,
338 				      "EM read buffer size too large: "
339 				      "buffer size %u, page size %lu\n",
340 				      hpriv->em_buf_sz, PAGE_SIZE);
341 		count = PAGE_SIZE;
342 	}
343 
344 	for (i = 0; i < count; i += 4) {
345 		msg = readl(em_mmio + i);
346 		buf[i] = msg & 0xff;
347 		buf[i + 1] = (msg >> 8) & 0xff;
348 		buf[i + 2] = (msg >> 16) & 0xff;
349 		buf[i + 3] = (msg >> 24) & 0xff;
350 	}
351 
352 	spin_unlock_irqrestore(ap->lock, flags);
353 	ahci_rpm_put_port(ap);
354 
355 	return i;
356 }
357 
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 				    struct device_attribute *attr,
360 				    const char *buf, size_t size)
361 {
362 	struct Scsi_Host *shost = class_to_shost(dev);
363 	struct ata_port *ap = ata_shost_to_port(shost);
364 	struct ahci_host_priv *hpriv = ap->host->private_data;
365 	void __iomem *mmio = hpriv->mmio;
366 	void __iomem *em_mmio = mmio + hpriv->em_loc;
367 	const unsigned char *msg_buf = buf;
368 	u32 em_ctl, msg;
369 	unsigned long flags;
370 	int i;
371 
372 	/* check size validity */
373 	if (!(ap->flags & ATA_FLAG_EM) ||
374 	    !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 	    size % 4 || size > hpriv->em_buf_sz)
376 		return -EINVAL;
377 
378 	ahci_rpm_get_port(ap);
379 	spin_lock_irqsave(ap->lock, flags);
380 
381 	em_ctl = readl(mmio + HOST_EM_CTL);
382 	if (em_ctl & EM_CTL_TM) {
383 		spin_unlock_irqrestore(ap->lock, flags);
384 		ahci_rpm_put_port(ap);
385 		return -EBUSY;
386 	}
387 
388 	for (i = 0; i < size; i += 4) {
389 		msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 		      msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 		writel(msg, em_mmio + i);
392 	}
393 
394 	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
395 
396 	spin_unlock_irqrestore(ap->lock, flags);
397 	ahci_rpm_put_port(ap);
398 
399 	return size;
400 }
401 
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)402 static ssize_t ahci_show_em_supported(struct device *dev,
403 				      struct device_attribute *attr, char *buf)
404 {
405 	struct Scsi_Host *shost = class_to_shost(dev);
406 	struct ata_port *ap = ata_shost_to_port(shost);
407 	struct ahci_host_priv *hpriv = ap->host->private_data;
408 	void __iomem *mmio = hpriv->mmio;
409 	u32 em_ctl;
410 
411 	ahci_rpm_get_port(ap);
412 	em_ctl = readl(mmio + HOST_EM_CTL);
413 	ahci_rpm_put_port(ap);
414 
415 	return sprintf(buf, "%s%s%s%s\n",
416 		       em_ctl & EM_CTL_LED ? "led " : "",
417 		       em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 		       em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 		       em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
420 }
421 
422 /**
423  *	ahci_save_initial_config - Save and fixup initial config values
424  *	@dev: target AHCI device
425  *	@hpriv: host private area to store config values
426  *
427  *	Some registers containing configuration info might be setup by
428  *	BIOS and might be cleared on reset.  This function saves the
429  *	initial values of those registers into @hpriv such that they
430  *	can be restored after controller reset.
431  *
432  *	If inconsistent, config values are fixed up by this function.
433  *
434  *	If it is not set already this function sets hpriv->start_engine to
435  *	ahci_start_engine.
436  *
437  *	LOCKING:
438  *	None.
439  */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
441 {
442 	void __iomem *mmio = hpriv->mmio;
443 	u32 cap, cap2, vers, port_map;
444 	int i;
445 
446 	/* make sure AHCI mode is enabled before accessing CAP */
447 	ahci_enable_ahci(mmio);
448 
449 	/* Values prefixed with saved_ are written back to host after
450 	 * reset.  Values without are used for driver operation.
451 	 */
452 	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
454 
455 	/* CAP2 register is only defined for AHCI 1.2 and later */
456 	vers = readl(mmio + HOST_VERSION);
457 	if ((vers >> 16) > 1 ||
458 	   ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 		hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
460 	else
461 		hpriv->saved_cap2 = cap2 = 0;
462 
463 	/* some chips have errata preventing 64bit use */
464 	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 		dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
466 		cap &= ~HOST_CAP_64;
467 	}
468 
469 	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 		dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 		cap &= ~HOST_CAP_NCQ;
472 	}
473 
474 	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 		dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
476 		cap |= HOST_CAP_NCQ;
477 	}
478 
479 	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 		dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 		cap &= ~HOST_CAP_PMP;
482 	}
483 
484 	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
485 		dev_info(dev,
486 			 "controller can't do SNTF, turning off CAP_SNTF\n");
487 		cap &= ~HOST_CAP_SNTF;
488 	}
489 
490 	if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
491 		dev_info(dev,
492 			 "controller can't do DEVSLP, turning off\n");
493 		cap2 &= ~HOST_CAP2_SDS;
494 		cap2 &= ~HOST_CAP2_SADM;
495 	}
496 
497 	if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 		dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
499 		cap |= HOST_CAP_FBS;
500 	}
501 
502 	if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 		dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 		cap &= ~HOST_CAP_FBS;
505 	}
506 
507 	if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 		dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 		cap |= HOST_CAP_ALPM;
510 	}
511 
512 	if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
513 		dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
514 			 port_map, hpriv->force_port_map);
515 		port_map = hpriv->force_port_map;
516 		hpriv->saved_port_map = port_map;
517 	}
518 
519 	if (hpriv->mask_port_map) {
520 		dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
521 			port_map,
522 			port_map & hpriv->mask_port_map);
523 		port_map &= hpriv->mask_port_map;
524 	}
525 
526 	/* cross check port_map and cap.n_ports */
527 	if (port_map) {
528 		int map_ports = 0;
529 
530 		for (i = 0; i < AHCI_MAX_PORTS; i++)
531 			if (port_map & (1 << i))
532 				map_ports++;
533 
534 		/* If PI has more ports than n_ports, whine, clear
535 		 * port_map and let it be generated from n_ports.
536 		 */
537 		if (map_ports > ahci_nr_ports(cap)) {
538 			dev_warn(dev,
539 				 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 				 port_map, ahci_nr_ports(cap));
541 			port_map = 0;
542 		}
543 	}
544 
545 	/* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 	if (!port_map && vers < 0x10300) {
547 		port_map = (1 << ahci_nr_ports(cap)) - 1;
548 		dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
549 
550 		/* write the fixed up value to the PI register */
551 		hpriv->saved_port_map = port_map;
552 	}
553 
554 	/* record values to use during operation */
555 	hpriv->cap = cap;
556 	hpriv->cap2 = cap2;
557 	hpriv->version = readl(mmio + HOST_VERSION);
558 	hpriv->port_map = port_map;
559 
560 	if (!hpriv->start_engine)
561 		hpriv->start_engine = ahci_start_engine;
562 
563 	if (!hpriv->stop_engine)
564 		hpriv->stop_engine = ahci_stop_engine;
565 
566 	if (!hpriv->irq_handler)
567 		hpriv->irq_handler = ahci_single_level_irq_intr;
568 }
569 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
570 
571 /**
572  *	ahci_restore_initial_config - Restore initial config
573  *	@host: target ATA host
574  *
575  *	Restore initial config stored by ahci_save_initial_config().
576  *
577  *	LOCKING:
578  *	None.
579  */
ahci_restore_initial_config(struct ata_host * host)580 static void ahci_restore_initial_config(struct ata_host *host)
581 {
582 	struct ahci_host_priv *hpriv = host->private_data;
583 	void __iomem *mmio = hpriv->mmio;
584 
585 	writel(hpriv->saved_cap, mmio + HOST_CAP);
586 	if (hpriv->saved_cap2)
587 		writel(hpriv->saved_cap2, mmio + HOST_CAP2);
588 	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
589 	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
590 }
591 
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)592 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
593 {
594 	static const int offset[] = {
595 		[SCR_STATUS]		= PORT_SCR_STAT,
596 		[SCR_CONTROL]		= PORT_SCR_CTL,
597 		[SCR_ERROR]		= PORT_SCR_ERR,
598 		[SCR_ACTIVE]		= PORT_SCR_ACT,
599 		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
600 	};
601 	struct ahci_host_priv *hpriv = ap->host->private_data;
602 
603 	if (sc_reg < ARRAY_SIZE(offset) &&
604 	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
605 		return offset[sc_reg];
606 	return 0;
607 }
608 
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)609 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
610 {
611 	void __iomem *port_mmio = ahci_port_base(link->ap);
612 	int offset = ahci_scr_offset(link->ap, sc_reg);
613 
614 	if (offset) {
615 		*val = readl(port_mmio + offset);
616 		return 0;
617 	}
618 	return -EINVAL;
619 }
620 
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)621 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
622 {
623 	void __iomem *port_mmio = ahci_port_base(link->ap);
624 	int offset = ahci_scr_offset(link->ap, sc_reg);
625 
626 	if (offset) {
627 		writel(val, port_mmio + offset);
628 		return 0;
629 	}
630 	return -EINVAL;
631 }
632 
ahci_start_engine(struct ata_port * ap)633 void ahci_start_engine(struct ata_port *ap)
634 {
635 	void __iomem *port_mmio = ahci_port_base(ap);
636 	u32 tmp;
637 
638 	/* start DMA */
639 	tmp = readl(port_mmio + PORT_CMD);
640 	tmp |= PORT_CMD_START;
641 	writel(tmp, port_mmio + PORT_CMD);
642 	readl(port_mmio + PORT_CMD); /* flush */
643 }
644 EXPORT_SYMBOL_GPL(ahci_start_engine);
645 
ahci_stop_engine(struct ata_port * ap)646 int ahci_stop_engine(struct ata_port *ap)
647 {
648 	void __iomem *port_mmio = ahci_port_base(ap);
649 	struct ahci_host_priv *hpriv = ap->host->private_data;
650 	u32 tmp;
651 
652 	/*
653 	 * On some controllers, stopping a port's DMA engine while the port
654 	 * is in ALPM state (partial or slumber) results in failures on
655 	 * subsequent DMA engine starts.  For those controllers, put the
656 	 * port back in active state before stopping its DMA engine.
657 	 */
658 	if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
659 	    (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
660 	    ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
661 		dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
662 		return -EIO;
663 	}
664 
665 	tmp = readl(port_mmio + PORT_CMD);
666 
667 	/* check if the HBA is idle */
668 	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
669 		return 0;
670 
671 	/* setting HBA to idle */
672 	tmp &= ~PORT_CMD_START;
673 	writel(tmp, port_mmio + PORT_CMD);
674 
675 	/* wait for engine to stop. This could be as long as 500 msec */
676 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
677 				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
678 	if (tmp & PORT_CMD_LIST_ON)
679 		return -EIO;
680 
681 	return 0;
682 }
683 EXPORT_SYMBOL_GPL(ahci_stop_engine);
684 
ahci_start_fis_rx(struct ata_port * ap)685 void ahci_start_fis_rx(struct ata_port *ap)
686 {
687 	void __iomem *port_mmio = ahci_port_base(ap);
688 	struct ahci_host_priv *hpriv = ap->host->private_data;
689 	struct ahci_port_priv *pp = ap->private_data;
690 	u32 tmp;
691 
692 	/* set FIS registers */
693 	if (hpriv->cap & HOST_CAP_64)
694 		writel((pp->cmd_slot_dma >> 16) >> 16,
695 		       port_mmio + PORT_LST_ADDR_HI);
696 	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
697 
698 	if (hpriv->cap & HOST_CAP_64)
699 		writel((pp->rx_fis_dma >> 16) >> 16,
700 		       port_mmio + PORT_FIS_ADDR_HI);
701 	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
702 
703 	/* enable FIS reception */
704 	tmp = readl(port_mmio + PORT_CMD);
705 	tmp |= PORT_CMD_FIS_RX;
706 	writel(tmp, port_mmio + PORT_CMD);
707 
708 	/* flush */
709 	readl(port_mmio + PORT_CMD);
710 }
711 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
712 
ahci_stop_fis_rx(struct ata_port * ap)713 static int ahci_stop_fis_rx(struct ata_port *ap)
714 {
715 	void __iomem *port_mmio = ahci_port_base(ap);
716 	u32 tmp;
717 
718 	/* disable FIS reception */
719 	tmp = readl(port_mmio + PORT_CMD);
720 	tmp &= ~PORT_CMD_FIS_RX;
721 	writel(tmp, port_mmio + PORT_CMD);
722 
723 	/* wait for completion, spec says 500ms, give it 1000 */
724 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
725 				PORT_CMD_FIS_ON, 10, 1000);
726 	if (tmp & PORT_CMD_FIS_ON)
727 		return -EBUSY;
728 
729 	return 0;
730 }
731 
ahci_power_up(struct ata_port * ap)732 static void ahci_power_up(struct ata_port *ap)
733 {
734 	struct ahci_host_priv *hpriv = ap->host->private_data;
735 	void __iomem *port_mmio = ahci_port_base(ap);
736 	u32 cmd;
737 
738 	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
739 
740 	/* spin up device */
741 	if (hpriv->cap & HOST_CAP_SSS) {
742 		cmd |= PORT_CMD_SPIN_UP;
743 		writel(cmd, port_mmio + PORT_CMD);
744 	}
745 
746 	/* wake up link */
747 	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
748 }
749 
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)750 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
751 			unsigned int hints)
752 {
753 	struct ata_port *ap = link->ap;
754 	struct ahci_host_priv *hpriv = ap->host->private_data;
755 	struct ahci_port_priv *pp = ap->private_data;
756 	void __iomem *port_mmio = ahci_port_base(ap);
757 
758 	if (policy != ATA_LPM_MAX_POWER) {
759 		/* wakeup flag only applies to the max power policy */
760 		hints &= ~ATA_LPM_WAKE_ONLY;
761 
762 		/*
763 		 * Disable interrupts on Phy Ready. This keeps us from
764 		 * getting woken up due to spurious phy ready
765 		 * interrupts.
766 		 */
767 		pp->intr_mask &= ~PORT_IRQ_PHYRDY;
768 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
769 
770 		sata_link_scr_lpm(link, policy, false);
771 	}
772 
773 	if (hpriv->cap & HOST_CAP_ALPM) {
774 		u32 cmd = readl(port_mmio + PORT_CMD);
775 
776 		if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
777 			if (!(hints & ATA_LPM_WAKE_ONLY))
778 				cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
779 			cmd |= PORT_CMD_ICC_ACTIVE;
780 
781 			writel(cmd, port_mmio + PORT_CMD);
782 			readl(port_mmio + PORT_CMD);
783 
784 			/* wait 10ms to be sure we've come out of LPM state */
785 			ata_msleep(ap, 10);
786 
787 			if (hints & ATA_LPM_WAKE_ONLY)
788 				return 0;
789 		} else {
790 			cmd |= PORT_CMD_ALPE;
791 			if (policy == ATA_LPM_MIN_POWER)
792 				cmd |= PORT_CMD_ASP;
793 
794 			/* write out new cmd value */
795 			writel(cmd, port_mmio + PORT_CMD);
796 		}
797 	}
798 
799 	/* set aggressive device sleep */
800 	if ((hpriv->cap2 & HOST_CAP2_SDS) &&
801 	    (hpriv->cap2 & HOST_CAP2_SADM) &&
802 	    (link->device->flags & ATA_DFLAG_DEVSLP)) {
803 		if (policy == ATA_LPM_MIN_POWER)
804 			ahci_set_aggressive_devslp(ap, true);
805 		else
806 			ahci_set_aggressive_devslp(ap, false);
807 	}
808 
809 	if (policy == ATA_LPM_MAX_POWER) {
810 		sata_link_scr_lpm(link, policy, false);
811 
812 		/* turn PHYRDY IRQ back on */
813 		pp->intr_mask |= PORT_IRQ_PHYRDY;
814 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
815 	}
816 
817 	return 0;
818 }
819 
820 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)821 static void ahci_power_down(struct ata_port *ap)
822 {
823 	struct ahci_host_priv *hpriv = ap->host->private_data;
824 	void __iomem *port_mmio = ahci_port_base(ap);
825 	u32 cmd, scontrol;
826 
827 	if (!(hpriv->cap & HOST_CAP_SSS))
828 		return;
829 
830 	/* put device into listen mode, first set PxSCTL.DET to 0 */
831 	scontrol = readl(port_mmio + PORT_SCR_CTL);
832 	scontrol &= ~0xf;
833 	writel(scontrol, port_mmio + PORT_SCR_CTL);
834 
835 	/* then set PxCMD.SUD to 0 */
836 	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
837 	cmd &= ~PORT_CMD_SPIN_UP;
838 	writel(cmd, port_mmio + PORT_CMD);
839 }
840 #endif
841 
ahci_start_port(struct ata_port * ap)842 static void ahci_start_port(struct ata_port *ap)
843 {
844 	struct ahci_host_priv *hpriv = ap->host->private_data;
845 	struct ahci_port_priv *pp = ap->private_data;
846 	struct ata_link *link;
847 	struct ahci_em_priv *emp;
848 	ssize_t rc;
849 	int i;
850 
851 	/* enable FIS reception */
852 	ahci_start_fis_rx(ap);
853 
854 	/* enable DMA */
855 	if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
856 		hpriv->start_engine(ap);
857 
858 	/* turn on LEDs */
859 	if (ap->flags & ATA_FLAG_EM) {
860 		ata_for_each_link(link, ap, EDGE) {
861 			emp = &pp->em_priv[link->pmp];
862 
863 			/* EM Transmit bit maybe busy during init */
864 			for (i = 0; i < EM_MAX_RETRY; i++) {
865 				rc = ap->ops->transmit_led_message(ap,
866 							       emp->led_state,
867 							       4);
868 				/*
869 				 * If busy, give a breather but do not
870 				 * release EH ownership by using msleep()
871 				 * instead of ata_msleep().  EM Transmit
872 				 * bit is busy for the whole host and
873 				 * releasing ownership will cause other
874 				 * ports to fail the same way.
875 				 */
876 				if (rc == -EBUSY)
877 					msleep(1);
878 				else
879 					break;
880 			}
881 		}
882 	}
883 
884 	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
885 		ata_for_each_link(link, ap, EDGE)
886 			ahci_init_sw_activity(link);
887 
888 }
889 
ahci_deinit_port(struct ata_port * ap,const char ** emsg)890 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
891 {
892 	int rc;
893 	struct ahci_host_priv *hpriv = ap->host->private_data;
894 
895 	/* disable DMA */
896 	rc = hpriv->stop_engine(ap);
897 	if (rc) {
898 		*emsg = "failed to stop engine";
899 		return rc;
900 	}
901 
902 	/* disable FIS reception */
903 	rc = ahci_stop_fis_rx(ap);
904 	if (rc) {
905 		*emsg = "failed stop FIS RX";
906 		return rc;
907 	}
908 
909 	return 0;
910 }
911 
ahci_reset_controller(struct ata_host * host)912 int ahci_reset_controller(struct ata_host *host)
913 {
914 	struct ahci_host_priv *hpriv = host->private_data;
915 	void __iomem *mmio = hpriv->mmio;
916 	u32 tmp;
917 
918 	/* we must be in AHCI mode, before using anything
919 	 * AHCI-specific, such as HOST_RESET.
920 	 */
921 	ahci_enable_ahci(mmio);
922 
923 	/* global controller reset */
924 	if (!ahci_skip_host_reset) {
925 		tmp = readl(mmio + HOST_CTL);
926 		if ((tmp & HOST_RESET) == 0) {
927 			writel(tmp | HOST_RESET, mmio + HOST_CTL);
928 			readl(mmio + HOST_CTL); /* flush */
929 		}
930 
931 		/*
932 		 * to perform host reset, OS should set HOST_RESET
933 		 * and poll until this bit is read to be "0".
934 		 * reset must complete within 1 second, or
935 		 * the hardware should be considered fried.
936 		 */
937 		tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
938 					HOST_RESET, 10, 1000);
939 
940 		if (tmp & HOST_RESET) {
941 			dev_err(host->dev, "controller reset failed (0x%x)\n",
942 				tmp);
943 			return -EIO;
944 		}
945 
946 		/* turn on AHCI mode */
947 		ahci_enable_ahci(mmio);
948 
949 		/* Some registers might be cleared on reset.  Restore
950 		 * initial values.
951 		 */
952 		if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
953 			ahci_restore_initial_config(host);
954 	} else
955 		dev_info(host->dev, "skipping global host reset\n");
956 
957 	return 0;
958 }
959 EXPORT_SYMBOL_GPL(ahci_reset_controller);
960 
ahci_sw_activity(struct ata_link * link)961 static void ahci_sw_activity(struct ata_link *link)
962 {
963 	struct ata_port *ap = link->ap;
964 	struct ahci_port_priv *pp = ap->private_data;
965 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
966 
967 	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
968 		return;
969 
970 	emp->activity++;
971 	if (!timer_pending(&emp->timer))
972 		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
973 }
974 
ahci_sw_activity_blink(unsigned long arg)975 static void ahci_sw_activity_blink(unsigned long arg)
976 {
977 	struct ata_link *link = (struct ata_link *)arg;
978 	struct ata_port *ap = link->ap;
979 	struct ahci_port_priv *pp = ap->private_data;
980 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
981 	unsigned long led_message = emp->led_state;
982 	u32 activity_led_state;
983 	unsigned long flags;
984 
985 	led_message &= EM_MSG_LED_VALUE;
986 	led_message |= ap->port_no | (link->pmp << 8);
987 
988 	/* check to see if we've had activity.  If so,
989 	 * toggle state of LED and reset timer.  If not,
990 	 * turn LED to desired idle state.
991 	 */
992 	spin_lock_irqsave(ap->lock, flags);
993 	if (emp->saved_activity != emp->activity) {
994 		emp->saved_activity = emp->activity;
995 		/* get the current LED state */
996 		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
997 
998 		if (activity_led_state)
999 			activity_led_state = 0;
1000 		else
1001 			activity_led_state = 1;
1002 
1003 		/* clear old state */
1004 		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1005 
1006 		/* toggle state */
1007 		led_message |= (activity_led_state << 16);
1008 		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1009 	} else {
1010 		/* switch to idle */
1011 		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1012 		if (emp->blink_policy == BLINK_OFF)
1013 			led_message |= (1 << 16);
1014 	}
1015 	spin_unlock_irqrestore(ap->lock, flags);
1016 	ap->ops->transmit_led_message(ap, led_message, 4);
1017 }
1018 
ahci_init_sw_activity(struct ata_link * link)1019 static void ahci_init_sw_activity(struct ata_link *link)
1020 {
1021 	struct ata_port *ap = link->ap;
1022 	struct ahci_port_priv *pp = ap->private_data;
1023 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1024 
1025 	/* init activity stats, setup timer */
1026 	emp->saved_activity = emp->activity = 0;
1027 	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1028 
1029 	/* check our blink policy and set flag for link if it's enabled */
1030 	if (emp->blink_policy)
1031 		link->flags |= ATA_LFLAG_SW_ACTIVITY;
1032 }
1033 
ahci_reset_em(struct ata_host * host)1034 int ahci_reset_em(struct ata_host *host)
1035 {
1036 	struct ahci_host_priv *hpriv = host->private_data;
1037 	void __iomem *mmio = hpriv->mmio;
1038 	u32 em_ctl;
1039 
1040 	em_ctl = readl(mmio + HOST_EM_CTL);
1041 	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1042 		return -EINVAL;
1043 
1044 	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1045 	return 0;
1046 }
1047 EXPORT_SYMBOL_GPL(ahci_reset_em);
1048 
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)1049 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1050 					ssize_t size)
1051 {
1052 	struct ahci_host_priv *hpriv = ap->host->private_data;
1053 	struct ahci_port_priv *pp = ap->private_data;
1054 	void __iomem *mmio = hpriv->mmio;
1055 	u32 em_ctl;
1056 	u32 message[] = {0, 0};
1057 	unsigned long flags;
1058 	int pmp;
1059 	struct ahci_em_priv *emp;
1060 
1061 	/* get the slot number from the message */
1062 	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1063 	if (pmp < EM_MAX_SLOTS)
1064 		emp = &pp->em_priv[pmp];
1065 	else
1066 		return -EINVAL;
1067 
1068 	ahci_rpm_get_port(ap);
1069 	spin_lock_irqsave(ap->lock, flags);
1070 
1071 	/*
1072 	 * if we are still busy transmitting a previous message,
1073 	 * do not allow
1074 	 */
1075 	em_ctl = readl(mmio + HOST_EM_CTL);
1076 	if (em_ctl & EM_CTL_TM) {
1077 		spin_unlock_irqrestore(ap->lock, flags);
1078 		ahci_rpm_put_port(ap);
1079 		return -EBUSY;
1080 	}
1081 
1082 	if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1083 		/*
1084 		 * create message header - this is all zero except for
1085 		 * the message size, which is 4 bytes.
1086 		 */
1087 		message[0] |= (4 << 8);
1088 
1089 		/* ignore 0:4 of byte zero, fill in port info yourself */
1090 		message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1091 
1092 		/* write message to EM_LOC */
1093 		writel(message[0], mmio + hpriv->em_loc);
1094 		writel(message[1], mmio + hpriv->em_loc+4);
1095 
1096 		/*
1097 		 * tell hardware to transmit the message
1098 		 */
1099 		writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1100 	}
1101 
1102 	/* save off new led state for port/slot */
1103 	emp->led_state = state;
1104 
1105 	spin_unlock_irqrestore(ap->lock, flags);
1106 	ahci_rpm_put_port(ap);
1107 
1108 	return size;
1109 }
1110 
ahci_led_show(struct ata_port * ap,char * buf)1111 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1112 {
1113 	struct ahci_port_priv *pp = ap->private_data;
1114 	struct ata_link *link;
1115 	struct ahci_em_priv *emp;
1116 	int rc = 0;
1117 
1118 	ata_for_each_link(link, ap, EDGE) {
1119 		emp = &pp->em_priv[link->pmp];
1120 		rc += sprintf(buf, "%lx\n", emp->led_state);
1121 	}
1122 	return rc;
1123 }
1124 
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1125 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1126 				size_t size)
1127 {
1128 	unsigned int state;
1129 	int pmp;
1130 	struct ahci_port_priv *pp = ap->private_data;
1131 	struct ahci_em_priv *emp;
1132 
1133 	if (kstrtouint(buf, 0, &state) < 0)
1134 		return -EINVAL;
1135 
1136 	/* get the slot number from the message */
1137 	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1138 	if (pmp < EM_MAX_SLOTS) {
1139 		pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1140 		emp = &pp->em_priv[pmp];
1141 	} else {
1142 		return -EINVAL;
1143 	}
1144 
1145 	/* mask off the activity bits if we are in sw_activity
1146 	 * mode, user should turn off sw_activity before setting
1147 	 * activity led through em_message
1148 	 */
1149 	if (emp->blink_policy)
1150 		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1151 
1152 	return ap->ops->transmit_led_message(ap, state, size);
1153 }
1154 
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1155 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1156 {
1157 	struct ata_link *link = dev->link;
1158 	struct ata_port *ap = link->ap;
1159 	struct ahci_port_priv *pp = ap->private_data;
1160 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1161 	u32 port_led_state = emp->led_state;
1162 
1163 	/* save the desired Activity LED behavior */
1164 	if (val == OFF) {
1165 		/* clear LFLAG */
1166 		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1167 
1168 		/* set the LED to OFF */
1169 		port_led_state &= EM_MSG_LED_VALUE_OFF;
1170 		port_led_state |= (ap->port_no | (link->pmp << 8));
1171 		ap->ops->transmit_led_message(ap, port_led_state, 4);
1172 	} else {
1173 		link->flags |= ATA_LFLAG_SW_ACTIVITY;
1174 		if (val == BLINK_OFF) {
1175 			/* set LED to ON for idle */
1176 			port_led_state &= EM_MSG_LED_VALUE_OFF;
1177 			port_led_state |= (ap->port_no | (link->pmp << 8));
1178 			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1179 			ap->ops->transmit_led_message(ap, port_led_state, 4);
1180 		}
1181 	}
1182 	emp->blink_policy = val;
1183 	return 0;
1184 }
1185 
ahci_activity_show(struct ata_device * dev,char * buf)1186 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1187 {
1188 	struct ata_link *link = dev->link;
1189 	struct ata_port *ap = link->ap;
1190 	struct ahci_port_priv *pp = ap->private_data;
1191 	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1192 
1193 	/* display the saved value of activity behavior for this
1194 	 * disk.
1195 	 */
1196 	return sprintf(buf, "%d\n", emp->blink_policy);
1197 }
1198 
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1199 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1200 			   int port_no, void __iomem *mmio,
1201 			   void __iomem *port_mmio)
1202 {
1203 	struct ahci_host_priv *hpriv = ap->host->private_data;
1204 	const char *emsg = NULL;
1205 	int rc;
1206 	u32 tmp;
1207 
1208 	/* make sure port is not active */
1209 	rc = ahci_deinit_port(ap, &emsg);
1210 	if (rc)
1211 		dev_warn(dev, "%s (%d)\n", emsg, rc);
1212 
1213 	/* clear SError */
1214 	tmp = readl(port_mmio + PORT_SCR_ERR);
1215 	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1216 	writel(tmp, port_mmio + PORT_SCR_ERR);
1217 
1218 	/* clear port IRQ */
1219 	tmp = readl(port_mmio + PORT_IRQ_STAT);
1220 	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1221 	if (tmp)
1222 		writel(tmp, port_mmio + PORT_IRQ_STAT);
1223 
1224 	writel(1 << port_no, mmio + HOST_IRQ_STAT);
1225 
1226 	/* mark esata ports */
1227 	tmp = readl(port_mmio + PORT_CMD);
1228 	if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1229 		ap->pflags |= ATA_PFLAG_EXTERNAL;
1230 }
1231 
ahci_init_controller(struct ata_host * host)1232 void ahci_init_controller(struct ata_host *host)
1233 {
1234 	struct ahci_host_priv *hpriv = host->private_data;
1235 	void __iomem *mmio = hpriv->mmio;
1236 	int i;
1237 	void __iomem *port_mmio;
1238 	u32 tmp;
1239 
1240 	for (i = 0; i < host->n_ports; i++) {
1241 		struct ata_port *ap = host->ports[i];
1242 
1243 		port_mmio = ahci_port_base(ap);
1244 		if (ata_port_is_dummy(ap))
1245 			continue;
1246 
1247 		ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1248 	}
1249 
1250 	tmp = readl(mmio + HOST_CTL);
1251 	VPRINTK("HOST_CTL 0x%x\n", tmp);
1252 	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1253 	tmp = readl(mmio + HOST_CTL);
1254 	VPRINTK("HOST_CTL 0x%x\n", tmp);
1255 }
1256 EXPORT_SYMBOL_GPL(ahci_init_controller);
1257 
ahci_dev_config(struct ata_device * dev)1258 static void ahci_dev_config(struct ata_device *dev)
1259 {
1260 	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1261 
1262 	if (hpriv->flags & AHCI_HFLAG_SECT255) {
1263 		dev->max_sectors = 255;
1264 		ata_dev_info(dev,
1265 			     "SB600 AHCI: limiting to 255 sectors per cmd\n");
1266 	}
1267 }
1268 
ahci_dev_classify(struct ata_port * ap)1269 unsigned int ahci_dev_classify(struct ata_port *ap)
1270 {
1271 	void __iomem *port_mmio = ahci_port_base(ap);
1272 	struct ata_taskfile tf;
1273 	u32 tmp;
1274 
1275 	tmp = readl(port_mmio + PORT_SIG);
1276 	tf.lbah		= (tmp >> 24)	& 0xff;
1277 	tf.lbam		= (tmp >> 16)	& 0xff;
1278 	tf.lbal		= (tmp >> 8)	& 0xff;
1279 	tf.nsect	= (tmp)		& 0xff;
1280 
1281 	return ata_dev_classify(&tf);
1282 }
1283 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1284 
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1285 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1286 			u32 opts)
1287 {
1288 	dma_addr_t cmd_tbl_dma;
1289 
1290 	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1291 
1292 	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1293 	pp->cmd_slot[tag].status = 0;
1294 	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1295 	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1296 }
1297 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1298 
ahci_kick_engine(struct ata_port * ap)1299 int ahci_kick_engine(struct ata_port *ap)
1300 {
1301 	void __iomem *port_mmio = ahci_port_base(ap);
1302 	struct ahci_host_priv *hpriv = ap->host->private_data;
1303 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1304 	u32 tmp;
1305 	int busy, rc;
1306 
1307 	/* stop engine */
1308 	rc = hpriv->stop_engine(ap);
1309 	if (rc)
1310 		goto out_restart;
1311 
1312 	/* need to do CLO?
1313 	 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1314 	 */
1315 	busy = status & (ATA_BUSY | ATA_DRQ);
1316 	if (!busy && !sata_pmp_attached(ap)) {
1317 		rc = 0;
1318 		goto out_restart;
1319 	}
1320 
1321 	if (!(hpriv->cap & HOST_CAP_CLO)) {
1322 		rc = -EOPNOTSUPP;
1323 		goto out_restart;
1324 	}
1325 
1326 	/* perform CLO */
1327 	tmp = readl(port_mmio + PORT_CMD);
1328 	tmp |= PORT_CMD_CLO;
1329 	writel(tmp, port_mmio + PORT_CMD);
1330 
1331 	rc = 0;
1332 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1333 				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1334 	if (tmp & PORT_CMD_CLO)
1335 		rc = -EIO;
1336 
1337 	/* restart engine */
1338  out_restart:
1339 	hpriv->start_engine(ap);
1340 	return rc;
1341 }
1342 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1343 
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned long timeout_msec)1344 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1345 				struct ata_taskfile *tf, int is_cmd, u16 flags,
1346 				unsigned long timeout_msec)
1347 {
1348 	const u32 cmd_fis_len = 5; /* five dwords */
1349 	struct ahci_port_priv *pp = ap->private_data;
1350 	void __iomem *port_mmio = ahci_port_base(ap);
1351 	u8 *fis = pp->cmd_tbl;
1352 	u32 tmp;
1353 
1354 	/* prep the command */
1355 	ata_tf_to_fis(tf, pmp, is_cmd, fis);
1356 	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1357 
1358 	/* set port value for softreset of Port Multiplier */
1359 	if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1360 		tmp = readl(port_mmio + PORT_FBS);
1361 		tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1362 		tmp |= pmp << PORT_FBS_DEV_OFFSET;
1363 		writel(tmp, port_mmio + PORT_FBS);
1364 		pp->fbs_last_dev = pmp;
1365 	}
1366 
1367 	/* issue & wait */
1368 	writel(1, port_mmio + PORT_CMD_ISSUE);
1369 
1370 	if (timeout_msec) {
1371 		tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1372 					0x1, 0x1, 1, timeout_msec);
1373 		if (tmp & 0x1) {
1374 			ahci_kick_engine(ap);
1375 			return -EBUSY;
1376 		}
1377 	} else
1378 		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
1379 
1380 	return 0;
1381 }
1382 
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1383 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1384 		      int pmp, unsigned long deadline,
1385 		      int (*check_ready)(struct ata_link *link))
1386 {
1387 	struct ata_port *ap = link->ap;
1388 	struct ahci_host_priv *hpriv = ap->host->private_data;
1389 	struct ahci_port_priv *pp = ap->private_data;
1390 	const char *reason = NULL;
1391 	unsigned long now, msecs;
1392 	struct ata_taskfile tf;
1393 	bool fbs_disabled = false;
1394 	int rc;
1395 
1396 	DPRINTK("ENTER\n");
1397 
1398 	/* prepare for SRST (AHCI-1.1 10.4.1) */
1399 	rc = ahci_kick_engine(ap);
1400 	if (rc && rc != -EOPNOTSUPP)
1401 		ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1402 
1403 	/*
1404 	 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1405 	 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1406 	 * that is attached to port multiplier.
1407 	 */
1408 	if (!ata_is_host_link(link) && pp->fbs_enabled) {
1409 		ahci_disable_fbs(ap);
1410 		fbs_disabled = true;
1411 	}
1412 
1413 	ata_tf_init(link->device, &tf);
1414 
1415 	/* issue the first H2D Register FIS */
1416 	msecs = 0;
1417 	now = jiffies;
1418 	if (time_after(deadline, now))
1419 		msecs = jiffies_to_msecs(deadline - now);
1420 
1421 	tf.ctl |= ATA_SRST;
1422 	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1423 				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1424 		rc = -EIO;
1425 		reason = "1st FIS failed";
1426 		goto fail;
1427 	}
1428 
1429 	/* spec says at least 5us, but be generous and sleep for 1ms */
1430 	ata_msleep(ap, 1);
1431 
1432 	/* issue the second H2D Register FIS */
1433 	tf.ctl &= ~ATA_SRST;
1434 	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1435 
1436 	/* wait for link to become ready */
1437 	rc = ata_wait_after_reset(link, deadline, check_ready);
1438 	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1439 		/*
1440 		 * Workaround for cases where link online status can't
1441 		 * be trusted.  Treat device readiness timeout as link
1442 		 * offline.
1443 		 */
1444 		ata_link_info(link, "device not ready, treating as offline\n");
1445 		*class = ATA_DEV_NONE;
1446 	} else if (rc) {
1447 		/* link occupied, -ENODEV too is an error */
1448 		reason = "device not ready";
1449 		goto fail;
1450 	} else
1451 		*class = ahci_dev_classify(ap);
1452 
1453 	/* re-enable FBS if disabled before */
1454 	if (fbs_disabled)
1455 		ahci_enable_fbs(ap);
1456 
1457 	DPRINTK("EXIT, class=%u\n", *class);
1458 	return 0;
1459 
1460  fail:
1461 	ata_link_err(link, "softreset failed (%s)\n", reason);
1462 	return rc;
1463 }
1464 
ahci_check_ready(struct ata_link * link)1465 int ahci_check_ready(struct ata_link *link)
1466 {
1467 	void __iomem *port_mmio = ahci_port_base(link->ap);
1468 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1469 
1470 	return ata_check_ready(status);
1471 }
1472 EXPORT_SYMBOL_GPL(ahci_check_ready);
1473 
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1474 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1475 			  unsigned long deadline)
1476 {
1477 	int pmp = sata_srst_pmp(link);
1478 
1479 	DPRINTK("ENTER\n");
1480 
1481 	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1482 }
1483 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1484 
ahci_bad_pmp_check_ready(struct ata_link * link)1485 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1486 {
1487 	void __iomem *port_mmio = ahci_port_base(link->ap);
1488 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1489 	u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1490 
1491 	/*
1492 	 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1493 	 * which can save timeout delay.
1494 	 */
1495 	if (irq_status & PORT_IRQ_BAD_PMP)
1496 		return -EIO;
1497 
1498 	return ata_check_ready(status);
1499 }
1500 
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1501 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1502 				    unsigned long deadline)
1503 {
1504 	struct ata_port *ap = link->ap;
1505 	void __iomem *port_mmio = ahci_port_base(ap);
1506 	int pmp = sata_srst_pmp(link);
1507 	int rc;
1508 	u32 irq_sts;
1509 
1510 	DPRINTK("ENTER\n");
1511 
1512 	rc = ahci_do_softreset(link, class, pmp, deadline,
1513 			       ahci_bad_pmp_check_ready);
1514 
1515 	/*
1516 	 * Soft reset fails with IPMS set when PMP is enabled but
1517 	 * SATA HDD/ODD is connected to SATA port, do soft reset
1518 	 * again to port 0.
1519 	 */
1520 	if (rc == -EIO) {
1521 		irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1522 		if (irq_sts & PORT_IRQ_BAD_PMP) {
1523 			ata_link_warn(link,
1524 					"applying PMP SRST workaround "
1525 					"and retrying\n");
1526 			rc = ahci_do_softreset(link, class, 0, deadline,
1527 					       ahci_check_ready);
1528 		}
1529 	}
1530 
1531 	return rc;
1532 }
1533 
ahci_do_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline,bool * online)1534 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1535 		      unsigned long deadline, bool *online)
1536 {
1537 	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1538 	struct ata_port *ap = link->ap;
1539 	struct ahci_port_priv *pp = ap->private_data;
1540 	struct ahci_host_priv *hpriv = ap->host->private_data;
1541 	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1542 	struct ata_taskfile tf;
1543 	int rc;
1544 
1545 	DPRINTK("ENTER\n");
1546 
1547 	hpriv->stop_engine(ap);
1548 
1549 	/* clear D2H reception area to properly wait for D2H FIS */
1550 	ata_tf_init(link->device, &tf);
1551 	tf.command = ATA_BUSY;
1552 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1553 
1554 	rc = sata_link_hardreset(link, timing, deadline, online,
1555 				 ahci_check_ready);
1556 
1557 	hpriv->start_engine(ap);
1558 
1559 	if (*online)
1560 		*class = ahci_dev_classify(ap);
1561 
1562 	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1563 	return rc;
1564 }
1565 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1566 
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1567 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1568 			  unsigned long deadline)
1569 {
1570 	bool online;
1571 
1572 	return ahci_do_hardreset(link, class, deadline, &online);
1573 }
1574 
ahci_postreset(struct ata_link * link,unsigned int * class)1575 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1576 {
1577 	struct ata_port *ap = link->ap;
1578 	void __iomem *port_mmio = ahci_port_base(ap);
1579 	u32 new_tmp, tmp;
1580 
1581 	ata_std_postreset(link, class);
1582 
1583 	/* Make sure port's ATAPI bit is set appropriately */
1584 	new_tmp = tmp = readl(port_mmio + PORT_CMD);
1585 	if (*class == ATA_DEV_ATAPI)
1586 		new_tmp |= PORT_CMD_ATAPI;
1587 	else
1588 		new_tmp &= ~PORT_CMD_ATAPI;
1589 	if (new_tmp != tmp) {
1590 		writel(new_tmp, port_mmio + PORT_CMD);
1591 		readl(port_mmio + PORT_CMD); /* flush */
1592 	}
1593 }
1594 
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1595 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1596 {
1597 	struct scatterlist *sg;
1598 	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1599 	unsigned int si;
1600 
1601 	VPRINTK("ENTER\n");
1602 
1603 	/*
1604 	 * Next, the S/G list.
1605 	 */
1606 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1607 		dma_addr_t addr = sg_dma_address(sg);
1608 		u32 sg_len = sg_dma_len(sg);
1609 
1610 		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1611 		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1612 		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1613 	}
1614 
1615 	return si;
1616 }
1617 
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1618 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1619 {
1620 	struct ata_port *ap = qc->ap;
1621 	struct ahci_port_priv *pp = ap->private_data;
1622 
1623 	if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1624 		return ata_std_qc_defer(qc);
1625 	else
1626 		return sata_pmp_qc_defer_cmd_switch(qc);
1627 }
1628 
ahci_qc_prep(struct ata_queued_cmd * qc)1629 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1630 {
1631 	struct ata_port *ap = qc->ap;
1632 	struct ahci_port_priv *pp = ap->private_data;
1633 	int is_atapi = ata_is_atapi(qc->tf.protocol);
1634 	void *cmd_tbl;
1635 	u32 opts;
1636 	const u32 cmd_fis_len = 5; /* five dwords */
1637 	unsigned int n_elem;
1638 
1639 	/*
1640 	 * Fill in command table information.  First, the header,
1641 	 * a SATA Register - Host to Device command FIS.
1642 	 */
1643 	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1644 
1645 	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1646 	if (is_atapi) {
1647 		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1648 		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1649 	}
1650 
1651 	n_elem = 0;
1652 	if (qc->flags & ATA_QCFLAG_DMAMAP)
1653 		n_elem = ahci_fill_sg(qc, cmd_tbl);
1654 
1655 	/*
1656 	 * Fill in command slot information.
1657 	 */
1658 	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1659 	if (qc->tf.flags & ATA_TFLAG_WRITE)
1660 		opts |= AHCI_CMD_WRITE;
1661 	if (is_atapi)
1662 		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1663 
1664 	ahci_fill_cmd_slot(pp, qc->tag, opts);
1665 }
1666 
ahci_fbs_dec_intr(struct ata_port * ap)1667 static void ahci_fbs_dec_intr(struct ata_port *ap)
1668 {
1669 	struct ahci_port_priv *pp = ap->private_data;
1670 	void __iomem *port_mmio = ahci_port_base(ap);
1671 	u32 fbs = readl(port_mmio + PORT_FBS);
1672 	int retries = 3;
1673 
1674 	DPRINTK("ENTER\n");
1675 	BUG_ON(!pp->fbs_enabled);
1676 
1677 	/* time to wait for DEC is not specified by AHCI spec,
1678 	 * add a retry loop for safety.
1679 	 */
1680 	writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1681 	fbs = readl(port_mmio + PORT_FBS);
1682 	while ((fbs & PORT_FBS_DEC) && retries--) {
1683 		udelay(1);
1684 		fbs = readl(port_mmio + PORT_FBS);
1685 	}
1686 
1687 	if (fbs & PORT_FBS_DEC)
1688 		dev_err(ap->host->dev, "failed to clear device error\n");
1689 }
1690 
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1691 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1692 {
1693 	struct ahci_host_priv *hpriv = ap->host->private_data;
1694 	struct ahci_port_priv *pp = ap->private_data;
1695 	struct ata_eh_info *host_ehi = &ap->link.eh_info;
1696 	struct ata_link *link = NULL;
1697 	struct ata_queued_cmd *active_qc;
1698 	struct ata_eh_info *active_ehi;
1699 	bool fbs_need_dec = false;
1700 	u32 serror;
1701 
1702 	/* determine active link with error */
1703 	if (pp->fbs_enabled) {
1704 		void __iomem *port_mmio = ahci_port_base(ap);
1705 		u32 fbs = readl(port_mmio + PORT_FBS);
1706 		int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1707 
1708 		if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1709 			link = &ap->pmp_link[pmp];
1710 			fbs_need_dec = true;
1711 		}
1712 
1713 	} else
1714 		ata_for_each_link(link, ap, EDGE)
1715 			if (ata_link_active(link))
1716 				break;
1717 
1718 	if (!link)
1719 		link = &ap->link;
1720 
1721 	active_qc = ata_qc_from_tag(ap, link->active_tag);
1722 	active_ehi = &link->eh_info;
1723 
1724 	/* record irq stat */
1725 	ata_ehi_clear_desc(host_ehi);
1726 	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1727 
1728 	/* AHCI needs SError cleared; otherwise, it might lock up */
1729 	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1730 	ahci_scr_write(&ap->link, SCR_ERROR, serror);
1731 	host_ehi->serror |= serror;
1732 
1733 	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
1734 	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1735 		irq_stat &= ~PORT_IRQ_IF_ERR;
1736 
1737 	if (irq_stat & PORT_IRQ_TF_ERR) {
1738 		/* If qc is active, charge it; otherwise, the active
1739 		 * link.  There's no active qc on NCQ errors.  It will
1740 		 * be determined by EH by reading log page 10h.
1741 		 */
1742 		if (active_qc)
1743 			active_qc->err_mask |= AC_ERR_DEV;
1744 		else
1745 			active_ehi->err_mask |= AC_ERR_DEV;
1746 
1747 		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1748 			host_ehi->serror &= ~SERR_INTERNAL;
1749 	}
1750 
1751 	if (irq_stat & PORT_IRQ_UNK_FIS) {
1752 		u32 *unk = pp->rx_fis + RX_FIS_UNK;
1753 
1754 		active_ehi->err_mask |= AC_ERR_HSM;
1755 		active_ehi->action |= ATA_EH_RESET;
1756 		ata_ehi_push_desc(active_ehi,
1757 				  "unknown FIS %08x %08x %08x %08x" ,
1758 				  unk[0], unk[1], unk[2], unk[3]);
1759 	}
1760 
1761 	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1762 		active_ehi->err_mask |= AC_ERR_HSM;
1763 		active_ehi->action |= ATA_EH_RESET;
1764 		ata_ehi_push_desc(active_ehi, "incorrect PMP");
1765 	}
1766 
1767 	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1768 		host_ehi->err_mask |= AC_ERR_HOST_BUS;
1769 		host_ehi->action |= ATA_EH_RESET;
1770 		ata_ehi_push_desc(host_ehi, "host bus error");
1771 	}
1772 
1773 	if (irq_stat & PORT_IRQ_IF_ERR) {
1774 		if (fbs_need_dec)
1775 			active_ehi->err_mask |= AC_ERR_DEV;
1776 		else {
1777 			host_ehi->err_mask |= AC_ERR_ATA_BUS;
1778 			host_ehi->action |= ATA_EH_RESET;
1779 		}
1780 
1781 		ata_ehi_push_desc(host_ehi, "interface fatal error");
1782 	}
1783 
1784 	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1785 		ata_ehi_hotplugged(host_ehi);
1786 		ata_ehi_push_desc(host_ehi, "%s",
1787 			irq_stat & PORT_IRQ_CONNECT ?
1788 			"connection status changed" : "PHY RDY changed");
1789 	}
1790 
1791 	/* okay, let's hand over to EH */
1792 
1793 	if (irq_stat & PORT_IRQ_FREEZE)
1794 		ata_port_freeze(ap);
1795 	else if (fbs_need_dec) {
1796 		ata_link_abort(link);
1797 		ahci_fbs_dec_intr(ap);
1798 	} else
1799 		ata_port_abort(ap);
1800 }
1801 
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1802 static void ahci_handle_port_interrupt(struct ata_port *ap,
1803 				       void __iomem *port_mmio, u32 status)
1804 {
1805 	struct ata_eh_info *ehi = &ap->link.eh_info;
1806 	struct ahci_port_priv *pp = ap->private_data;
1807 	struct ahci_host_priv *hpriv = ap->host->private_data;
1808 	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1809 	u32 qc_active = 0;
1810 	int rc;
1811 
1812 	/* ignore BAD_PMP while resetting */
1813 	if (unlikely(resetting))
1814 		status &= ~PORT_IRQ_BAD_PMP;
1815 
1816 	if (sata_lpm_ignore_phy_events(&ap->link)) {
1817 		status &= ~PORT_IRQ_PHYRDY;
1818 		ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1819 	}
1820 
1821 	if (unlikely(status & PORT_IRQ_ERROR)) {
1822 		ahci_error_intr(ap, status);
1823 		return;
1824 	}
1825 
1826 	if (status & PORT_IRQ_SDB_FIS) {
1827 		/* If SNotification is available, leave notification
1828 		 * handling to sata_async_notification().  If not,
1829 		 * emulate it by snooping SDB FIS RX area.
1830 		 *
1831 		 * Snooping FIS RX area is probably cheaper than
1832 		 * poking SNotification but some constrollers which
1833 		 * implement SNotification, ICH9 for example, don't
1834 		 * store AN SDB FIS into receive area.
1835 		 */
1836 		if (hpriv->cap & HOST_CAP_SNTF)
1837 			sata_async_notification(ap);
1838 		else {
1839 			/* If the 'N' bit in word 0 of the FIS is set,
1840 			 * we just received asynchronous notification.
1841 			 * Tell libata about it.
1842 			 *
1843 			 * Lack of SNotification should not appear in
1844 			 * ahci 1.2, so the workaround is unnecessary
1845 			 * when FBS is enabled.
1846 			 */
1847 			if (pp->fbs_enabled)
1848 				WARN_ON_ONCE(1);
1849 			else {
1850 				const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1851 				u32 f0 = le32_to_cpu(f[0]);
1852 				if (f0 & (1 << 15))
1853 					sata_async_notification(ap);
1854 			}
1855 		}
1856 	}
1857 
1858 	/* pp->active_link is not reliable once FBS is enabled, both
1859 	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1860 	 * NCQ and non-NCQ commands may be in flight at the same time.
1861 	 */
1862 	if (pp->fbs_enabled) {
1863 		if (ap->qc_active) {
1864 			qc_active = readl(port_mmio + PORT_SCR_ACT);
1865 			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1866 		}
1867 	} else {
1868 		/* pp->active_link is valid iff any command is in flight */
1869 		if (ap->qc_active && pp->active_link->sactive)
1870 			qc_active = readl(port_mmio + PORT_SCR_ACT);
1871 		else
1872 			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1873 	}
1874 
1875 
1876 	rc = ata_qc_complete_multiple(ap, qc_active);
1877 
1878 	/* while resetting, invalid completions are expected */
1879 	if (unlikely(rc < 0 && !resetting)) {
1880 		ehi->err_mask |= AC_ERR_HSM;
1881 		ehi->action |= ATA_EH_RESET;
1882 		ata_port_freeze(ap);
1883 	}
1884 }
1885 
ahci_port_intr(struct ata_port * ap)1886 static void ahci_port_intr(struct ata_port *ap)
1887 {
1888 	void __iomem *port_mmio = ahci_port_base(ap);
1889 	u32 status;
1890 
1891 	status = readl(port_mmio + PORT_IRQ_STAT);
1892 	writel(status, port_mmio + PORT_IRQ_STAT);
1893 
1894 	ahci_handle_port_interrupt(ap, port_mmio, status);
1895 }
1896 
ahci_multi_irqs_intr_hard(int irq,void * dev_instance)1897 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1898 {
1899 	struct ata_port *ap = dev_instance;
1900 	void __iomem *port_mmio = ahci_port_base(ap);
1901 	u32 status;
1902 
1903 	VPRINTK("ENTER\n");
1904 
1905 	status = readl(port_mmio + PORT_IRQ_STAT);
1906 	writel(status, port_mmio + PORT_IRQ_STAT);
1907 
1908 	spin_lock(ap->lock);
1909 	ahci_handle_port_interrupt(ap, port_mmio, status);
1910 	spin_unlock(ap->lock);
1911 
1912 	VPRINTK("EXIT\n");
1913 
1914 	return IRQ_HANDLED;
1915 }
1916 
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1917 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1918 {
1919 	unsigned int i, handled = 0;
1920 
1921 	for (i = 0; i < host->n_ports; i++) {
1922 		struct ata_port *ap;
1923 
1924 		if (!(irq_masked & (1 << i)))
1925 			continue;
1926 
1927 		ap = host->ports[i];
1928 		if (ap) {
1929 			ahci_port_intr(ap);
1930 			VPRINTK("port %u\n", i);
1931 		} else {
1932 			VPRINTK("port %u (no irq)\n", i);
1933 			if (ata_ratelimit())
1934 				dev_warn(host->dev,
1935 					 "interrupt on disabled port %u\n", i);
1936 		}
1937 
1938 		handled = 1;
1939 	}
1940 
1941 	return handled;
1942 }
1943 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1944 
ahci_single_level_irq_intr(int irq,void * dev_instance)1945 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1946 {
1947 	struct ata_host *host = dev_instance;
1948 	struct ahci_host_priv *hpriv;
1949 	unsigned int rc = 0;
1950 	void __iomem *mmio;
1951 	u32 irq_stat, irq_masked;
1952 
1953 	VPRINTK("ENTER\n");
1954 
1955 	hpriv = host->private_data;
1956 	mmio = hpriv->mmio;
1957 
1958 	/* sigh.  0xffffffff is a valid return from h/w */
1959 	irq_stat = readl(mmio + HOST_IRQ_STAT);
1960 	if (!irq_stat)
1961 		return IRQ_NONE;
1962 
1963 	irq_masked = irq_stat & hpriv->port_map;
1964 
1965 	spin_lock(&host->lock);
1966 
1967 	rc = ahci_handle_port_intr(host, irq_masked);
1968 
1969 	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
1970 	 * it should be cleared after all the port events are cleared;
1971 	 * otherwise, it will raise a spurious interrupt after each
1972 	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
1973 	 * information.
1974 	 *
1975 	 * Also, use the unmasked value to clear interrupt as spurious
1976 	 * pending event on a dummy port might cause screaming IRQ.
1977 	 */
1978 	writel(irq_stat, mmio + HOST_IRQ_STAT);
1979 
1980 	spin_unlock(&host->lock);
1981 
1982 	VPRINTK("EXIT\n");
1983 
1984 	return IRQ_RETVAL(rc);
1985 }
1986 
ahci_qc_issue(struct ata_queued_cmd * qc)1987 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1988 {
1989 	struct ata_port *ap = qc->ap;
1990 	void __iomem *port_mmio = ahci_port_base(ap);
1991 	struct ahci_port_priv *pp = ap->private_data;
1992 
1993 	/* Keep track of the currently active link.  It will be used
1994 	 * in completion path to determine whether NCQ phase is in
1995 	 * progress.
1996 	 */
1997 	pp->active_link = qc->dev->link;
1998 
1999 	if (ata_is_ncq(qc->tf.protocol))
2000 		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2001 
2002 	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2003 		u32 fbs = readl(port_mmio + PORT_FBS);
2004 		fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2005 		fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2006 		writel(fbs, port_mmio + PORT_FBS);
2007 		pp->fbs_last_dev = qc->dev->link->pmp;
2008 	}
2009 
2010 	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2011 
2012 	ahci_sw_activity(qc->dev->link);
2013 
2014 	return 0;
2015 }
2016 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2017 
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)2018 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2019 {
2020 	struct ahci_port_priv *pp = qc->ap->private_data;
2021 	u8 *rx_fis = pp->rx_fis;
2022 
2023 	if (pp->fbs_enabled)
2024 		rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2025 
2026 	/*
2027 	 * After a successful execution of an ATA PIO data-in command,
2028 	 * the device doesn't send D2H Reg FIS to update the TF and
2029 	 * the host should take TF and E_Status from the preceding PIO
2030 	 * Setup FIS.
2031 	 */
2032 	if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2033 	    !(qc->flags & ATA_QCFLAG_FAILED)) {
2034 		ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2035 		qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2036 	} else
2037 		ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2038 
2039 	return true;
2040 }
2041 
ahci_freeze(struct ata_port * ap)2042 static void ahci_freeze(struct ata_port *ap)
2043 {
2044 	void __iomem *port_mmio = ahci_port_base(ap);
2045 
2046 	/* turn IRQ off */
2047 	writel(0, port_mmio + PORT_IRQ_MASK);
2048 }
2049 
ahci_thaw(struct ata_port * ap)2050 static void ahci_thaw(struct ata_port *ap)
2051 {
2052 	struct ahci_host_priv *hpriv = ap->host->private_data;
2053 	void __iomem *mmio = hpriv->mmio;
2054 	void __iomem *port_mmio = ahci_port_base(ap);
2055 	u32 tmp;
2056 	struct ahci_port_priv *pp = ap->private_data;
2057 
2058 	/* clear IRQ */
2059 	tmp = readl(port_mmio + PORT_IRQ_STAT);
2060 	writel(tmp, port_mmio + PORT_IRQ_STAT);
2061 	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2062 
2063 	/* turn IRQ back on */
2064 	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2065 }
2066 
ahci_error_handler(struct ata_port * ap)2067 void ahci_error_handler(struct ata_port *ap)
2068 {
2069 	struct ahci_host_priv *hpriv = ap->host->private_data;
2070 
2071 	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2072 		/* restart engine */
2073 		hpriv->stop_engine(ap);
2074 		hpriv->start_engine(ap);
2075 	}
2076 
2077 	sata_pmp_error_handler(ap);
2078 
2079 	if (!ata_dev_enabled(ap->link.device))
2080 		hpriv->stop_engine(ap);
2081 }
2082 EXPORT_SYMBOL_GPL(ahci_error_handler);
2083 
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2084 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2085 {
2086 	struct ata_port *ap = qc->ap;
2087 
2088 	/* make DMA engine forget about the failed command */
2089 	if (qc->flags & ATA_QCFLAG_FAILED)
2090 		ahci_kick_engine(ap);
2091 }
2092 
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2093 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2094 {
2095 	struct ahci_host_priv *hpriv = ap->host->private_data;
2096 	void __iomem *port_mmio = ahci_port_base(ap);
2097 	struct ata_device *dev = ap->link.device;
2098 	u32 devslp, dm, dito, mdat, deto, dito_conf;
2099 	int rc;
2100 	unsigned int err_mask;
2101 
2102 	devslp = readl(port_mmio + PORT_DEVSLP);
2103 	if (!(devslp & PORT_DEVSLP_DSP)) {
2104 		dev_info(ap->host->dev, "port does not support device sleep\n");
2105 		return;
2106 	}
2107 
2108 	/* disable device sleep */
2109 	if (!sleep) {
2110 		if (devslp & PORT_DEVSLP_ADSE) {
2111 			writel(devslp & ~PORT_DEVSLP_ADSE,
2112 			       port_mmio + PORT_DEVSLP);
2113 			err_mask = ata_dev_set_feature(dev,
2114 						       SETFEATURES_SATA_DISABLE,
2115 						       SATA_DEVSLP);
2116 			if (err_mask && err_mask != AC_ERR_DEV)
2117 				ata_dev_warn(dev, "failed to disable DEVSLP\n");
2118 		}
2119 		return;
2120 	}
2121 
2122 	dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2123 	dito = devslp_idle_timeout / (dm + 1);
2124 	if (dito > 0x3ff)
2125 		dito = 0x3ff;
2126 
2127 	dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2128 
2129 	/* device sleep was already enabled and same dito */
2130 	if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2131 		return;
2132 
2133 	/* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2134 	rc = hpriv->stop_engine(ap);
2135 	if (rc)
2136 		return;
2137 
2138 	/* Use the nominal value 10 ms if the read MDAT is zero,
2139 	 * the nominal value of DETO is 20 ms.
2140 	 */
2141 	if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2142 	    ATA_LOG_DEVSLP_VALID_MASK) {
2143 		mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2144 		       ATA_LOG_DEVSLP_MDAT_MASK;
2145 		if (!mdat)
2146 			mdat = 10;
2147 		deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2148 		if (!deto)
2149 			deto = 20;
2150 	} else {
2151 		mdat = 10;
2152 		deto = 20;
2153 	}
2154 
2155 	/* Make dito, mdat, deto bits to 0s */
2156 	devslp &= ~GENMASK_ULL(24, 2);
2157 	devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2158 		   (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2159 		   (deto << PORT_DEVSLP_DETO_OFFSET) |
2160 		   PORT_DEVSLP_ADSE);
2161 	writel(devslp, port_mmio + PORT_DEVSLP);
2162 
2163 	hpriv->start_engine(ap);
2164 
2165 	/* enable device sleep feature for the drive */
2166 	err_mask = ata_dev_set_feature(dev,
2167 				       SETFEATURES_SATA_ENABLE,
2168 				       SATA_DEVSLP);
2169 	if (err_mask && err_mask != AC_ERR_DEV)
2170 		ata_dev_warn(dev, "failed to enable DEVSLP\n");
2171 }
2172 
ahci_enable_fbs(struct ata_port * ap)2173 static void ahci_enable_fbs(struct ata_port *ap)
2174 {
2175 	struct ahci_host_priv *hpriv = ap->host->private_data;
2176 	struct ahci_port_priv *pp = ap->private_data;
2177 	void __iomem *port_mmio = ahci_port_base(ap);
2178 	u32 fbs;
2179 	int rc;
2180 
2181 	if (!pp->fbs_supported)
2182 		return;
2183 
2184 	fbs = readl(port_mmio + PORT_FBS);
2185 	if (fbs & PORT_FBS_EN) {
2186 		pp->fbs_enabled = true;
2187 		pp->fbs_last_dev = -1; /* initialization */
2188 		return;
2189 	}
2190 
2191 	rc = hpriv->stop_engine(ap);
2192 	if (rc)
2193 		return;
2194 
2195 	writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2196 	fbs = readl(port_mmio + PORT_FBS);
2197 	if (fbs & PORT_FBS_EN) {
2198 		dev_info(ap->host->dev, "FBS is enabled\n");
2199 		pp->fbs_enabled = true;
2200 		pp->fbs_last_dev = -1; /* initialization */
2201 	} else
2202 		dev_err(ap->host->dev, "Failed to enable FBS\n");
2203 
2204 	hpriv->start_engine(ap);
2205 }
2206 
ahci_disable_fbs(struct ata_port * ap)2207 static void ahci_disable_fbs(struct ata_port *ap)
2208 {
2209 	struct ahci_host_priv *hpriv = ap->host->private_data;
2210 	struct ahci_port_priv *pp = ap->private_data;
2211 	void __iomem *port_mmio = ahci_port_base(ap);
2212 	u32 fbs;
2213 	int rc;
2214 
2215 	if (!pp->fbs_supported)
2216 		return;
2217 
2218 	fbs = readl(port_mmio + PORT_FBS);
2219 	if ((fbs & PORT_FBS_EN) == 0) {
2220 		pp->fbs_enabled = false;
2221 		return;
2222 	}
2223 
2224 	rc = hpriv->stop_engine(ap);
2225 	if (rc)
2226 		return;
2227 
2228 	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2229 	fbs = readl(port_mmio + PORT_FBS);
2230 	if (fbs & PORT_FBS_EN)
2231 		dev_err(ap->host->dev, "Failed to disable FBS\n");
2232 	else {
2233 		dev_info(ap->host->dev, "FBS is disabled\n");
2234 		pp->fbs_enabled = false;
2235 	}
2236 
2237 	hpriv->start_engine(ap);
2238 }
2239 
ahci_pmp_attach(struct ata_port * ap)2240 static void ahci_pmp_attach(struct ata_port *ap)
2241 {
2242 	void __iomem *port_mmio = ahci_port_base(ap);
2243 	struct ahci_port_priv *pp = ap->private_data;
2244 	u32 cmd;
2245 
2246 	cmd = readl(port_mmio + PORT_CMD);
2247 	cmd |= PORT_CMD_PMP;
2248 	writel(cmd, port_mmio + PORT_CMD);
2249 
2250 	ahci_enable_fbs(ap);
2251 
2252 	pp->intr_mask |= PORT_IRQ_BAD_PMP;
2253 
2254 	/*
2255 	 * We must not change the port interrupt mask register if the
2256 	 * port is marked frozen, the value in pp->intr_mask will be
2257 	 * restored later when the port is thawed.
2258 	 *
2259 	 * Note that during initialization, the port is marked as
2260 	 * frozen since the irq handler is not yet registered.
2261 	 */
2262 	if (!(ap->pflags & ATA_PFLAG_FROZEN))
2263 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2264 }
2265 
ahci_pmp_detach(struct ata_port * ap)2266 static void ahci_pmp_detach(struct ata_port *ap)
2267 {
2268 	void __iomem *port_mmio = ahci_port_base(ap);
2269 	struct ahci_port_priv *pp = ap->private_data;
2270 	u32 cmd;
2271 
2272 	ahci_disable_fbs(ap);
2273 
2274 	cmd = readl(port_mmio + PORT_CMD);
2275 	cmd &= ~PORT_CMD_PMP;
2276 	writel(cmd, port_mmio + PORT_CMD);
2277 
2278 	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2279 
2280 	/* see comment above in ahci_pmp_attach() */
2281 	if (!(ap->pflags & ATA_PFLAG_FROZEN))
2282 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2283 }
2284 
ahci_port_resume(struct ata_port * ap)2285 int ahci_port_resume(struct ata_port *ap)
2286 {
2287 	ahci_rpm_get_port(ap);
2288 
2289 	ahci_power_up(ap);
2290 	ahci_start_port(ap);
2291 
2292 	if (sata_pmp_attached(ap))
2293 		ahci_pmp_attach(ap);
2294 	else
2295 		ahci_pmp_detach(ap);
2296 
2297 	return 0;
2298 }
2299 EXPORT_SYMBOL_GPL(ahci_port_resume);
2300 
2301 #ifdef CONFIG_PM
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2302 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2303 {
2304 	const char *emsg = NULL;
2305 	int rc;
2306 
2307 	rc = ahci_deinit_port(ap, &emsg);
2308 	if (rc == 0)
2309 		ahci_power_down(ap);
2310 	else {
2311 		ata_port_err(ap, "%s (%d)\n", emsg, rc);
2312 		ata_port_freeze(ap);
2313 	}
2314 
2315 	ahci_rpm_put_port(ap);
2316 	return rc;
2317 }
2318 #endif
2319 
ahci_port_start(struct ata_port * ap)2320 static int ahci_port_start(struct ata_port *ap)
2321 {
2322 	struct ahci_host_priv *hpriv = ap->host->private_data;
2323 	struct device *dev = ap->host->dev;
2324 	struct ahci_port_priv *pp;
2325 	void *mem;
2326 	dma_addr_t mem_dma;
2327 	size_t dma_sz, rx_fis_sz;
2328 
2329 	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2330 	if (!pp)
2331 		return -ENOMEM;
2332 
2333 	if (ap->host->n_ports > 1) {
2334 		pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2335 		if (!pp->irq_desc) {
2336 			devm_kfree(dev, pp);
2337 			return -ENOMEM;
2338 		}
2339 		snprintf(pp->irq_desc, 8,
2340 			 "%s%d", dev_driver_string(dev), ap->port_no);
2341 	}
2342 
2343 	/* check FBS capability */
2344 	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2345 		void __iomem *port_mmio = ahci_port_base(ap);
2346 		u32 cmd = readl(port_mmio + PORT_CMD);
2347 		if (cmd & PORT_CMD_FBSCP)
2348 			pp->fbs_supported = true;
2349 		else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2350 			dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2351 				 ap->port_no);
2352 			pp->fbs_supported = true;
2353 		} else
2354 			dev_warn(dev, "port %d is not capable of FBS\n",
2355 				 ap->port_no);
2356 	}
2357 
2358 	if (pp->fbs_supported) {
2359 		dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2360 		rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2361 	} else {
2362 		dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2363 		rx_fis_sz = AHCI_RX_FIS_SZ;
2364 	}
2365 
2366 	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2367 	if (!mem)
2368 		return -ENOMEM;
2369 	memset(mem, 0, dma_sz);
2370 
2371 	/*
2372 	 * First item in chunk of DMA memory: 32-slot command table,
2373 	 * 32 bytes each in size
2374 	 */
2375 	pp->cmd_slot = mem;
2376 	pp->cmd_slot_dma = mem_dma;
2377 
2378 	mem += AHCI_CMD_SLOT_SZ;
2379 	mem_dma += AHCI_CMD_SLOT_SZ;
2380 
2381 	/*
2382 	 * Second item: Received-FIS area
2383 	 */
2384 	pp->rx_fis = mem;
2385 	pp->rx_fis_dma = mem_dma;
2386 
2387 	mem += rx_fis_sz;
2388 	mem_dma += rx_fis_sz;
2389 
2390 	/*
2391 	 * Third item: data area for storing a single command
2392 	 * and its scatter-gather table
2393 	 */
2394 	pp->cmd_tbl = mem;
2395 	pp->cmd_tbl_dma = mem_dma;
2396 
2397 	/*
2398 	 * Save off initial list of interrupts to be enabled.
2399 	 * This could be changed later
2400 	 */
2401 	pp->intr_mask = DEF_PORT_IRQ;
2402 
2403 	/*
2404 	 * Switch to per-port locking in case each port has its own MSI vector.
2405 	 */
2406 	if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2407 		spin_lock_init(&pp->lock);
2408 		ap->lock = &pp->lock;
2409 	}
2410 
2411 	ap->private_data = pp;
2412 
2413 	/* engage engines, captain */
2414 	return ahci_port_resume(ap);
2415 }
2416 
ahci_port_stop(struct ata_port * ap)2417 static void ahci_port_stop(struct ata_port *ap)
2418 {
2419 	const char *emsg = NULL;
2420 	struct ahci_host_priv *hpriv = ap->host->private_data;
2421 	void __iomem *host_mmio = hpriv->mmio;
2422 	int rc;
2423 
2424 	/* de-initialize port */
2425 	rc = ahci_deinit_port(ap, &emsg);
2426 	if (rc)
2427 		ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2428 
2429 	/*
2430 	 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2431 	 * re-enabling INTx.
2432 	 */
2433 	writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2434 }
2435 
ahci_print_info(struct ata_host * host,const char * scc_s)2436 void ahci_print_info(struct ata_host *host, const char *scc_s)
2437 {
2438 	struct ahci_host_priv *hpriv = host->private_data;
2439 	u32 vers, cap, cap2, impl, speed;
2440 	const char *speed_s;
2441 
2442 	vers = hpriv->version;
2443 	cap = hpriv->cap;
2444 	cap2 = hpriv->cap2;
2445 	impl = hpriv->port_map;
2446 
2447 	speed = (cap >> 20) & 0xf;
2448 	if (speed == 1)
2449 		speed_s = "1.5";
2450 	else if (speed == 2)
2451 		speed_s = "3";
2452 	else if (speed == 3)
2453 		speed_s = "6";
2454 	else
2455 		speed_s = "?";
2456 
2457 	dev_info(host->dev,
2458 		"AHCI %02x%02x.%02x%02x "
2459 		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2460 		,
2461 
2462 		(vers >> 24) & 0xff,
2463 		(vers >> 16) & 0xff,
2464 		(vers >> 8) & 0xff,
2465 		vers & 0xff,
2466 
2467 		((cap >> 8) & 0x1f) + 1,
2468 		(cap & 0x1f) + 1,
2469 		speed_s,
2470 		impl,
2471 		scc_s);
2472 
2473 	dev_info(host->dev,
2474 		"flags: "
2475 		"%s%s%s%s%s%s%s"
2476 		"%s%s%s%s%s%s%s"
2477 		"%s%s%s%s%s%s%s"
2478 		"%s%s\n"
2479 		,
2480 
2481 		cap & HOST_CAP_64 ? "64bit " : "",
2482 		cap & HOST_CAP_NCQ ? "ncq " : "",
2483 		cap & HOST_CAP_SNTF ? "sntf " : "",
2484 		cap & HOST_CAP_MPS ? "ilck " : "",
2485 		cap & HOST_CAP_SSS ? "stag " : "",
2486 		cap & HOST_CAP_ALPM ? "pm " : "",
2487 		cap & HOST_CAP_LED ? "led " : "",
2488 		cap & HOST_CAP_CLO ? "clo " : "",
2489 		cap & HOST_CAP_ONLY ? "only " : "",
2490 		cap & HOST_CAP_PMP ? "pmp " : "",
2491 		cap & HOST_CAP_FBS ? "fbs " : "",
2492 		cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2493 		cap & HOST_CAP_SSC ? "slum " : "",
2494 		cap & HOST_CAP_PART ? "part " : "",
2495 		cap & HOST_CAP_CCC ? "ccc " : "",
2496 		cap & HOST_CAP_EMS ? "ems " : "",
2497 		cap & HOST_CAP_SXS ? "sxs " : "",
2498 		cap2 & HOST_CAP2_DESO ? "deso " : "",
2499 		cap2 & HOST_CAP2_SADM ? "sadm " : "",
2500 		cap2 & HOST_CAP2_SDS ? "sds " : "",
2501 		cap2 & HOST_CAP2_APST ? "apst " : "",
2502 		cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2503 		cap2 & HOST_CAP2_BOH ? "boh " : ""
2504 		);
2505 }
2506 EXPORT_SYMBOL_GPL(ahci_print_info);
2507 
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2508 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2509 			  struct ata_port_info *pi)
2510 {
2511 	u8 messages;
2512 	void __iomem *mmio = hpriv->mmio;
2513 	u32 em_loc = readl(mmio + HOST_EM_LOC);
2514 	u32 em_ctl = readl(mmio + HOST_EM_CTL);
2515 
2516 	if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2517 		return;
2518 
2519 	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2520 
2521 	if (messages) {
2522 		/* store em_loc */
2523 		hpriv->em_loc = ((em_loc >> 16) * 4);
2524 		hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2525 		hpriv->em_msg_type = messages;
2526 		pi->flags |= ATA_FLAG_EM;
2527 		if (!(em_ctl & EM_CTL_ALHD))
2528 			pi->flags |= ATA_FLAG_SW_ACTIVITY;
2529 	}
2530 }
2531 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2532 
ahci_host_activate_multi_irqs(struct ata_host * host,struct scsi_host_template * sht)2533 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2534 					 struct scsi_host_template *sht)
2535 {
2536 	struct ahci_host_priv *hpriv = host->private_data;
2537 	int i, rc;
2538 
2539 	rc = ata_host_start(host);
2540 	if (rc)
2541 		return rc;
2542 	/*
2543 	 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2544 	 * allocated. That is one MSI per port, starting from @irq.
2545 	 */
2546 	for (i = 0; i < host->n_ports; i++) {
2547 		struct ahci_port_priv *pp = host->ports[i]->private_data;
2548 		int irq = hpriv->get_irq_vector(host, i);
2549 
2550 		/* Do not receive interrupts sent by dummy ports */
2551 		if (!pp) {
2552 			disable_irq(irq);
2553 			continue;
2554 		}
2555 
2556 		rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2557 				0, pp->irq_desc, host->ports[i]);
2558 
2559 		if (rc)
2560 			return rc;
2561 		ata_port_desc(host->ports[i], "irq %d", irq);
2562 	}
2563 
2564 	return ata_host_register(host, sht);
2565 }
2566 
2567 /**
2568  *	ahci_host_activate - start AHCI host, request IRQs and register it
2569  *	@host: target ATA host
2570  *	@sht: scsi_host_template to use when registering the host
2571  *
2572  *	LOCKING:
2573  *	Inherited from calling layer (may sleep).
2574  *
2575  *	RETURNS:
2576  *	0 on success, -errno otherwise.
2577  */
ahci_host_activate(struct ata_host * host,struct scsi_host_template * sht)2578 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2579 {
2580 	struct ahci_host_priv *hpriv = host->private_data;
2581 	int irq = hpriv->irq;
2582 	int rc;
2583 
2584 	if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2585 		if (hpriv->irq_handler)
2586 			dev_warn(host->dev,
2587 			         "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2588 		if (!hpriv->get_irq_vector) {
2589 			dev_err(host->dev,
2590 				"AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2591 			return -EIO;
2592 		}
2593 
2594 		rc = ahci_host_activate_multi_irqs(host, sht);
2595 	} else {
2596 		rc = ata_host_activate(host, irq, hpriv->irq_handler,
2597 				       IRQF_SHARED, sht);
2598 	}
2599 
2600 
2601 	return rc;
2602 }
2603 EXPORT_SYMBOL_GPL(ahci_host_activate);
2604 
2605 MODULE_AUTHOR("Jeff Garzik");
2606 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2607 MODULE_LICENSE("GPL");
2608