1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_i2c.h"
31
32 #include "atom.h"
33 #include "atom-bits.h"
34 #include "atombios_encoders.h"
35 #include "bif/bif_4_1_d.h"
36
amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device * adev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
38 ATOM_GPIO_I2C_ASSIGMENT *gpio,
39 u8 index)
40 {
41
42 }
43
amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
45 {
46 struct amdgpu_i2c_bus_rec i2c;
47
48 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
49
50 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
51 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
52 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
53 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
54 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
55 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
56 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
57 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
58 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
59 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
60 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
61 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
62 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
63 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
64 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
65 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
66
67 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
68 i2c.hw_capable = true;
69 else
70 i2c.hw_capable = false;
71
72 if (gpio->sucI2cId.ucAccess == 0xa0)
73 i2c.mm_i2c = true;
74 else
75 i2c.mm_i2c = false;
76
77 i2c.i2c_id = gpio->sucI2cId.ucAccess;
78
79 if (i2c.mask_clk_reg)
80 i2c.valid = true;
81 else
82 i2c.valid = false;
83
84 return i2c;
85 }
86
amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device * adev,uint8_t id)87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
88 uint8_t id)
89 {
90 struct atom_context *ctx = adev->mode_info.atom_context;
91 ATOM_GPIO_I2C_ASSIGMENT *gpio;
92 struct amdgpu_i2c_bus_rec i2c;
93 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
94 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95 uint16_t data_offset, size;
96 int i, num_indices;
97
98 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
99 i2c.valid = false;
100
101 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
102 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
103
104 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
105 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
106
107 gpio = &i2c_info->asGPIO_Info[0];
108 for (i = 0; i < num_indices; i++) {
109
110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
111
112 if (gpio->sucI2cId.ucAccess == id) {
113 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
114 break;
115 }
116 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
117 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
118 }
119 }
120
121 return i2c;
122 }
123
amdgpu_atombios_i2c_init(struct amdgpu_device * adev)124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
125 {
126 struct atom_context *ctx = adev->mode_info.atom_context;
127 ATOM_GPIO_I2C_ASSIGMENT *gpio;
128 struct amdgpu_i2c_bus_rec i2c;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
130 struct _ATOM_GPIO_I2C_INFO *i2c_info;
131 uint16_t data_offset, size;
132 int i, num_indices;
133 char stmp[32];
134
135 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
137
138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
139 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
140
141 gpio = &i2c_info->asGPIO_Info[0];
142 for (i = 0; i < num_indices; i++) {
143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
144
145 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
146
147 if (i2c.valid) {
148 sprintf(stmp, "0x%x", i2c.i2c_id);
149 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
150 }
151 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
152 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
153 }
154 }
155 }
156
157 struct amdgpu_gpio_rec
amdgpu_atombios_lookup_gpio(struct amdgpu_device * adev,u8 id)158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
159 u8 id)
160 {
161 struct atom_context *ctx = adev->mode_info.atom_context;
162 struct amdgpu_gpio_rec gpio;
163 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
164 struct _ATOM_GPIO_PIN_LUT *gpio_info;
165 ATOM_GPIO_PIN_ASSIGNMENT *pin;
166 u16 data_offset, size;
167 int i, num_indices;
168
169 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
170 gpio.valid = false;
171
172 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
173 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
174
175 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
177
178 pin = gpio_info->asGPIO_Pin;
179 for (i = 0; i < num_indices; i++) {
180 if (id == pin->ucGPIO_ID) {
181 gpio.id = pin->ucGPIO_ID;
182 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
183 gpio.shift = pin->ucGpioPinBitShift;
184 gpio.mask = (1 << pin->ucGpioPinBitShift);
185 gpio.valid = true;
186 break;
187 }
188 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
189 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
190 }
191 }
192
193 return gpio;
194 }
195
196 static struct amdgpu_hpd
amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device * adev,struct amdgpu_gpio_rec * gpio)197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
198 struct amdgpu_gpio_rec *gpio)
199 {
200 struct amdgpu_hpd hpd;
201 u32 reg;
202
203 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
204
205 reg = amdgpu_display_hpd_get_gpio_reg(adev);
206
207 hpd.gpio = *gpio;
208 if (gpio->reg == reg) {
209 switch(gpio->mask) {
210 case (1 << 0):
211 hpd.hpd = AMDGPU_HPD_1;
212 break;
213 case (1 << 8):
214 hpd.hpd = AMDGPU_HPD_2;
215 break;
216 case (1 << 16):
217 hpd.hpd = AMDGPU_HPD_3;
218 break;
219 case (1 << 24):
220 hpd.hpd = AMDGPU_HPD_4;
221 break;
222 case (1 << 26):
223 hpd.hpd = AMDGPU_HPD_5;
224 break;
225 case (1 << 28):
226 hpd.hpd = AMDGPU_HPD_6;
227 break;
228 default:
229 hpd.hpd = AMDGPU_HPD_NONE;
230 break;
231 }
232 } else
233 hpd.hpd = AMDGPU_HPD_NONE;
234 return hpd;
235 }
236
237 static const int object_connector_convert[] = {
238 DRM_MODE_CONNECTOR_Unknown,
239 DRM_MODE_CONNECTOR_DVII,
240 DRM_MODE_CONNECTOR_DVII,
241 DRM_MODE_CONNECTOR_DVID,
242 DRM_MODE_CONNECTOR_DVID,
243 DRM_MODE_CONNECTOR_VGA,
244 DRM_MODE_CONNECTOR_Composite,
245 DRM_MODE_CONNECTOR_SVIDEO,
246 DRM_MODE_CONNECTOR_Unknown,
247 DRM_MODE_CONNECTOR_Unknown,
248 DRM_MODE_CONNECTOR_9PinDIN,
249 DRM_MODE_CONNECTOR_Unknown,
250 DRM_MODE_CONNECTOR_HDMIA,
251 DRM_MODE_CONNECTOR_HDMIB,
252 DRM_MODE_CONNECTOR_LVDS,
253 DRM_MODE_CONNECTOR_9PinDIN,
254 DRM_MODE_CONNECTOR_Unknown,
255 DRM_MODE_CONNECTOR_Unknown,
256 DRM_MODE_CONNECTOR_Unknown,
257 DRM_MODE_CONNECTOR_DisplayPort,
258 DRM_MODE_CONNECTOR_eDP,
259 DRM_MODE_CONNECTOR_Unknown
260 };
261
amdgpu_atombios_has_dce_engine_info(struct amdgpu_device * adev)262 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
263 {
264 struct amdgpu_mode_info *mode_info = &adev->mode_info;
265 struct atom_context *ctx = mode_info->atom_context;
266 int index = GetIndexIntoMasterTable(DATA, Object_Header);
267 u16 size, data_offset;
268 u8 frev, crev;
269 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
270 ATOM_OBJECT_HEADER *obj_header;
271
272 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
273 return false;
274
275 if (crev < 2)
276 return false;
277
278 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
279 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
280 (ctx->bios + data_offset +
281 le16_to_cpu(obj_header->usDisplayPathTableOffset));
282
283 if (path_obj->ucNumOfDispPath)
284 return true;
285 else
286 return false;
287 }
288
amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * adev)289 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
290 {
291 struct amdgpu_mode_info *mode_info = &adev->mode_info;
292 struct atom_context *ctx = mode_info->atom_context;
293 int index = GetIndexIntoMasterTable(DATA, Object_Header);
294 u16 size, data_offset;
295 u8 frev, crev;
296 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
297 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
298 ATOM_OBJECT_TABLE *router_obj;
299 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
300 ATOM_OBJECT_HEADER *obj_header;
301 int i, j, k, path_size, device_support;
302 int connector_type;
303 u16 conn_id, connector_object_id;
304 struct amdgpu_i2c_bus_rec ddc_bus;
305 struct amdgpu_router router;
306 struct amdgpu_gpio_rec gpio;
307 struct amdgpu_hpd hpd;
308
309 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
310 return false;
311
312 if (crev < 2)
313 return false;
314
315 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
316 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
317 (ctx->bios + data_offset +
318 le16_to_cpu(obj_header->usDisplayPathTableOffset));
319 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
320 (ctx->bios + data_offset +
321 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
322 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
323 (ctx->bios + data_offset +
324 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
325 router_obj = (ATOM_OBJECT_TABLE *)
326 (ctx->bios + data_offset +
327 le16_to_cpu(obj_header->usRouterObjectTableOffset));
328 device_support = le16_to_cpu(obj_header->usDeviceSupport);
329
330 path_size = 0;
331 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
332 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
333 ATOM_DISPLAY_OBJECT_PATH *path;
334 addr += path_size;
335 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
336 path_size += le16_to_cpu(path->usSize);
337
338 if (device_support & le16_to_cpu(path->usDeviceTag)) {
339 uint8_t con_obj_id =
340 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
341 >> OBJECT_ID_SHIFT;
342
343 /* Skip TV/CV support */
344 if ((le16_to_cpu(path->usDeviceTag) ==
345 ATOM_DEVICE_TV1_SUPPORT) ||
346 (le16_to_cpu(path->usDeviceTag) ==
347 ATOM_DEVICE_CV_SUPPORT))
348 continue;
349
350 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
351 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
352 con_obj_id, le16_to_cpu(path->usDeviceTag));
353 continue;
354 }
355
356 connector_type =
357 object_connector_convert[con_obj_id];
358 connector_object_id = con_obj_id;
359
360 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
361 continue;
362
363 router.ddc_valid = false;
364 router.cd_valid = false;
365 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
366 uint8_t grph_obj_type =
367 (le16_to_cpu(path->usGraphicObjIds[j]) &
368 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
369
370 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
371 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
372 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
373 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
374 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
375 (ctx->bios + data_offset +
376 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
377 ATOM_ENCODER_CAP_RECORD *cap_record;
378 u16 caps = 0;
379
380 while (record->ucRecordSize > 0 &&
381 record->ucRecordType > 0 &&
382 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
383 switch (record->ucRecordType) {
384 case ATOM_ENCODER_CAP_RECORD_TYPE:
385 cap_record =(ATOM_ENCODER_CAP_RECORD *)
386 record;
387 caps = le16_to_cpu(cap_record->usEncoderCap);
388 break;
389 }
390 record = (ATOM_COMMON_RECORD_HEADER *)
391 ((char *)record + record->ucRecordSize);
392 }
393 amdgpu_display_add_encoder(adev, encoder_obj,
394 le16_to_cpu(path->usDeviceTag),
395 caps);
396 }
397 }
398 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
399 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
400 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
401 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
402 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
403 (ctx->bios + data_offset +
404 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
405 ATOM_I2C_RECORD *i2c_record;
406 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
407 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
408 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
409 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
410 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
411 (ctx->bios + data_offset +
412 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
413 u8 *num_dst_objs = (u8 *)
414 ((u8 *)router_src_dst_table + 1 +
415 (router_src_dst_table->ucNumberOfSrc * 2));
416 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
417 int enum_id;
418
419 router.router_id = router_obj_id;
420 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
421 if (le16_to_cpu(path->usConnObjectId) ==
422 le16_to_cpu(dst_objs[enum_id]))
423 break;
424 }
425
426 while (record->ucRecordSize > 0 &&
427 record->ucRecordType > 0 &&
428 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
429 switch (record->ucRecordType) {
430 case ATOM_I2C_RECORD_TYPE:
431 i2c_record =
432 (ATOM_I2C_RECORD *)
433 record;
434 i2c_config =
435 (ATOM_I2C_ID_CONFIG_ACCESS *)
436 &i2c_record->sucI2cId;
437 router.i2c_info =
438 amdgpu_atombios_lookup_i2c_gpio(adev,
439 i2c_config->
440 ucAccess);
441 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
442 break;
443 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
444 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
445 record;
446 router.ddc_valid = true;
447 router.ddc_mux_type = ddc_path->ucMuxType;
448 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
449 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
450 break;
451 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
452 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
453 record;
454 router.cd_valid = true;
455 router.cd_mux_type = cd_path->ucMuxType;
456 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
457 router.cd_mux_state = cd_path->ucMuxState[enum_id];
458 break;
459 }
460 record = (ATOM_COMMON_RECORD_HEADER *)
461 ((char *)record + record->ucRecordSize);
462 }
463 }
464 }
465 }
466 }
467
468 /* look up gpio for ddc, hpd */
469 ddc_bus.valid = false;
470 hpd.hpd = AMDGPU_HPD_NONE;
471 if ((le16_to_cpu(path->usDeviceTag) &
472 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
473 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
474 if (le16_to_cpu(path->usConnObjectId) ==
475 le16_to_cpu(con_obj->asObjects[j].
476 usObjectID)) {
477 ATOM_COMMON_RECORD_HEADER
478 *record =
479 (ATOM_COMMON_RECORD_HEADER
480 *)
481 (ctx->bios + data_offset +
482 le16_to_cpu(con_obj->
483 asObjects[j].
484 usRecordOffset));
485 ATOM_I2C_RECORD *i2c_record;
486 ATOM_HPD_INT_RECORD *hpd_record;
487 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
488
489 while (record->ucRecordSize > 0 &&
490 record->ucRecordType > 0 &&
491 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
492 switch (record->ucRecordType) {
493 case ATOM_I2C_RECORD_TYPE:
494 i2c_record =
495 (ATOM_I2C_RECORD *)
496 record;
497 i2c_config =
498 (ATOM_I2C_ID_CONFIG_ACCESS *)
499 &i2c_record->sucI2cId;
500 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
501 i2c_config->
502 ucAccess);
503 break;
504 case ATOM_HPD_INT_RECORD_TYPE:
505 hpd_record =
506 (ATOM_HPD_INT_RECORD *)
507 record;
508 gpio = amdgpu_atombios_lookup_gpio(adev,
509 hpd_record->ucHPDIntGPIOID);
510 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
511 hpd.plugged_state = hpd_record->ucPlugged_PinState;
512 break;
513 }
514 record =
515 (ATOM_COMMON_RECORD_HEADER
516 *) ((char *)record
517 +
518 record->
519 ucRecordSize);
520 }
521 break;
522 }
523 }
524 }
525
526 /* needed for aux chan transactions */
527 ddc_bus.hpd = hpd.hpd;
528
529 conn_id = le16_to_cpu(path->usConnObjectId);
530
531 amdgpu_display_add_connector(adev,
532 conn_id,
533 le16_to_cpu(path->usDeviceTag),
534 connector_type, &ddc_bus,
535 connector_object_id,
536 &hpd,
537 &router);
538
539 }
540 }
541
542 amdgpu_link_encoder_connector(adev->ddev);
543
544 return true;
545 }
546
547 union firmware_info {
548 ATOM_FIRMWARE_INFO info;
549 ATOM_FIRMWARE_INFO_V1_2 info_12;
550 ATOM_FIRMWARE_INFO_V1_3 info_13;
551 ATOM_FIRMWARE_INFO_V1_4 info_14;
552 ATOM_FIRMWARE_INFO_V2_1 info_21;
553 ATOM_FIRMWARE_INFO_V2_2 info_22;
554 };
555
amdgpu_atombios_get_clock_info(struct amdgpu_device * adev)556 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
557 {
558 struct amdgpu_mode_info *mode_info = &adev->mode_info;
559 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
560 uint8_t frev, crev;
561 uint16_t data_offset;
562 int ret = -EINVAL;
563
564 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
565 &frev, &crev, &data_offset)) {
566 int i;
567 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
568 struct amdgpu_pll *spll = &adev->clock.spll;
569 struct amdgpu_pll *mpll = &adev->clock.mpll;
570 union firmware_info *firmware_info =
571 (union firmware_info *)(mode_info->atom_context->bios +
572 data_offset);
573 /* pixel clocks */
574 ppll->reference_freq =
575 le16_to_cpu(firmware_info->info.usReferenceClock);
576 ppll->reference_div = 0;
577
578 ppll->pll_out_min =
579 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
580 ppll->pll_out_max =
581 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
582
583 ppll->lcd_pll_out_min =
584 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
585 if (ppll->lcd_pll_out_min == 0)
586 ppll->lcd_pll_out_min = ppll->pll_out_min;
587 ppll->lcd_pll_out_max =
588 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
589 if (ppll->lcd_pll_out_max == 0)
590 ppll->lcd_pll_out_max = ppll->pll_out_max;
591
592 if (ppll->pll_out_min == 0)
593 ppll->pll_out_min = 64800;
594
595 ppll->pll_in_min =
596 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
597 ppll->pll_in_max =
598 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
599
600 ppll->min_post_div = 2;
601 ppll->max_post_div = 0x7f;
602 ppll->min_frac_feedback_div = 0;
603 ppll->max_frac_feedback_div = 9;
604 ppll->min_ref_div = 2;
605 ppll->max_ref_div = 0x3ff;
606 ppll->min_feedback_div = 4;
607 ppll->max_feedback_div = 0xfff;
608 ppll->best_vco = 0;
609
610 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
611 adev->clock.ppll[i] = *ppll;
612
613 /* system clock */
614 spll->reference_freq =
615 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
616 spll->reference_div = 0;
617
618 spll->pll_out_min =
619 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
620 spll->pll_out_max =
621 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
622
623 /* ??? */
624 if (spll->pll_out_min == 0)
625 spll->pll_out_min = 64800;
626
627 spll->pll_in_min =
628 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
629 spll->pll_in_max =
630 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
631
632 spll->min_post_div = 1;
633 spll->max_post_div = 1;
634 spll->min_ref_div = 2;
635 spll->max_ref_div = 0xff;
636 spll->min_feedback_div = 4;
637 spll->max_feedback_div = 0xff;
638 spll->best_vco = 0;
639
640 /* memory clock */
641 mpll->reference_freq =
642 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
643 mpll->reference_div = 0;
644
645 mpll->pll_out_min =
646 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
647 mpll->pll_out_max =
648 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
649
650 /* ??? */
651 if (mpll->pll_out_min == 0)
652 mpll->pll_out_min = 64800;
653
654 mpll->pll_in_min =
655 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
656 mpll->pll_in_max =
657 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
658
659 adev->clock.default_sclk =
660 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
661 adev->clock.default_mclk =
662 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
663
664 mpll->min_post_div = 1;
665 mpll->max_post_div = 1;
666 mpll->min_ref_div = 2;
667 mpll->max_ref_div = 0xff;
668 mpll->min_feedback_div = 4;
669 mpll->max_feedback_div = 0xff;
670 mpll->best_vco = 0;
671
672 /* disp clock */
673 adev->clock.default_dispclk =
674 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
675 /* set a reasonable default for DP */
676 if (adev->clock.default_dispclk < 53900) {
677 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
678 adev->clock.default_dispclk / 100);
679 adev->clock.default_dispclk = 60000;
680 } else if (adev->clock.default_dispclk <= 60000) {
681 DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",
682 adev->clock.default_dispclk / 100);
683 adev->clock.default_dispclk = 62500;
684 }
685 adev->clock.dp_extclk =
686 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
687 adev->clock.current_dispclk = adev->clock.default_dispclk;
688
689 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
690 if (adev->clock.max_pixel_clock == 0)
691 adev->clock.max_pixel_clock = 40000;
692
693 /* not technically a clock, but... */
694 adev->mode_info.firmware_flags =
695 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
696
697 ret = 0;
698 }
699
700 adev->pm.current_sclk = adev->clock.default_sclk;
701 adev->pm.current_mclk = adev->clock.default_mclk;
702
703 return ret;
704 }
705
706 union gfx_info {
707 ATOM_GFX_INFO_V2_1 info;
708 };
709
amdgpu_atombios_get_gfx_info(struct amdgpu_device * adev)710 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
711 {
712 struct amdgpu_mode_info *mode_info = &adev->mode_info;
713 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
714 uint8_t frev, crev;
715 uint16_t data_offset;
716 int ret = -EINVAL;
717
718 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
719 &frev, &crev, &data_offset)) {
720 union gfx_info *gfx_info = (union gfx_info *)
721 (mode_info->atom_context->bios + data_offset);
722
723 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
724 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
725 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
726 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
727 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
728 adev->gfx.config.max_texture_channel_caches =
729 gfx_info->info.max_texture_channel_caches;
730
731 ret = 0;
732 }
733 return ret;
734 }
735
736 union igp_info {
737 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
738 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
739 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
740 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
741 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
742 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
743 };
744
745 /*
746 * Return vram width from integrated system info table, if available,
747 * or 0 if not.
748 */
amdgpu_atombios_get_vram_width(struct amdgpu_device * adev)749 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
750 {
751 struct amdgpu_mode_info *mode_info = &adev->mode_info;
752 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
753 u16 data_offset, size;
754 union igp_info *igp_info;
755 u8 frev, crev;
756
757 /* get any igp specific overrides */
758 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
759 &frev, &crev, &data_offset)) {
760 igp_info = (union igp_info *)
761 (mode_info->atom_context->bios + data_offset);
762 switch (crev) {
763 case 8:
764 case 9:
765 return igp_info->info_8.ucUMAChannelNumber * 64;
766 default:
767 return 0;
768 }
769 }
770
771 return 0;
772 }
773
amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device * adev,struct amdgpu_atom_ss * ss,int id)774 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
775 struct amdgpu_atom_ss *ss,
776 int id)
777 {
778 struct amdgpu_mode_info *mode_info = &adev->mode_info;
779 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
780 u16 data_offset, size;
781 union igp_info *igp_info;
782 u8 frev, crev;
783 u16 percentage = 0, rate = 0;
784
785 /* get any igp specific overrides */
786 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
787 &frev, &crev, &data_offset)) {
788 igp_info = (union igp_info *)
789 (mode_info->atom_context->bios + data_offset);
790 switch (crev) {
791 case 6:
792 switch (id) {
793 case ASIC_INTERNAL_SS_ON_TMDS:
794 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
795 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
796 break;
797 case ASIC_INTERNAL_SS_ON_HDMI:
798 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
799 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
800 break;
801 case ASIC_INTERNAL_SS_ON_LVDS:
802 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
803 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
804 break;
805 }
806 break;
807 case 7:
808 switch (id) {
809 case ASIC_INTERNAL_SS_ON_TMDS:
810 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
811 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
812 break;
813 case ASIC_INTERNAL_SS_ON_HDMI:
814 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
815 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
816 break;
817 case ASIC_INTERNAL_SS_ON_LVDS:
818 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
819 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
820 break;
821 }
822 break;
823 case 8:
824 switch (id) {
825 case ASIC_INTERNAL_SS_ON_TMDS:
826 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
827 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
828 break;
829 case ASIC_INTERNAL_SS_ON_HDMI:
830 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
831 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
832 break;
833 case ASIC_INTERNAL_SS_ON_LVDS:
834 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
835 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
836 break;
837 }
838 break;
839 case 9:
840 switch (id) {
841 case ASIC_INTERNAL_SS_ON_TMDS:
842 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
843 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
844 break;
845 case ASIC_INTERNAL_SS_ON_HDMI:
846 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
847 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
848 break;
849 case ASIC_INTERNAL_SS_ON_LVDS:
850 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
851 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
852 break;
853 }
854 break;
855 default:
856 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
857 break;
858 }
859 if (percentage)
860 ss->percentage = percentage;
861 if (rate)
862 ss->rate = rate;
863 }
864 }
865
866 union asic_ss_info {
867 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
868 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
869 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
870 };
871
872 union asic_ss_assignment {
873 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
874 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
875 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
876 };
877
amdgpu_atombios_get_asic_ss_info(struct amdgpu_device * adev,struct amdgpu_atom_ss * ss,int id,u32 clock)878 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
879 struct amdgpu_atom_ss *ss,
880 int id, u32 clock)
881 {
882 struct amdgpu_mode_info *mode_info = &adev->mode_info;
883 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
884 uint16_t data_offset, size;
885 union asic_ss_info *ss_info;
886 union asic_ss_assignment *ss_assign;
887 uint8_t frev, crev;
888 int i, num_indices;
889
890 if (id == ASIC_INTERNAL_MEMORY_SS) {
891 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
892 return false;
893 }
894 if (id == ASIC_INTERNAL_ENGINE_SS) {
895 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
896 return false;
897 }
898
899 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
900 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
901 &frev, &crev, &data_offset)) {
902
903 ss_info =
904 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
905
906 switch (frev) {
907 case 1:
908 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
909 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
910
911 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
912 for (i = 0; i < num_indices; i++) {
913 if ((ss_assign->v1.ucClockIndication == id) &&
914 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
915 ss->percentage =
916 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
917 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
918 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
919 ss->percentage_divider = 100;
920 return true;
921 }
922 ss_assign = (union asic_ss_assignment *)
923 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
924 }
925 break;
926 case 2:
927 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
928 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
929 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
930 for (i = 0; i < num_indices; i++) {
931 if ((ss_assign->v2.ucClockIndication == id) &&
932 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
933 ss->percentage =
934 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
935 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
936 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
937 ss->percentage_divider = 100;
938 if ((crev == 2) &&
939 ((id == ASIC_INTERNAL_ENGINE_SS) ||
940 (id == ASIC_INTERNAL_MEMORY_SS)))
941 ss->rate /= 100;
942 return true;
943 }
944 ss_assign = (union asic_ss_assignment *)
945 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
946 }
947 break;
948 case 3:
949 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
950 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
951 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
952 for (i = 0; i < num_indices; i++) {
953 if ((ss_assign->v3.ucClockIndication == id) &&
954 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
955 ss->percentage =
956 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
957 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
958 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
959 if (ss_assign->v3.ucSpreadSpectrumMode &
960 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
961 ss->percentage_divider = 1000;
962 else
963 ss->percentage_divider = 100;
964 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
965 (id == ASIC_INTERNAL_MEMORY_SS))
966 ss->rate /= 100;
967 if (adev->flags & AMD_IS_APU)
968 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
969 return true;
970 }
971 ss_assign = (union asic_ss_assignment *)
972 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
973 }
974 break;
975 default:
976 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
977 break;
978 }
979
980 }
981 return false;
982 }
983
984 union get_clock_dividers {
985 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
986 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
987 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
988 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
989 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
990 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
991 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
992 };
993
amdgpu_atombios_get_clock_dividers(struct amdgpu_device * adev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)994 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
995 u8 clock_type,
996 u32 clock,
997 bool strobe_mode,
998 struct atom_clock_dividers *dividers)
999 {
1000 union get_clock_dividers args;
1001 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1002 u8 frev, crev;
1003
1004 memset(&args, 0, sizeof(args));
1005 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1006
1007 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1008 return -EINVAL;
1009
1010 switch (crev) {
1011 case 2:
1012 case 3:
1013 case 5:
1014 /* r6xx, r7xx, evergreen, ni, si.
1015 * TODO: add support for asic_type <= CHIP_RV770*/
1016 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1017 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1018
1019 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1020
1021 dividers->post_div = args.v3.ucPostDiv;
1022 dividers->enable_post_div = (args.v3.ucCntlFlag &
1023 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1024 dividers->enable_dithen = (args.v3.ucCntlFlag &
1025 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1026 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1027 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1028 dividers->ref_div = args.v3.ucRefDiv;
1029 dividers->vco_mode = (args.v3.ucCntlFlag &
1030 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1031 } else {
1032 /* for SI we use ComputeMemoryClockParam for memory plls */
1033 if (adev->asic_type >= CHIP_TAHITI)
1034 return -EINVAL;
1035 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1036 if (strobe_mode)
1037 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1038
1039 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1040
1041 dividers->post_div = args.v5.ucPostDiv;
1042 dividers->enable_post_div = (args.v5.ucCntlFlag &
1043 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1044 dividers->enable_dithen = (args.v5.ucCntlFlag &
1045 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1046 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1047 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1048 dividers->ref_div = args.v5.ucRefDiv;
1049 dividers->vco_mode = (args.v5.ucCntlFlag &
1050 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1051 }
1052 break;
1053 case 4:
1054 /* fusion */
1055 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
1056
1057 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1058
1059 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1060 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1061 break;
1062 case 6:
1063 /* CI */
1064 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1065 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1066 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
1067
1068 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1069
1070 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1071 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1072 dividers->ref_div = args.v6_out.ucPllRefDiv;
1073 dividers->post_div = args.v6_out.ucPllPostDiv;
1074 dividers->flags = args.v6_out.ucPllCntlFlag;
1075 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1076 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1077 break;
1078 default:
1079 return -EINVAL;
1080 }
1081 return 0;
1082 }
1083
amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device * adev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)1084 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1085 u32 clock,
1086 bool strobe_mode,
1087 struct atom_mpll_param *mpll_param)
1088 {
1089 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1090 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1091 u8 frev, crev;
1092
1093 memset(&args, 0, sizeof(args));
1094 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1095
1096 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1097 return -EINVAL;
1098
1099 switch (frev) {
1100 case 2:
1101 switch (crev) {
1102 case 1:
1103 /* SI */
1104 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1105 args.ucInputFlag = 0;
1106 if (strobe_mode)
1107 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1108
1109 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1110
1111 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1112 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1113 mpll_param->post_div = args.ucPostDiv;
1114 mpll_param->dll_speed = args.ucDllSpeed;
1115 mpll_param->bwcntl = args.ucBWCntl;
1116 mpll_param->vco_mode =
1117 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1118 mpll_param->yclk_sel =
1119 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1120 mpll_param->qdr =
1121 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1122 mpll_param->half_rate =
1123 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128 break;
1129 default:
1130 return -EINVAL;
1131 }
1132 return 0;
1133 }
1134
amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device * adev,u32 eng_clock,u32 mem_clock)1135 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1136 u32 eng_clock, u32 mem_clock)
1137 {
1138 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1139 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1140 u32 tmp;
1141
1142 memset(&args, 0, sizeof(args));
1143
1144 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1145 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1146
1147 args.ulTargetEngineClock = cpu_to_le32(tmp);
1148 if (mem_clock)
1149 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1150
1151 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1152 }
1153
amdgpu_atombios_get_default_voltages(struct amdgpu_device * adev,u16 * vddc,u16 * vddci,u16 * mvdd)1154 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1155 u16 *vddc, u16 *vddci, u16 *mvdd)
1156 {
1157 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1158 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1159 u8 frev, crev;
1160 u16 data_offset;
1161 union firmware_info *firmware_info;
1162
1163 *vddc = 0;
1164 *vddci = 0;
1165 *mvdd = 0;
1166
1167 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1168 &frev, &crev, &data_offset)) {
1169 firmware_info =
1170 (union firmware_info *)(mode_info->atom_context->bios +
1171 data_offset);
1172 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1173 if ((frev == 2) && (crev >= 2)) {
1174 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1175 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1176 }
1177 }
1178 }
1179
1180 union set_voltage {
1181 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1182 struct _SET_VOLTAGE_PARAMETERS v1;
1183 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1184 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1185 };
1186
amdgpu_atombios_get_max_vddc(struct amdgpu_device * adev,u8 voltage_type,u16 voltage_id,u16 * voltage)1187 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1188 u16 voltage_id, u16 *voltage)
1189 {
1190 union set_voltage args;
1191 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1192 u8 frev, crev;
1193
1194 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1195 return -EINVAL;
1196
1197 switch (crev) {
1198 case 1:
1199 return -EINVAL;
1200 case 2:
1201 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1202 args.v2.ucVoltageMode = 0;
1203 args.v2.usVoltageLevel = 0;
1204
1205 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1206
1207 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1208 break;
1209 case 3:
1210 args.v3.ucVoltageType = voltage_type;
1211 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1212 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1213
1214 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1215
1216 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1217 break;
1218 default:
1219 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1220 return -EINVAL;
1221 }
1222
1223 return 0;
1224 }
1225
amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device * adev,u16 * voltage,u16 leakage_idx)1226 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1227 u16 *voltage,
1228 u16 leakage_idx)
1229 {
1230 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1231 }
1232
amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device * adev,u16 * leakage_id)1233 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1234 u16 *leakage_id)
1235 {
1236 union set_voltage args;
1237 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1238 u8 frev, crev;
1239
1240 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1241 return -EINVAL;
1242
1243 switch (crev) {
1244 case 3:
1245 case 4:
1246 args.v3.ucVoltageType = 0;
1247 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1248 args.v3.usVoltageLevel = 0;
1249
1250 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1251
1252 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1253 break;
1254 default:
1255 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1256 return -EINVAL;
1257 }
1258
1259 return 0;
1260 }
1261
amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device * adev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)1262 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1263 u16 *vddc, u16 *vddci,
1264 u16 virtual_voltage_id,
1265 u16 vbios_voltage_id)
1266 {
1267 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1268 u8 frev, crev;
1269 u16 data_offset, size;
1270 int i, j;
1271 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1272 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1273
1274 *vddc = 0;
1275 *vddci = 0;
1276
1277 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1278 &frev, &crev, &data_offset))
1279 return -EINVAL;
1280
1281 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1282 (adev->mode_info.atom_context->bios + data_offset);
1283
1284 switch (frev) {
1285 case 1:
1286 return -EINVAL;
1287 case 2:
1288 switch (crev) {
1289 case 1:
1290 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1291 return -EINVAL;
1292 leakage_bin = (u16 *)
1293 (adev->mode_info.atom_context->bios + data_offset +
1294 le16_to_cpu(profile->usLeakageBinArrayOffset));
1295 vddc_id_buf = (u16 *)
1296 (adev->mode_info.atom_context->bios + data_offset +
1297 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1298 vddc_buf = (u16 *)
1299 (adev->mode_info.atom_context->bios + data_offset +
1300 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1301 vddci_id_buf = (u16 *)
1302 (adev->mode_info.atom_context->bios + data_offset +
1303 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1304 vddci_buf = (u16 *)
1305 (adev->mode_info.atom_context->bios + data_offset +
1306 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1307
1308 if (profile->ucElbVDDC_Num > 0) {
1309 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1310 if (vddc_id_buf[i] == virtual_voltage_id) {
1311 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1312 if (vbios_voltage_id <= leakage_bin[j]) {
1313 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1314 break;
1315 }
1316 }
1317 break;
1318 }
1319 }
1320 }
1321 if (profile->ucElbVDDCI_Num > 0) {
1322 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1323 if (vddci_id_buf[i] == virtual_voltage_id) {
1324 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1325 if (vbios_voltage_id <= leakage_bin[j]) {
1326 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1327 break;
1328 }
1329 }
1330 break;
1331 }
1332 }
1333 }
1334 break;
1335 default:
1336 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1337 return -EINVAL;
1338 }
1339 break;
1340 default:
1341 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1342 return -EINVAL;
1343 }
1344
1345 return 0;
1346 }
1347
1348 union get_voltage_info {
1349 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1350 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1351 };
1352
amdgpu_atombios_get_voltage_evv(struct amdgpu_device * adev,u16 virtual_voltage_id,u16 * voltage)1353 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1354 u16 virtual_voltage_id,
1355 u16 *voltage)
1356 {
1357 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1358 u32 entry_id;
1359 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1360 union get_voltage_info args;
1361
1362 for (entry_id = 0; entry_id < count; entry_id++) {
1363 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1364 virtual_voltage_id)
1365 break;
1366 }
1367
1368 if (entry_id >= count)
1369 return -EINVAL;
1370
1371 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1372 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1373 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1374 args.in.ulSCLKFreq =
1375 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1376
1377 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1378
1379 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1380
1381 return 0;
1382 }
1383
1384 union voltage_object_info {
1385 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1386 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1387 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1388 };
1389
1390 union voltage_object {
1391 struct _ATOM_VOLTAGE_OBJECT v1;
1392 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1393 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1394 };
1395
1396
amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)1397 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1398 u8 voltage_type, u8 voltage_mode)
1399 {
1400 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1401 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1402 u8 *start = (u8*)v3;
1403
1404 while (offset < size) {
1405 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1406 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1407 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1408 return vo;
1409 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1410 }
1411 return NULL;
1412 }
1413
amdgpu_atombios_get_svi2_info(struct amdgpu_device * adev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)1414 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1415 u8 voltage_type,
1416 u8 *svd_gpio_id, u8 *svc_gpio_id)
1417 {
1418 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1419 u8 frev, crev;
1420 u16 data_offset, size;
1421 union voltage_object_info *voltage_info;
1422 union voltage_object *voltage_object = NULL;
1423
1424 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1425 &frev, &crev, &data_offset)) {
1426 voltage_info = (union voltage_object_info *)
1427 (adev->mode_info.atom_context->bios + data_offset);
1428
1429 switch (frev) {
1430 case 3:
1431 switch (crev) {
1432 case 1:
1433 voltage_object = (union voltage_object *)
1434 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1435 voltage_type,
1436 VOLTAGE_OBJ_SVID2);
1437 if (voltage_object) {
1438 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1439 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1440 } else {
1441 return -EINVAL;
1442 }
1443 break;
1444 default:
1445 DRM_ERROR("unknown voltage object table\n");
1446 return -EINVAL;
1447 }
1448 break;
1449 default:
1450 DRM_ERROR("unknown voltage object table\n");
1451 return -EINVAL;
1452 }
1453
1454 }
1455 return 0;
1456 }
1457
1458 bool
amdgpu_atombios_is_voltage_gpio(struct amdgpu_device * adev,u8 voltage_type,u8 voltage_mode)1459 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1460 u8 voltage_type, u8 voltage_mode)
1461 {
1462 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1463 u8 frev, crev;
1464 u16 data_offset, size;
1465 union voltage_object_info *voltage_info;
1466
1467 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1468 &frev, &crev, &data_offset)) {
1469 voltage_info = (union voltage_object_info *)
1470 (adev->mode_info.atom_context->bios + data_offset);
1471
1472 switch (frev) {
1473 case 3:
1474 switch (crev) {
1475 case 1:
1476 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1477 voltage_type, voltage_mode))
1478 return true;
1479 break;
1480 default:
1481 DRM_ERROR("unknown voltage object table\n");
1482 return false;
1483 }
1484 break;
1485 default:
1486 DRM_ERROR("unknown voltage object table\n");
1487 return false;
1488 }
1489
1490 }
1491 return false;
1492 }
1493
amdgpu_atombios_get_voltage_table(struct amdgpu_device * adev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)1494 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1495 u8 voltage_type, u8 voltage_mode,
1496 struct atom_voltage_table *voltage_table)
1497 {
1498 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1499 u8 frev, crev;
1500 u16 data_offset, size;
1501 int i;
1502 union voltage_object_info *voltage_info;
1503 union voltage_object *voltage_object = NULL;
1504
1505 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1506 &frev, &crev, &data_offset)) {
1507 voltage_info = (union voltage_object_info *)
1508 (adev->mode_info.atom_context->bios + data_offset);
1509
1510 switch (frev) {
1511 case 3:
1512 switch (crev) {
1513 case 1:
1514 voltage_object = (union voltage_object *)
1515 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1516 voltage_type, voltage_mode);
1517 if (voltage_object) {
1518 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1519 &voltage_object->v3.asGpioVoltageObj;
1520 VOLTAGE_LUT_ENTRY_V2 *lut;
1521 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1522 return -EINVAL;
1523 lut = &gpio->asVolGpioLut[0];
1524 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1525 voltage_table->entries[i].value =
1526 le16_to_cpu(lut->usVoltageValue);
1527 voltage_table->entries[i].smio_low =
1528 le32_to_cpu(lut->ulVoltageId);
1529 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1530 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1531 }
1532 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1533 voltage_table->count = gpio->ucGpioEntryNum;
1534 voltage_table->phase_delay = gpio->ucPhaseDelay;
1535 return 0;
1536 }
1537 break;
1538 default:
1539 DRM_ERROR("unknown voltage object table\n");
1540 return -EINVAL;
1541 }
1542 break;
1543 default:
1544 DRM_ERROR("unknown voltage object table\n");
1545 return -EINVAL;
1546 }
1547 }
1548 return -EINVAL;
1549 }
1550
1551 union vram_info {
1552 struct _ATOM_VRAM_INFO_V3 v1_3;
1553 struct _ATOM_VRAM_INFO_V4 v1_4;
1554 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1555 };
1556
1557 #define MEM_ID_MASK 0xff000000
1558 #define MEM_ID_SHIFT 24
1559 #define CLOCK_RANGE_MASK 0x00ffffff
1560 #define CLOCK_RANGE_SHIFT 0
1561 #define LOW_NIBBLE_MASK 0xf
1562 #define DATA_EQU_PREV 0
1563 #define DATA_FROM_TABLE 4
1564
amdgpu_atombios_init_mc_reg_table(struct amdgpu_device * adev,u8 module_index,struct atom_mc_reg_table * reg_table)1565 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1566 u8 module_index,
1567 struct atom_mc_reg_table *reg_table)
1568 {
1569 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1570 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1571 u32 i = 0, j;
1572 u16 data_offset, size;
1573 union vram_info *vram_info;
1574
1575 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1576
1577 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1578 &frev, &crev, &data_offset)) {
1579 vram_info = (union vram_info *)
1580 (adev->mode_info.atom_context->bios + data_offset);
1581 switch (frev) {
1582 case 1:
1583 DRM_ERROR("old table version %d, %d\n", frev, crev);
1584 return -EINVAL;
1585 case 2:
1586 switch (crev) {
1587 case 1:
1588 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1589 ATOM_INIT_REG_BLOCK *reg_block =
1590 (ATOM_INIT_REG_BLOCK *)
1591 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1592 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1593 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1594 ((u8 *)reg_block + (2 * sizeof(u16)) +
1595 le16_to_cpu(reg_block->usRegIndexTblSize));
1596 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
1597 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1598 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1599 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1600 return -EINVAL;
1601 while (i < num_entries) {
1602 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1603 break;
1604 reg_table->mc_reg_address[i].s1 =
1605 (u16)(le16_to_cpu(format->usRegIndex));
1606 reg_table->mc_reg_address[i].pre_reg_data =
1607 (u8)(format->ucPreRegDataLength);
1608 i++;
1609 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1610 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1611 }
1612 reg_table->last = i;
1613 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1614 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1615 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1616 >> MEM_ID_SHIFT);
1617 if (module_index == t_mem_id) {
1618 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1619 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1620 >> CLOCK_RANGE_SHIFT);
1621 for (i = 0, j = 1; i < reg_table->last; i++) {
1622 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1623 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1624 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1625 j++;
1626 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1627 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1628 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1629 }
1630 }
1631 num_ranges++;
1632 }
1633 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1634 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1635 }
1636 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1637 return -EINVAL;
1638 reg_table->num_entries = num_ranges;
1639 } else
1640 return -EINVAL;
1641 break;
1642 default:
1643 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1644 return -EINVAL;
1645 }
1646 break;
1647 default:
1648 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1649 return -EINVAL;
1650 }
1651 return 0;
1652 }
1653 return -EINVAL;
1654 }
1655
amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device * adev)1656 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1657 {
1658 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1659 u8 frev, crev;
1660 u16 data_offset, size;
1661
1662 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1663 &frev, &crev, &data_offset))
1664 return true;
1665
1666 return false;
1667 }
1668
amdgpu_atombios_scratch_regs_lock(struct amdgpu_device * adev,bool lock)1669 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1670 {
1671 uint32_t bios_6_scratch;
1672
1673 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1674
1675 if (lock) {
1676 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1677 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1678 } else {
1679 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1680 bios_6_scratch |= ATOM_S6_ACC_MODE;
1681 }
1682
1683 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1684 }
1685
amdgpu_atombios_scratch_regs_init(struct amdgpu_device * adev)1686 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1687 {
1688 uint32_t bios_2_scratch, bios_6_scratch;
1689
1690 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1691
1692 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1693 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1694
1695 /* let the bios control the backlight */
1696 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1697
1698 /* tell the bios not to handle mode switching */
1699 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1700
1701 /* clear the vbios dpms state */
1702 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1703
1704 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1705 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1706 }
1707
amdgpu_atombios_scratch_regs_save(struct amdgpu_device * adev)1708 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1709 {
1710 int i;
1711
1712 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1713 adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + i);
1714 }
1715
amdgpu_atombios_scratch_regs_restore(struct amdgpu_device * adev)1716 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1717 {
1718 int i;
1719
1720 /*
1721 * VBIOS will check ASIC_INIT_COMPLETE bit to decide if
1722 * execute ASIC_Init posting via driver
1723 */
1724 adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;
1725
1726 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1727 WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]);
1728 }
1729
amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device * adev,bool hung)1730 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1731 bool hung)
1732 {
1733 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1734
1735 if (hung)
1736 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1737 else
1738 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1739
1740 WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1741 }
1742
amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device * adev)1743 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1744 {
1745 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1746
1747 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1748 return false;
1749 else
1750 return true;
1751 }
1752
1753 /* Atom needs data in little endian format so swap as appropriate when copying
1754 * data to or from atom. Note that atom operates on dw units.
1755 *
1756 * Use to_le=true when sending data to atom and provide at least
1757 * ALIGN(num_bytes,4) bytes in the dst buffer.
1758 *
1759 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1760 * byes in the src buffer.
1761 */
amdgpu_atombios_copy_swap(u8 * dst,u8 * src,u8 num_bytes,bool to_le)1762 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1763 {
1764 #ifdef __BIG_ENDIAN
1765 u32 src_tmp[5], dst_tmp[5];
1766 int i;
1767 u8 align_num_bytes = ALIGN(num_bytes, 4);
1768
1769 if (to_le) {
1770 memcpy(src_tmp, src, num_bytes);
1771 for (i = 0; i < align_num_bytes / 4; i++)
1772 dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1773 memcpy(dst, dst_tmp, align_num_bytes);
1774 } else {
1775 memcpy(src_tmp, src, align_num_bytes);
1776 for (i = 0; i < align_num_bytes / 4; i++)
1777 dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1778 memcpy(dst, dst_tmp, num_bytes);
1779 }
1780 #else
1781 memcpy(dst, src, num_bytes);
1782 #endif
1783 }
1784
amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device * adev)1785 int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1786 {
1787 struct atom_context *ctx = adev->mode_info.atom_context;
1788 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1789 uint16_t data_offset;
1790 int usage_bytes = 0;
1791 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1792
1793 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1794 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1795
1796 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1797 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1798 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1799
1800 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1801 }
1802 ctx->scratch_size_bytes = 0;
1803 if (usage_bytes == 0)
1804 usage_bytes = 20 * 1024;
1805 /* allocate some scratch memory */
1806 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1807 if (!ctx->scratch)
1808 return -ENOMEM;
1809 ctx->scratch_size_bytes = usage_bytes;
1810 return 0;
1811 }
1812