1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <drm/drmP.h>
30 #include <drm/drm.h>
31
32 #include "amdgpu.h"
33 #include "amdgpu_pm.h"
34 #include "amdgpu_vcn.h"
35 #include "soc15d.h"
36 #include "soc15_common.h"
37
38 #include "vega10/soc15ip.h"
39 #include "raven1/VCN/vcn_1_0_offset.h"
40
41 /* 1 second timeout */
42 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
43
44 /* Firmware Names */
45 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
46
47 MODULE_FIRMWARE(FIRMWARE_RAVEN);
48
49 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
50
amdgpu_vcn_sw_init(struct amdgpu_device * adev)51 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
52 {
53 struct amdgpu_ring *ring;
54 struct amd_sched_rq *rq;
55 unsigned long bo_size;
56 const char *fw_name;
57 const struct common_firmware_header *hdr;
58 unsigned version_major, version_minor, family_id;
59 int r;
60
61 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
62
63 switch (adev->asic_type) {
64 case CHIP_RAVEN:
65 fw_name = FIRMWARE_RAVEN;
66 break;
67 default:
68 return -EINVAL;
69 }
70
71 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
72 if (r) {
73 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
74 fw_name);
75 return r;
76 }
77
78 r = amdgpu_ucode_validate(adev->vcn.fw);
79 if (r) {
80 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
81 fw_name);
82 release_firmware(adev->vcn.fw);
83 adev->vcn.fw = NULL;
84 return r;
85 }
86
87 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
88 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
89 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
90 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
91 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
92 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
93 version_major, version_minor, family_id);
94
95
96 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
97 + AMDGPU_VCN_SESSION_SIZE * 40;
98 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
99 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
100 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
101 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
102 &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
103 if (r) {
104 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
105 return r;
106 }
107
108 ring = &adev->vcn.ring_dec;
109 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
110 r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
111 rq, amdgpu_sched_jobs);
112 if (r != 0) {
113 DRM_ERROR("Failed setting up VCN dec run queue.\n");
114 return r;
115 }
116
117 ring = &adev->vcn.ring_enc[0];
118 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
119 r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
120 rq, amdgpu_sched_jobs);
121 if (r != 0) {
122 DRM_ERROR("Failed setting up VCN enc run queue.\n");
123 return r;
124 }
125
126 return 0;
127 }
128
amdgpu_vcn_sw_fini(struct amdgpu_device * adev)129 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
130 {
131 int i;
132
133 kfree(adev->vcn.saved_bo);
134
135 amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
136
137 amd_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc);
138
139 amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
140 &adev->vcn.gpu_addr,
141 (void **)&adev->vcn.cpu_addr);
142
143 amdgpu_ring_fini(&adev->vcn.ring_dec);
144
145 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
146 amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
147
148 release_firmware(adev->vcn.fw);
149
150 return 0;
151 }
152
amdgpu_vcn_suspend(struct amdgpu_device * adev)153 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
154 {
155 unsigned size;
156 void *ptr;
157
158 cancel_delayed_work_sync(&adev->vcn.idle_work);
159
160 if (adev->vcn.vcpu_bo == NULL)
161 return 0;
162
163 size = amdgpu_bo_size(adev->vcn.vcpu_bo);
164 ptr = adev->vcn.cpu_addr;
165
166 adev->vcn.saved_bo = kmalloc(size, GFP_KERNEL);
167 if (!adev->vcn.saved_bo)
168 return -ENOMEM;
169
170 memcpy_fromio(adev->vcn.saved_bo, ptr, size);
171
172 return 0;
173 }
174
amdgpu_vcn_resume(struct amdgpu_device * adev)175 int amdgpu_vcn_resume(struct amdgpu_device *adev)
176 {
177 unsigned size;
178 void *ptr;
179
180 if (adev->vcn.vcpu_bo == NULL)
181 return -EINVAL;
182
183 size = amdgpu_bo_size(adev->vcn.vcpu_bo);
184 ptr = adev->vcn.cpu_addr;
185
186 if (adev->vcn.saved_bo != NULL) {
187 memcpy_toio(ptr, adev->vcn.saved_bo, size);
188 kfree(adev->vcn.saved_bo);
189 adev->vcn.saved_bo = NULL;
190 } else {
191 const struct common_firmware_header *hdr;
192 unsigned offset;
193
194 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
195 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
196 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
197 memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
198 le32_to_cpu(hdr->ucode_size_bytes));
199 size -= le32_to_cpu(hdr->ucode_size_bytes);
200 ptr += le32_to_cpu(hdr->ucode_size_bytes);
201 }
202 memset_io(ptr, 0, size);
203 }
204
205 return 0;
206 }
207
amdgpu_vcn_idle_work_handler(struct work_struct * work)208 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
209 {
210 struct amdgpu_device *adev =
211 container_of(work, struct amdgpu_device, vcn.idle_work.work);
212 unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
213
214 if (fences == 0) {
215 if (adev->pm.dpm_enabled) {
216 /* might be used when with pg/cg
217 amdgpu_dpm_enable_uvd(adev, false);
218 */
219 }
220 } else {
221 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
222 }
223 }
224
amdgpu_vcn_ring_begin_use(struct amdgpu_ring * ring)225 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
226 {
227 struct amdgpu_device *adev = ring->adev;
228 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
229
230 if (set_clocks && adev->pm.dpm_enabled) {
231 /* might be used when with pg/cg
232 amdgpu_dpm_enable_uvd(adev, true);
233 */
234 }
235 }
236
amdgpu_vcn_ring_end_use(struct amdgpu_ring * ring)237 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
238 {
239 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
240 }
241
amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring * ring)242 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
243 {
244 struct amdgpu_device *adev = ring->adev;
245 uint32_t tmp = 0;
246 unsigned i;
247 int r;
248
249 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
250 r = amdgpu_ring_alloc(ring, 3);
251 if (r) {
252 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
253 ring->idx, r);
254 return r;
255 }
256 amdgpu_ring_write(ring,
257 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
258 amdgpu_ring_write(ring, 0xDEADBEEF);
259 amdgpu_ring_commit(ring);
260 for (i = 0; i < adev->usec_timeout; i++) {
261 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
262 if (tmp == 0xDEADBEEF)
263 break;
264 DRM_UDELAY(1);
265 }
266
267 if (i < adev->usec_timeout) {
268 DRM_INFO("ring test on %d succeeded in %d usecs\n",
269 ring->idx, i);
270 } else {
271 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
272 ring->idx, tmp);
273 r = -EINVAL;
274 }
275 return r;
276 }
277
amdgpu_vcn_dec_send_msg(struct amdgpu_ring * ring,struct amdgpu_bo * bo,bool direct,struct dma_fence ** fence)278 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
279 bool direct, struct dma_fence **fence)
280 {
281 struct ttm_validate_buffer tv;
282 struct ww_acquire_ctx ticket;
283 struct list_head head;
284 struct amdgpu_job *job;
285 struct amdgpu_ib *ib;
286 struct dma_fence *f = NULL;
287 struct amdgpu_device *adev = ring->adev;
288 uint64_t addr;
289 int i, r;
290
291 memset(&tv, 0, sizeof(tv));
292 tv.bo = &bo->tbo;
293
294 INIT_LIST_HEAD(&head);
295 list_add(&tv.head, &head);
296
297 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
298 if (r)
299 return r;
300
301 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
302 if (r)
303 goto err;
304
305 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
306 if (r)
307 goto err;
308
309 ib = &job->ibs[0];
310 addr = amdgpu_bo_gpu_offset(bo);
311 ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
312 ib->ptr[1] = addr;
313 ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
314 ib->ptr[3] = addr >> 32;
315 ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
316 ib->ptr[5] = 0;
317 for (i = 6; i < 16; i += 2) {
318 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
319 ib->ptr[i+1] = 0;
320 }
321 ib->length_dw = 16;
322
323 if (direct) {
324 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
325 job->fence = dma_fence_get(f);
326 if (r)
327 goto err_free;
328
329 amdgpu_job_free(job);
330 } else {
331 r = amdgpu_job_submit(job, ring, &adev->vcn.entity_dec,
332 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
333 if (r)
334 goto err_free;
335 }
336
337 ttm_eu_fence_buffer_objects(&ticket, &head, f);
338
339 if (fence)
340 *fence = dma_fence_get(f);
341 amdgpu_bo_unref(&bo);
342 dma_fence_put(f);
343
344 return 0;
345
346 err_free:
347 amdgpu_job_free(job);
348
349 err:
350 ttm_eu_backoff_reservation(&ticket, &head);
351 return r;
352 }
353
amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct dma_fence ** fence)354 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
355 struct dma_fence **fence)
356 {
357 struct amdgpu_device *adev = ring->adev;
358 struct amdgpu_bo *bo;
359 uint32_t *msg;
360 int r, i;
361
362 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
363 AMDGPU_GEM_DOMAIN_VRAM,
364 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
365 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
366 NULL, NULL, 0, &bo);
367 if (r)
368 return r;
369
370 r = amdgpu_bo_reserve(bo, false);
371 if (r) {
372 amdgpu_bo_unref(&bo);
373 return r;
374 }
375
376 r = amdgpu_bo_kmap(bo, (void **)&msg);
377 if (r) {
378 amdgpu_bo_unreserve(bo);
379 amdgpu_bo_unref(&bo);
380 return r;
381 }
382
383 msg[0] = cpu_to_le32(0x00000028);
384 msg[1] = cpu_to_le32(0x00000038);
385 msg[2] = cpu_to_le32(0x00000001);
386 msg[3] = cpu_to_le32(0x00000000);
387 msg[4] = cpu_to_le32(handle);
388 msg[5] = cpu_to_le32(0x00000000);
389 msg[6] = cpu_to_le32(0x00000001);
390 msg[7] = cpu_to_le32(0x00000028);
391 msg[8] = cpu_to_le32(0x00000010);
392 msg[9] = cpu_to_le32(0x00000000);
393 msg[10] = cpu_to_le32(0x00000007);
394 msg[11] = cpu_to_le32(0x00000000);
395 msg[12] = cpu_to_le32(0x00000780);
396 msg[13] = cpu_to_le32(0x00000440);
397 for (i = 14; i < 1024; ++i)
398 msg[i] = cpu_to_le32(0x0);
399
400 amdgpu_bo_kunmap(bo);
401 amdgpu_bo_unreserve(bo);
402
403 return amdgpu_vcn_dec_send_msg(ring, bo, true, fence);
404 }
405
amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,bool direct,struct dma_fence ** fence)406 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
407 bool direct, struct dma_fence **fence)
408 {
409 struct amdgpu_device *adev = ring->adev;
410 struct amdgpu_bo *bo;
411 uint32_t *msg;
412 int r, i;
413
414 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
415 AMDGPU_GEM_DOMAIN_VRAM,
416 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
417 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
418 NULL, NULL, 0, &bo);
419 if (r)
420 return r;
421
422 r = amdgpu_bo_reserve(bo, false);
423 if (r) {
424 amdgpu_bo_unref(&bo);
425 return r;
426 }
427
428 r = amdgpu_bo_kmap(bo, (void **)&msg);
429 if (r) {
430 amdgpu_bo_unreserve(bo);
431 amdgpu_bo_unref(&bo);
432 return r;
433 }
434
435 msg[0] = cpu_to_le32(0x00000028);
436 msg[1] = cpu_to_le32(0x00000018);
437 msg[2] = cpu_to_le32(0x00000000);
438 msg[3] = cpu_to_le32(0x00000002);
439 msg[4] = cpu_to_le32(handle);
440 msg[5] = cpu_to_le32(0x00000000);
441 for (i = 6; i < 1024; ++i)
442 msg[i] = cpu_to_le32(0x0);
443
444 amdgpu_bo_kunmap(bo);
445 amdgpu_bo_unreserve(bo);
446
447 return amdgpu_vcn_dec_send_msg(ring, bo, direct, fence);
448 }
449
amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)450 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
451 {
452 struct dma_fence *fence;
453 long r;
454
455 r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
456 if (r) {
457 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
458 goto error;
459 }
460
461 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, true, &fence);
462 if (r) {
463 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
464 goto error;
465 }
466
467 r = dma_fence_wait_timeout(fence, false, timeout);
468 if (r == 0) {
469 DRM_ERROR("amdgpu: IB test timed out.\n");
470 r = -ETIMEDOUT;
471 } else if (r < 0) {
472 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
473 } else {
474 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
475 r = 0;
476 }
477
478 dma_fence_put(fence);
479
480 error:
481 return r;
482 }
483
amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring * ring)484 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
485 {
486 struct amdgpu_device *adev = ring->adev;
487 uint32_t rptr = amdgpu_ring_get_rptr(ring);
488 unsigned i;
489 int r;
490
491 r = amdgpu_ring_alloc(ring, 16);
492 if (r) {
493 DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
494 ring->idx, r);
495 return r;
496 }
497 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
498 amdgpu_ring_commit(ring);
499
500 for (i = 0; i < adev->usec_timeout; i++) {
501 if (amdgpu_ring_get_rptr(ring) != rptr)
502 break;
503 DRM_UDELAY(1);
504 }
505
506 if (i < adev->usec_timeout) {
507 DRM_INFO("ring test on %d succeeded in %d usecs\n",
508 ring->idx, i);
509 } else {
510 DRM_ERROR("amdgpu: ring %d test failed\n",
511 ring->idx);
512 r = -ETIMEDOUT;
513 }
514
515 return r;
516 }
517
amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct dma_fence ** fence)518 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
519 struct dma_fence **fence)
520 {
521 const unsigned ib_size_dw = 16;
522 struct amdgpu_job *job;
523 struct amdgpu_ib *ib;
524 struct dma_fence *f = NULL;
525 uint64_t dummy;
526 int i, r;
527
528 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
529 if (r)
530 return r;
531
532 ib = &job->ibs[0];
533 dummy = ib->gpu_addr + 1024;
534
535 ib->length_dw = 0;
536 ib->ptr[ib->length_dw++] = 0x00000018;
537 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
538 ib->ptr[ib->length_dw++] = handle;
539 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
540 ib->ptr[ib->length_dw++] = dummy;
541 ib->ptr[ib->length_dw++] = 0x0000000b;
542
543 ib->ptr[ib->length_dw++] = 0x00000014;
544 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
545 ib->ptr[ib->length_dw++] = 0x0000001c;
546 ib->ptr[ib->length_dw++] = 0x00000000;
547 ib->ptr[ib->length_dw++] = 0x00000000;
548
549 ib->ptr[ib->length_dw++] = 0x00000008;
550 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
551
552 for (i = ib->length_dw; i < ib_size_dw; ++i)
553 ib->ptr[i] = 0x0;
554
555 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
556 job->fence = dma_fence_get(f);
557 if (r)
558 goto err;
559
560 amdgpu_job_free(job);
561 if (fence)
562 *fence = dma_fence_get(f);
563 dma_fence_put(f);
564
565 return 0;
566
567 err:
568 amdgpu_job_free(job);
569 return r;
570 }
571
amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct dma_fence ** fence)572 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
573 struct dma_fence **fence)
574 {
575 const unsigned ib_size_dw = 16;
576 struct amdgpu_job *job;
577 struct amdgpu_ib *ib;
578 struct dma_fence *f = NULL;
579 uint64_t dummy;
580 int i, r;
581
582 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
583 if (r)
584 return r;
585
586 ib = &job->ibs[0];
587 dummy = ib->gpu_addr + 1024;
588
589 ib->length_dw = 0;
590 ib->ptr[ib->length_dw++] = 0x00000018;
591 ib->ptr[ib->length_dw++] = 0x00000001;
592 ib->ptr[ib->length_dw++] = handle;
593 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
594 ib->ptr[ib->length_dw++] = dummy;
595 ib->ptr[ib->length_dw++] = 0x0000000b;
596
597 ib->ptr[ib->length_dw++] = 0x00000014;
598 ib->ptr[ib->length_dw++] = 0x00000002;
599 ib->ptr[ib->length_dw++] = 0x0000001c;
600 ib->ptr[ib->length_dw++] = 0x00000000;
601 ib->ptr[ib->length_dw++] = 0x00000000;
602
603 ib->ptr[ib->length_dw++] = 0x00000008;
604 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
605
606 for (i = ib->length_dw; i < ib_size_dw; ++i)
607 ib->ptr[i] = 0x0;
608
609 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
610 job->fence = dma_fence_get(f);
611 if (r)
612 goto err;
613
614 amdgpu_job_free(job);
615 if (fence)
616 *fence = dma_fence_get(f);
617 dma_fence_put(f);
618
619 return 0;
620
621 err:
622 amdgpu_job_free(job);
623 return r;
624 }
625
amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)626 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
627 {
628 struct dma_fence *fence = NULL;
629 long r;
630
631 r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
632 if (r) {
633 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
634 goto error;
635 }
636
637 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
638 if (r) {
639 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
640 goto error;
641 }
642
643 r = dma_fence_wait_timeout(fence, false, timeout);
644 if (r == 0) {
645 DRM_ERROR("amdgpu: IB test timed out.\n");
646 r = -ETIMEDOUT;
647 } else if (r < 0) {
648 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
649 } else {
650 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
651 r = 0;
652 }
653 error:
654 dma_fence_put(fence);
655 return r;
656 }
657