1 /*
2 * Aic94xx SAS/SATA driver hardware interface.
3 *
4 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This file is part of the aic94xx driver.
10 *
11 * The aic94xx driver is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; version 2 of the
14 * License.
15 *
16 * The aic94xx driver is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with the aic94xx driver; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 *
25 */
26
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/module.h>
31 #include <linux/firmware.h>
32
33 #include "aic94xx.h"
34 #include "aic94xx_reg.h"
35 #include "aic94xx_hwi.h"
36 #include "aic94xx_seq.h"
37 #include "aic94xx_dump.h"
38
39 u32 MBAR0_SWB_SIZE;
40
41 /* ---------- Initialization ---------- */
42
asd_get_user_sas_addr(struct asd_ha_struct * asd_ha)43 static int asd_get_user_sas_addr(struct asd_ha_struct *asd_ha)
44 {
45 /* adapter came with a sas address */
46 if (asd_ha->hw_prof.sas_addr[0])
47 return 0;
48
49 return sas_request_addr(asd_ha->sas_ha.core.shost,
50 asd_ha->hw_prof.sas_addr);
51 }
52
asd_propagate_sas_addr(struct asd_ha_struct * asd_ha)53 static void asd_propagate_sas_addr(struct asd_ha_struct *asd_ha)
54 {
55 int i;
56
57 for (i = 0; i < ASD_MAX_PHYS; i++) {
58 if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0)
59 continue;
60 /* Set a phy's address only if it has none.
61 */
62 ASD_DPRINTK("setting phy%d addr to %llx\n", i,
63 SAS_ADDR(asd_ha->hw_prof.sas_addr));
64 memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr,
65 asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE);
66 }
67 }
68
69 /* ---------- PHY initialization ---------- */
70
asd_init_phy_identify(struct asd_phy * phy)71 static void asd_init_phy_identify(struct asd_phy *phy)
72 {
73 phy->identify_frame = phy->id_frm_tok->vaddr;
74
75 memset(phy->identify_frame, 0, sizeof(*phy->identify_frame));
76
77 phy->identify_frame->dev_type = SAS_END_DEVICE;
78 if (phy->sas_phy.role & PHY_ROLE_INITIATOR)
79 phy->identify_frame->initiator_bits = phy->sas_phy.iproto;
80 if (phy->sas_phy.role & PHY_ROLE_TARGET)
81 phy->identify_frame->target_bits = phy->sas_phy.tproto;
82 memcpy(phy->identify_frame->sas_addr, phy->phy_desc->sas_addr,
83 SAS_ADDR_SIZE);
84 phy->identify_frame->phy_id = phy->sas_phy.id;
85 }
86
asd_init_phy(struct asd_phy * phy)87 static int asd_init_phy(struct asd_phy *phy)
88 {
89 struct asd_ha_struct *asd_ha = phy->sas_phy.ha->lldd_ha;
90 struct asd_sas_phy *sas_phy = &phy->sas_phy;
91
92 sas_phy->enabled = 1;
93 sas_phy->class = SAS;
94 sas_phy->iproto = SAS_PROTOCOL_ALL;
95 sas_phy->tproto = 0;
96 sas_phy->type = PHY_TYPE_PHYSICAL;
97 sas_phy->role = PHY_ROLE_INITIATOR;
98 sas_phy->oob_mode = OOB_NOT_CONNECTED;
99 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
100
101 phy->id_frm_tok = asd_alloc_coherent(asd_ha,
102 sizeof(*phy->identify_frame),
103 GFP_KERNEL);
104 if (!phy->id_frm_tok) {
105 asd_printk("no mem for IDENTIFY for phy%d\n", sas_phy->id);
106 return -ENOMEM;
107 } else
108 asd_init_phy_identify(phy);
109
110 memset(phy->frame_rcvd, 0, sizeof(phy->frame_rcvd));
111
112 return 0;
113 }
114
asd_init_ports(struct asd_ha_struct * asd_ha)115 static void asd_init_ports(struct asd_ha_struct *asd_ha)
116 {
117 int i;
118
119 spin_lock_init(&asd_ha->asd_ports_lock);
120 for (i = 0; i < ASD_MAX_PHYS; i++) {
121 struct asd_port *asd_port = &asd_ha->asd_ports[i];
122
123 memset(asd_port->sas_addr, 0, SAS_ADDR_SIZE);
124 memset(asd_port->attached_sas_addr, 0, SAS_ADDR_SIZE);
125 asd_port->phy_mask = 0;
126 asd_port->num_phys = 0;
127 }
128 }
129
asd_init_phys(struct asd_ha_struct * asd_ha)130 static int asd_init_phys(struct asd_ha_struct *asd_ha)
131 {
132 u8 i;
133 u8 phy_mask = asd_ha->hw_prof.enabled_phys;
134
135 for (i = 0; i < ASD_MAX_PHYS; i++) {
136 struct asd_phy *phy = &asd_ha->phys[i];
137
138 phy->phy_desc = &asd_ha->hw_prof.phy_desc[i];
139 phy->asd_port = NULL;
140
141 phy->sas_phy.enabled = 0;
142 phy->sas_phy.id = i;
143 phy->sas_phy.sas_addr = &phy->phy_desc->sas_addr[0];
144 phy->sas_phy.frame_rcvd = &phy->frame_rcvd[0];
145 phy->sas_phy.ha = &asd_ha->sas_ha;
146 phy->sas_phy.lldd_phy = phy;
147 }
148
149 /* Now enable and initialize only the enabled phys. */
150 for_each_phy(phy_mask, phy_mask, i) {
151 int err = asd_init_phy(&asd_ha->phys[i]);
152 if (err)
153 return err;
154 }
155
156 return 0;
157 }
158
159 /* ---------- Sliding windows ---------- */
160
asd_init_sw(struct asd_ha_struct * asd_ha)161 static int asd_init_sw(struct asd_ha_struct *asd_ha)
162 {
163 struct pci_dev *pcidev = asd_ha->pcidev;
164 int err;
165 u32 v;
166
167 /* Unlock MBARs */
168 err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v);
169 if (err) {
170 asd_printk("couldn't access conf. space of %s\n",
171 pci_name(pcidev));
172 goto Err;
173 }
174 if (v)
175 err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v);
176 if (err) {
177 asd_printk("couldn't write to MBAR_KEY of %s\n",
178 pci_name(pcidev));
179 goto Err;
180 }
181
182 /* Set sliding windows A, B and C to point to proper internal
183 * memory regions.
184 */
185 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR);
186 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWB,
187 REG_BASE_ADDR_CSEQCIO);
188 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWC, REG_BASE_ADDR_EXSI);
189 asd_ha->io_handle[0].swa_base = REG_BASE_ADDR;
190 asd_ha->io_handle[0].swb_base = REG_BASE_ADDR_CSEQCIO;
191 asd_ha->io_handle[0].swc_base = REG_BASE_ADDR_EXSI;
192 MBAR0_SWB_SIZE = asd_ha->io_handle[0].len - 0x80;
193 if (!asd_ha->iospace) {
194 /* MBAR1 will point to OCM (On Chip Memory) */
195 pci_write_config_dword(pcidev, PCI_CONF_MBAR1, OCM_BASE_ADDR);
196 asd_ha->io_handle[1].swa_base = OCM_BASE_ADDR;
197 }
198 spin_lock_init(&asd_ha->iolock);
199 Err:
200 return err;
201 }
202
203 /* ---------- SCB initialization ---------- */
204
205 /**
206 * asd_init_scbs - manually allocate the first SCB.
207 * @asd_ha: pointer to host adapter structure
208 *
209 * This allocates the very first SCB which would be sent to the
210 * sequencer for execution. Its bus address is written to
211 * CSEQ_Q_NEW_POINTER, mode page 2, mode 8. Since the bus address of
212 * the _next_ scb to be DMA-ed to the host adapter is read from the last
213 * SCB DMA-ed to the host adapter, we have to always stay one step
214 * ahead of the sequencer and keep one SCB already allocated.
215 */
asd_init_scbs(struct asd_ha_struct * asd_ha)216 static int asd_init_scbs(struct asd_ha_struct *asd_ha)
217 {
218 struct asd_seq_data *seq = &asd_ha->seq;
219 int bitmap_bytes;
220
221 /* allocate the index array and bitmap */
222 asd_ha->seq.tc_index_bitmap_bits = asd_ha->hw_prof.max_scbs;
223 asd_ha->seq.tc_index_array = kzalloc(asd_ha->seq.tc_index_bitmap_bits*
224 sizeof(void *), GFP_KERNEL);
225 if (!asd_ha->seq.tc_index_array)
226 return -ENOMEM;
227
228 bitmap_bytes = (asd_ha->seq.tc_index_bitmap_bits+7)/8;
229 bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
230 asd_ha->seq.tc_index_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
231 if (!asd_ha->seq.tc_index_bitmap) {
232 kfree(asd_ha->seq.tc_index_array);
233 asd_ha->seq.tc_index_array = NULL;
234 return -ENOMEM;
235 }
236
237 spin_lock_init(&seq->tc_index_lock);
238
239 seq->next_scb.size = sizeof(struct scb);
240 seq->next_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool, GFP_KERNEL,
241 &seq->next_scb.dma_handle);
242 if (!seq->next_scb.vaddr) {
243 kfree(asd_ha->seq.tc_index_bitmap);
244 kfree(asd_ha->seq.tc_index_array);
245 asd_ha->seq.tc_index_bitmap = NULL;
246 asd_ha->seq.tc_index_array = NULL;
247 return -ENOMEM;
248 }
249
250 seq->pending = 0;
251 spin_lock_init(&seq->pend_q_lock);
252 INIT_LIST_HEAD(&seq->pend_q);
253
254 return 0;
255 }
256
asd_get_max_scb_ddb(struct asd_ha_struct * asd_ha)257 static void asd_get_max_scb_ddb(struct asd_ha_struct *asd_ha)
258 {
259 asd_ha->hw_prof.max_scbs = asd_get_cmdctx_size(asd_ha)/ASD_SCB_SIZE;
260 asd_ha->hw_prof.max_ddbs = asd_get_devctx_size(asd_ha)/ASD_DDB_SIZE;
261 ASD_DPRINTK("max_scbs:%d, max_ddbs:%d\n",
262 asd_ha->hw_prof.max_scbs,
263 asd_ha->hw_prof.max_ddbs);
264 }
265
266 /* ---------- Done List initialization ---------- */
267
268 static void asd_dl_tasklet_handler(unsigned long);
269
asd_init_dl(struct asd_ha_struct * asd_ha)270 static int asd_init_dl(struct asd_ha_struct *asd_ha)
271 {
272 asd_ha->seq.actual_dl
273 = asd_alloc_coherent(asd_ha,
274 ASD_DL_SIZE * sizeof(struct done_list_struct),
275 GFP_KERNEL);
276 if (!asd_ha->seq.actual_dl)
277 return -ENOMEM;
278 asd_ha->seq.dl = asd_ha->seq.actual_dl->vaddr;
279 asd_ha->seq.dl_toggle = ASD_DEF_DL_TOGGLE;
280 asd_ha->seq.dl_next = 0;
281 tasklet_init(&asd_ha->seq.dl_tasklet, asd_dl_tasklet_handler,
282 (unsigned long) asd_ha);
283
284 return 0;
285 }
286
287 /* ---------- EDB and ESCB init ---------- */
288
asd_alloc_edbs(struct asd_ha_struct * asd_ha,gfp_t gfp_flags)289 static int asd_alloc_edbs(struct asd_ha_struct *asd_ha, gfp_t gfp_flags)
290 {
291 struct asd_seq_data *seq = &asd_ha->seq;
292 int i;
293
294 seq->edb_arr = kmalloc(seq->num_edbs*sizeof(*seq->edb_arr), gfp_flags);
295 if (!seq->edb_arr)
296 return -ENOMEM;
297
298 for (i = 0; i < seq->num_edbs; i++) {
299 seq->edb_arr[i] = asd_alloc_coherent(asd_ha, ASD_EDB_SIZE,
300 gfp_flags);
301 if (!seq->edb_arr[i])
302 goto Err_unroll;
303 memset(seq->edb_arr[i]->vaddr, 0, ASD_EDB_SIZE);
304 }
305
306 ASD_DPRINTK("num_edbs:%d\n", seq->num_edbs);
307
308 return 0;
309
310 Err_unroll:
311 for (i-- ; i >= 0; i--)
312 asd_free_coherent(asd_ha, seq->edb_arr[i]);
313 kfree(seq->edb_arr);
314 seq->edb_arr = NULL;
315
316 return -ENOMEM;
317 }
318
asd_alloc_escbs(struct asd_ha_struct * asd_ha,gfp_t gfp_flags)319 static int asd_alloc_escbs(struct asd_ha_struct *asd_ha,
320 gfp_t gfp_flags)
321 {
322 struct asd_seq_data *seq = &asd_ha->seq;
323 struct asd_ascb *escb;
324 int i, escbs;
325
326 seq->escb_arr = kmalloc(seq->num_escbs*sizeof(*seq->escb_arr),
327 gfp_flags);
328 if (!seq->escb_arr)
329 return -ENOMEM;
330
331 escbs = seq->num_escbs;
332 escb = asd_ascb_alloc_list(asd_ha, &escbs, gfp_flags);
333 if (!escb) {
334 asd_printk("couldn't allocate list of escbs\n");
335 goto Err;
336 }
337 seq->num_escbs -= escbs; /* subtract what was not allocated */
338 ASD_DPRINTK("num_escbs:%d\n", seq->num_escbs);
339
340 for (i = 0; i < seq->num_escbs; i++, escb = list_entry(escb->list.next,
341 struct asd_ascb,
342 list)) {
343 seq->escb_arr[i] = escb;
344 escb->scb->header.opcode = EMPTY_SCB;
345 }
346
347 return 0;
348 Err:
349 kfree(seq->escb_arr);
350 seq->escb_arr = NULL;
351 return -ENOMEM;
352
353 }
354
asd_assign_edbs2escbs(struct asd_ha_struct * asd_ha)355 static void asd_assign_edbs2escbs(struct asd_ha_struct *asd_ha)
356 {
357 struct asd_seq_data *seq = &asd_ha->seq;
358 int i, k, z = 0;
359
360 for (i = 0; i < seq->num_escbs; i++) {
361 struct asd_ascb *ascb = seq->escb_arr[i];
362 struct empty_scb *escb = &ascb->scb->escb;
363
364 ascb->edb_index = z;
365
366 escb->num_valid = ASD_EDBS_PER_SCB;
367
368 for (k = 0; k < ASD_EDBS_PER_SCB; k++) {
369 struct sg_el *eb = &escb->eb[k];
370 struct asd_dma_tok *edb = seq->edb_arr[z++];
371
372 memset(eb, 0, sizeof(*eb));
373 eb->bus_addr = cpu_to_le64(((u64) edb->dma_handle));
374 eb->size = cpu_to_le32(((u32) edb->size));
375 }
376 }
377 }
378
379 /**
380 * asd_init_escbs -- allocate and initialize empty scbs
381 * @asd_ha: pointer to host adapter structure
382 *
383 * An empty SCB has sg_elements of ASD_EDBS_PER_SCB (7) buffers.
384 * They transport sense data, etc.
385 */
asd_init_escbs(struct asd_ha_struct * asd_ha)386 static int asd_init_escbs(struct asd_ha_struct *asd_ha)
387 {
388 struct asd_seq_data *seq = &asd_ha->seq;
389 int err = 0;
390
391 /* Allocate two empty data buffers (edb) per sequencer. */
392 int edbs = 2*(1+asd_ha->hw_prof.num_phys);
393
394 seq->num_escbs = (edbs+ASD_EDBS_PER_SCB-1)/ASD_EDBS_PER_SCB;
395 seq->num_edbs = seq->num_escbs * ASD_EDBS_PER_SCB;
396
397 err = asd_alloc_edbs(asd_ha, GFP_KERNEL);
398 if (err) {
399 asd_printk("couldn't allocate edbs\n");
400 return err;
401 }
402
403 err = asd_alloc_escbs(asd_ha, GFP_KERNEL);
404 if (err) {
405 asd_printk("couldn't allocate escbs\n");
406 return err;
407 }
408
409 asd_assign_edbs2escbs(asd_ha);
410 /* In order to insure that normal SCBs do not overfill sequencer
411 * memory and leave no space for escbs (halting condition),
412 * we increment pending here by the number of escbs. However,
413 * escbs are never pending.
414 */
415 seq->pending = seq->num_escbs;
416 seq->can_queue = 1 + (asd_ha->hw_prof.max_scbs - seq->pending)/2;
417
418 return 0;
419 }
420
421 /* ---------- HW initialization ---------- */
422
423 /**
424 * asd_chip_hardrst -- hard reset the chip
425 * @asd_ha: pointer to host adapter structure
426 *
427 * This takes 16 cycles and is synchronous to CFCLK, which runs
428 * at 200 MHz, so this should take at most 80 nanoseconds.
429 */
asd_chip_hardrst(struct asd_ha_struct * asd_ha)430 int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
431 {
432 int i;
433 int count = 100;
434 u32 reg;
435
436 for (i = 0 ; i < 4 ; i++) {
437 asd_write_reg_dword(asd_ha, COMBIST, HARDRST);
438 }
439
440 do {
441 udelay(1);
442 reg = asd_read_reg_dword(asd_ha, CHIMINT);
443 if (reg & HARDRSTDET) {
444 asd_write_reg_dword(asd_ha, CHIMINT,
445 HARDRSTDET|PORRSTDET);
446 return 0;
447 }
448 } while (--count > 0);
449
450 return -ENODEV;
451 }
452
453 /**
454 * asd_init_chip -- initialize the chip
455 * @asd_ha: pointer to host adapter structure
456 *
457 * Hard resets the chip, disables HA interrupts, downloads the sequnecer
458 * microcode and starts the sequencers. The caller has to explicitly
459 * enable HA interrupts with asd_enable_ints(asd_ha).
460 */
asd_init_chip(struct asd_ha_struct * asd_ha)461 static int asd_init_chip(struct asd_ha_struct *asd_ha)
462 {
463 int err;
464
465 err = asd_chip_hardrst(asd_ha);
466 if (err) {
467 asd_printk("couldn't hard reset %s\n",
468 pci_name(asd_ha->pcidev));
469 goto out;
470 }
471
472 asd_disable_ints(asd_ha);
473
474 err = asd_init_seqs(asd_ha);
475 if (err) {
476 asd_printk("couldn't init seqs for %s\n",
477 pci_name(asd_ha->pcidev));
478 goto out;
479 }
480
481 err = asd_start_seqs(asd_ha);
482 if (err) {
483 asd_printk("couldn't start seqs for %s\n",
484 pci_name(asd_ha->pcidev));
485 goto out;
486 }
487 out:
488 return err;
489 }
490
491 #define MAX_DEVS ((OCM_MAX_SIZE) / (ASD_DDB_SIZE))
492
493 static int max_devs = 0;
494 module_param_named(max_devs, max_devs, int, S_IRUGO);
495 MODULE_PARM_DESC(max_devs, "\n"
496 "\tMaximum number of SAS devices to support (not LUs).\n"
497 "\tDefault: 2176, Maximum: 65663.\n");
498
499 static int max_cmnds = 0;
500 module_param_named(max_cmnds, max_cmnds, int, S_IRUGO);
501 MODULE_PARM_DESC(max_cmnds, "\n"
502 "\tMaximum number of commands queuable.\n"
503 "\tDefault: 512, Maximum: 66047.\n");
504
asd_extend_devctx_ocm(struct asd_ha_struct * asd_ha)505 static void asd_extend_devctx_ocm(struct asd_ha_struct *asd_ha)
506 {
507 unsigned long dma_addr = OCM_BASE_ADDR;
508 u32 d;
509
510 dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
511 asd_write_reg_addr(asd_ha, DEVCTXBASE, (dma_addr_t) dma_addr);
512 d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
513 d |= 4;
514 asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
515 asd_ha->hw_prof.max_ddbs += MAX_DEVS;
516 }
517
asd_extend_devctx(struct asd_ha_struct * asd_ha)518 static int asd_extend_devctx(struct asd_ha_struct *asd_ha)
519 {
520 dma_addr_t dma_handle;
521 unsigned long dma_addr;
522 u32 d;
523 int size;
524
525 asd_extend_devctx_ocm(asd_ha);
526
527 asd_ha->hw_prof.ddb_ext = NULL;
528 if (max_devs <= asd_ha->hw_prof.max_ddbs || max_devs > 0xFFFF) {
529 max_devs = asd_ha->hw_prof.max_ddbs;
530 return 0;
531 }
532
533 size = (max_devs - asd_ha->hw_prof.max_ddbs + 1) * ASD_DDB_SIZE;
534
535 asd_ha->hw_prof.ddb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
536 if (!asd_ha->hw_prof.ddb_ext) {
537 asd_printk("couldn't allocate memory for %d devices\n",
538 max_devs);
539 max_devs = asd_ha->hw_prof.max_ddbs;
540 return -ENOMEM;
541 }
542 dma_handle = asd_ha->hw_prof.ddb_ext->dma_handle;
543 dma_addr = ALIGN((unsigned long) dma_handle, ASD_DDB_SIZE);
544 dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
545 dma_handle = (dma_addr_t) dma_addr;
546 asd_write_reg_addr(asd_ha, DEVCTXBASE, dma_handle);
547 d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
548 d &= ~4;
549 asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
550
551 asd_ha->hw_prof.max_ddbs = max_devs;
552
553 return 0;
554 }
555
asd_extend_cmdctx(struct asd_ha_struct * asd_ha)556 static int asd_extend_cmdctx(struct asd_ha_struct *asd_ha)
557 {
558 dma_addr_t dma_handle;
559 unsigned long dma_addr;
560 u32 d;
561 int size;
562
563 asd_ha->hw_prof.scb_ext = NULL;
564 if (max_cmnds <= asd_ha->hw_prof.max_scbs || max_cmnds > 0xFFFF) {
565 max_cmnds = asd_ha->hw_prof.max_scbs;
566 return 0;
567 }
568
569 size = (max_cmnds - asd_ha->hw_prof.max_scbs + 1) * ASD_SCB_SIZE;
570
571 asd_ha->hw_prof.scb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
572 if (!asd_ha->hw_prof.scb_ext) {
573 asd_printk("couldn't allocate memory for %d commands\n",
574 max_cmnds);
575 max_cmnds = asd_ha->hw_prof.max_scbs;
576 return -ENOMEM;
577 }
578 dma_handle = asd_ha->hw_prof.scb_ext->dma_handle;
579 dma_addr = ALIGN((unsigned long) dma_handle, ASD_SCB_SIZE);
580 dma_addr -= asd_ha->hw_prof.max_scbs * ASD_SCB_SIZE;
581 dma_handle = (dma_addr_t) dma_addr;
582 asd_write_reg_addr(asd_ha, CMDCTXBASE, dma_handle);
583 d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
584 d &= ~1;
585 asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
586
587 asd_ha->hw_prof.max_scbs = max_cmnds;
588
589 return 0;
590 }
591
592 /**
593 * asd_init_ctxmem -- initialize context memory
594 * asd_ha: pointer to host adapter structure
595 *
596 * This function sets the maximum number of SCBs and
597 * DDBs which can be used by the sequencer. This is normally
598 * 512 and 128 respectively. If support for more SCBs or more DDBs
599 * is required then CMDCTXBASE, DEVCTXBASE and CTXDOMAIN are
600 * initialized here to extend context memory to point to host memory,
601 * thus allowing unlimited support for SCBs and DDBs -- only limited
602 * by host memory.
603 */
asd_init_ctxmem(struct asd_ha_struct * asd_ha)604 static int asd_init_ctxmem(struct asd_ha_struct *asd_ha)
605 {
606 int bitmap_bytes;
607
608 asd_get_max_scb_ddb(asd_ha);
609 asd_extend_devctx(asd_ha);
610 asd_extend_cmdctx(asd_ha);
611
612 /* The kernel wants bitmaps to be unsigned long sized. */
613 bitmap_bytes = (asd_ha->hw_prof.max_ddbs+7)/8;
614 bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
615 asd_ha->hw_prof.ddb_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
616 if (!asd_ha->hw_prof.ddb_bitmap)
617 return -ENOMEM;
618 spin_lock_init(&asd_ha->hw_prof.ddb_lock);
619
620 return 0;
621 }
622
asd_init_hw(struct asd_ha_struct * asd_ha)623 int asd_init_hw(struct asd_ha_struct *asd_ha)
624 {
625 int err;
626 u32 v;
627
628 err = asd_init_sw(asd_ha);
629 if (err)
630 return err;
631
632 err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v);
633 if (err) {
634 asd_printk("couldn't read PCIC_HSTPCIX_CNTRL of %s\n",
635 pci_name(asd_ha->pcidev));
636 return err;
637 }
638 err = pci_write_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL,
639 v | SC_TMR_DIS);
640 if (err) {
641 asd_printk("couldn't disable split completion timer of %s\n",
642 pci_name(asd_ha->pcidev));
643 return err;
644 }
645
646 err = asd_read_ocm(asd_ha);
647 if (err) {
648 asd_printk("couldn't read ocm(%d)\n", err);
649 /* While suspicios, it is not an error that we
650 * couldn't read the OCM. */
651 }
652
653 err = asd_read_flash(asd_ha);
654 if (err) {
655 asd_printk("couldn't read flash(%d)\n", err);
656 /* While suspicios, it is not an error that we
657 * couldn't read FLASH memory.
658 */
659 }
660
661 asd_init_ctxmem(asd_ha);
662
663 if (asd_get_user_sas_addr(asd_ha)) {
664 asd_printk("No SAS Address provided for %s\n",
665 pci_name(asd_ha->pcidev));
666 err = -ENODEV;
667 goto Out;
668 }
669
670 asd_propagate_sas_addr(asd_ha);
671
672 err = asd_init_phys(asd_ha);
673 if (err) {
674 asd_printk("couldn't initialize phys for %s\n",
675 pci_name(asd_ha->pcidev));
676 goto Out;
677 }
678
679 asd_init_ports(asd_ha);
680
681 err = asd_init_scbs(asd_ha);
682 if (err) {
683 asd_printk("couldn't initialize scbs for %s\n",
684 pci_name(asd_ha->pcidev));
685 goto Out;
686 }
687
688 err = asd_init_dl(asd_ha);
689 if (err) {
690 asd_printk("couldn't initialize the done list:%d\n",
691 err);
692 goto Out;
693 }
694
695 err = asd_init_escbs(asd_ha);
696 if (err) {
697 asd_printk("couldn't initialize escbs\n");
698 goto Out;
699 }
700
701 err = asd_init_chip(asd_ha);
702 if (err) {
703 asd_printk("couldn't init the chip\n");
704 goto Out;
705 }
706 Out:
707 return err;
708 }
709
710 /* ---------- Chip reset ---------- */
711
712 /**
713 * asd_chip_reset -- reset the host adapter, etc
714 * @asd_ha: pointer to host adapter structure of interest
715 *
716 * Called from the ISR. Hard reset the chip. Let everything
717 * timeout. This should be no different than hot-unplugging the
718 * host adapter. Once everything times out we'll init the chip with
719 * a call to asd_init_chip() and enable interrupts with asd_enable_ints().
720 * XXX finish.
721 */
asd_chip_reset(struct asd_ha_struct * asd_ha)722 static void asd_chip_reset(struct asd_ha_struct *asd_ha)
723 {
724 struct sas_ha_struct *sas_ha = &asd_ha->sas_ha;
725
726 ASD_DPRINTK("chip reset for %s\n", pci_name(asd_ha->pcidev));
727 asd_chip_hardrst(asd_ha);
728 sas_ha->notify_ha_event(sas_ha, HAE_RESET);
729 }
730
731 /* ---------- Done List Routines ---------- */
732
asd_dl_tasklet_handler(unsigned long data)733 static void asd_dl_tasklet_handler(unsigned long data)
734 {
735 struct asd_ha_struct *asd_ha = (struct asd_ha_struct *) data;
736 struct asd_seq_data *seq = &asd_ha->seq;
737 unsigned long flags;
738
739 while (1) {
740 struct done_list_struct *dl = &seq->dl[seq->dl_next];
741 struct asd_ascb *ascb;
742
743 if ((dl->toggle & DL_TOGGLE_MASK) != seq->dl_toggle)
744 break;
745
746 /* find the aSCB */
747 spin_lock_irqsave(&seq->tc_index_lock, flags);
748 ascb = asd_tc_index_find(seq, (int)le16_to_cpu(dl->index));
749 spin_unlock_irqrestore(&seq->tc_index_lock, flags);
750 if (unlikely(!ascb)) {
751 ASD_DPRINTK("BUG:sequencer:dl:no ascb?!\n");
752 goto next_1;
753 } else if (ascb->scb->header.opcode == EMPTY_SCB) {
754 goto out;
755 } else if (!ascb->uldd_timer && !del_timer(&ascb->timer)) {
756 goto next_1;
757 }
758 spin_lock_irqsave(&seq->pend_q_lock, flags);
759 list_del_init(&ascb->list);
760 seq->pending--;
761 spin_unlock_irqrestore(&seq->pend_q_lock, flags);
762 out:
763 ascb->tasklet_complete(ascb, dl);
764
765 next_1:
766 seq->dl_next = (seq->dl_next + 1) & (ASD_DL_SIZE-1);
767 if (!seq->dl_next)
768 seq->dl_toggle ^= DL_TOGGLE_MASK;
769 }
770 }
771
772 /* ---------- Interrupt Service Routines ---------- */
773
774 /**
775 * asd_process_donelist_isr -- schedule processing of done list entries
776 * @asd_ha: pointer to host adapter structure
777 */
asd_process_donelist_isr(struct asd_ha_struct * asd_ha)778 static void asd_process_donelist_isr(struct asd_ha_struct *asd_ha)
779 {
780 tasklet_schedule(&asd_ha->seq.dl_tasklet);
781 }
782
783 /**
784 * asd_com_sas_isr -- process device communication interrupt (COMINT)
785 * @asd_ha: pointer to host adapter structure
786 */
asd_com_sas_isr(struct asd_ha_struct * asd_ha)787 static void asd_com_sas_isr(struct asd_ha_struct *asd_ha)
788 {
789 u32 comstat = asd_read_reg_dword(asd_ha, COMSTAT);
790
791 /* clear COMSTAT int */
792 asd_write_reg_dword(asd_ha, COMSTAT, 0xFFFFFFFF);
793
794 if (comstat & CSBUFPERR) {
795 asd_printk("%s: command/status buffer dma parity error\n",
796 pci_name(asd_ha->pcidev));
797 } else if (comstat & CSERR) {
798 int i;
799 u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
800 dmaerr &= 0xFF;
801 asd_printk("%s: command/status dma error, DMAERR: 0x%02x, "
802 "CSDMAADR: 0x%04x, CSDMAADR+4: 0x%04x\n",
803 pci_name(asd_ha->pcidev),
804 dmaerr,
805 asd_read_reg_dword(asd_ha, CSDMAADR),
806 asd_read_reg_dword(asd_ha, CSDMAADR+4));
807 asd_printk("CSBUFFER:\n");
808 for (i = 0; i < 8; i++) {
809 asd_printk("%08x %08x %08x %08x\n",
810 asd_read_reg_dword(asd_ha, CSBUFFER),
811 asd_read_reg_dword(asd_ha, CSBUFFER+4),
812 asd_read_reg_dword(asd_ha, CSBUFFER+8),
813 asd_read_reg_dword(asd_ha, CSBUFFER+12));
814 }
815 asd_dump_seq_state(asd_ha, 0);
816 } else if (comstat & OVLYERR) {
817 u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
818 dmaerr = (dmaerr >> 8) & 0xFF;
819 asd_printk("%s: overlay dma error:0x%x\n",
820 pci_name(asd_ha->pcidev),
821 dmaerr);
822 }
823 asd_chip_reset(asd_ha);
824 }
825
asd_arp2_err(struct asd_ha_struct * asd_ha,u32 dchstatus)826 static void asd_arp2_err(struct asd_ha_struct *asd_ha, u32 dchstatus)
827 {
828 static const char *halt_code[256] = {
829 "UNEXPECTED_INTERRUPT0",
830 "UNEXPECTED_INTERRUPT1",
831 "UNEXPECTED_INTERRUPT2",
832 "UNEXPECTED_INTERRUPT3",
833 "UNEXPECTED_INTERRUPT4",
834 "UNEXPECTED_INTERRUPT5",
835 "UNEXPECTED_INTERRUPT6",
836 "UNEXPECTED_INTERRUPT7",
837 "UNEXPECTED_INTERRUPT8",
838 "UNEXPECTED_INTERRUPT9",
839 "UNEXPECTED_INTERRUPT10",
840 [11 ... 19] = "unknown[11,19]",
841 "NO_FREE_SCB_AVAILABLE",
842 "INVALID_SCB_OPCODE",
843 "INVALID_MBX_OPCODE",
844 "INVALID_ATA_STATE",
845 "ATA_QUEUE_FULL",
846 "ATA_TAG_TABLE_FAULT",
847 "ATA_TAG_MASK_FAULT",
848 "BAD_LINK_QUEUE_STATE",
849 "DMA2CHIM_QUEUE_ERROR",
850 "EMPTY_SCB_LIST_FULL",
851 "unknown[30]",
852 "IN_USE_SCB_ON_FREE_LIST",
853 "BAD_OPEN_WAIT_STATE",
854 "INVALID_STP_AFFILIATION",
855 "unknown[34]",
856 "EXEC_QUEUE_ERROR",
857 "TOO_MANY_EMPTIES_NEEDED",
858 "EMPTY_REQ_QUEUE_ERROR",
859 "Q_MONIRTT_MGMT_ERROR",
860 "TARGET_MODE_FLOW_ERROR",
861 "DEVICE_QUEUE_NOT_FOUND",
862 "START_IRTT_TIMER_ERROR",
863 "ABORT_TASK_ILLEGAL_REQ",
864 [43 ... 255] = "unknown[43,255]"
865 };
866
867 if (dchstatus & CSEQINT) {
868 u32 arp2int = asd_read_reg_dword(asd_ha, CARP2INT);
869
870 if (arp2int & (ARP2WAITTO|ARP2ILLOPC|ARP2PERR|ARP2CIOPERR)) {
871 asd_printk("%s: CSEQ arp2int:0x%x\n",
872 pci_name(asd_ha->pcidev),
873 arp2int);
874 } else if (arp2int & ARP2HALTC)
875 asd_printk("%s: CSEQ halted: %s\n",
876 pci_name(asd_ha->pcidev),
877 halt_code[(arp2int>>16)&0xFF]);
878 else
879 asd_printk("%s: CARP2INT:0x%x\n",
880 pci_name(asd_ha->pcidev),
881 arp2int);
882 }
883 if (dchstatus & LSEQINT_MASK) {
884 int lseq;
885 u8 lseq_mask = dchstatus & LSEQINT_MASK;
886
887 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
888 u32 arp2int = asd_read_reg_dword(asd_ha,
889 LmARP2INT(lseq));
890 if (arp2int & (ARP2WAITTO | ARP2ILLOPC | ARP2PERR
891 | ARP2CIOPERR)) {
892 asd_printk("%s: LSEQ%d arp2int:0x%x\n",
893 pci_name(asd_ha->pcidev),
894 lseq, arp2int);
895 /* XXX we should only do lseq reset */
896 } else if (arp2int & ARP2HALTC)
897 asd_printk("%s: LSEQ%d halted: %s\n",
898 pci_name(asd_ha->pcidev),
899 lseq,halt_code[(arp2int>>16)&0xFF]);
900 else
901 asd_printk("%s: LSEQ%d ARP2INT:0x%x\n",
902 pci_name(asd_ha->pcidev), lseq,
903 arp2int);
904 }
905 }
906 asd_chip_reset(asd_ha);
907 }
908
909 /**
910 * asd_dch_sas_isr -- process device channel interrupt (DEVINT)
911 * @asd_ha: pointer to host adapter structure
912 */
asd_dch_sas_isr(struct asd_ha_struct * asd_ha)913 static void asd_dch_sas_isr(struct asd_ha_struct *asd_ha)
914 {
915 u32 dchstatus = asd_read_reg_dword(asd_ha, DCHSTATUS);
916
917 if (dchstatus & CFIFTOERR) {
918 asd_printk("%s: CFIFTOERR\n", pci_name(asd_ha->pcidev));
919 asd_chip_reset(asd_ha);
920 } else
921 asd_arp2_err(asd_ha, dchstatus);
922 }
923
924 /**
925 * ads_rbi_exsi_isr -- process external system interface interrupt (INITERR)
926 * @asd_ha: pointer to host adapter structure
927 */
asd_rbi_exsi_isr(struct asd_ha_struct * asd_ha)928 static void asd_rbi_exsi_isr(struct asd_ha_struct *asd_ha)
929 {
930 u32 stat0r = asd_read_reg_dword(asd_ha, ASISTAT0R);
931
932 if (!(stat0r & ASIERR)) {
933 asd_printk("hmm, EXSI interrupted but no error?\n");
934 return;
935 }
936
937 if (stat0r & ASIFMTERR) {
938 asd_printk("ASI SEEPROM format error for %s\n",
939 pci_name(asd_ha->pcidev));
940 } else if (stat0r & ASISEECHKERR) {
941 u32 stat1r = asd_read_reg_dword(asd_ha, ASISTAT1R);
942 asd_printk("ASI SEEPROM checksum 0x%x error for %s\n",
943 stat1r & CHECKSUM_MASK,
944 pci_name(asd_ha->pcidev));
945 } else {
946 u32 statr = asd_read_reg_dword(asd_ha, ASIERRSTATR);
947
948 if (!(statr & CPI2ASIMSTERR_MASK)) {
949 ASD_DPRINTK("hmm, ASIERR?\n");
950 return;
951 } else {
952 u32 addr = asd_read_reg_dword(asd_ha, ASIERRADDR);
953 u32 data = asd_read_reg_dword(asd_ha, ASIERRDATAR);
954
955 asd_printk("%s: CPI2 xfer err: addr: 0x%x, wdata: 0x%x, "
956 "count: 0x%x, byteen: 0x%x, targerr: 0x%x "
957 "master id: 0x%x, master err: 0x%x\n",
958 pci_name(asd_ha->pcidev),
959 addr, data,
960 (statr & CPI2ASIBYTECNT_MASK) >> 16,
961 (statr & CPI2ASIBYTEEN_MASK) >> 12,
962 (statr & CPI2ASITARGERR_MASK) >> 8,
963 (statr & CPI2ASITARGMID_MASK) >> 4,
964 (statr & CPI2ASIMSTERR_MASK));
965 }
966 }
967 asd_chip_reset(asd_ha);
968 }
969
970 /**
971 * asd_hst_pcix_isr -- process host interface interrupts
972 * @asd_ha: pointer to host adapter structure
973 *
974 * Asserted on PCIX errors: target abort, etc.
975 */
asd_hst_pcix_isr(struct asd_ha_struct * asd_ha)976 static void asd_hst_pcix_isr(struct asd_ha_struct *asd_ha)
977 {
978 u16 status;
979 u32 pcix_status;
980 u32 ecc_status;
981
982 pci_read_config_word(asd_ha->pcidev, PCI_STATUS, &status);
983 pci_read_config_dword(asd_ha->pcidev, PCIX_STATUS, &pcix_status);
984 pci_read_config_dword(asd_ha->pcidev, ECC_CTRL_STAT, &ecc_status);
985
986 if (status & PCI_STATUS_DETECTED_PARITY)
987 asd_printk("parity error for %s\n", pci_name(asd_ha->pcidev));
988 else if (status & PCI_STATUS_REC_MASTER_ABORT)
989 asd_printk("master abort for %s\n", pci_name(asd_ha->pcidev));
990 else if (status & PCI_STATUS_REC_TARGET_ABORT)
991 asd_printk("target abort for %s\n", pci_name(asd_ha->pcidev));
992 else if (status & PCI_STATUS_PARITY)
993 asd_printk("data parity for %s\n", pci_name(asd_ha->pcidev));
994 else if (pcix_status & RCV_SCE) {
995 asd_printk("received split completion error for %s\n",
996 pci_name(asd_ha->pcidev));
997 pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
998 /* XXX: Abort task? */
999 return;
1000 } else if (pcix_status & UNEXP_SC) {
1001 asd_printk("unexpected split completion for %s\n",
1002 pci_name(asd_ha->pcidev));
1003 pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
1004 /* ignore */
1005 return;
1006 } else if (pcix_status & SC_DISCARD)
1007 asd_printk("split completion discarded for %s\n",
1008 pci_name(asd_ha->pcidev));
1009 else if (ecc_status & UNCOR_ECCERR)
1010 asd_printk("uncorrectable ECC error for %s\n",
1011 pci_name(asd_ha->pcidev));
1012 asd_chip_reset(asd_ha);
1013 }
1014
1015 /**
1016 * asd_hw_isr -- host adapter interrupt service routine
1017 * @irq: ignored
1018 * @dev_id: pointer to host adapter structure
1019 *
1020 * The ISR processes done list entries and level 3 error handling.
1021 */
asd_hw_isr(int irq,void * dev_id)1022 irqreturn_t asd_hw_isr(int irq, void *dev_id)
1023 {
1024 struct asd_ha_struct *asd_ha = dev_id;
1025 u32 chimint = asd_read_reg_dword(asd_ha, CHIMINT);
1026
1027 if (!chimint)
1028 return IRQ_NONE;
1029
1030 asd_write_reg_dword(asd_ha, CHIMINT, chimint);
1031 (void) asd_read_reg_dword(asd_ha, CHIMINT);
1032
1033 if (chimint & DLAVAIL)
1034 asd_process_donelist_isr(asd_ha);
1035 if (chimint & COMINT)
1036 asd_com_sas_isr(asd_ha);
1037 if (chimint & DEVINT)
1038 asd_dch_sas_isr(asd_ha);
1039 if (chimint & INITERR)
1040 asd_rbi_exsi_isr(asd_ha);
1041 if (chimint & HOSTERR)
1042 asd_hst_pcix_isr(asd_ha);
1043
1044 return IRQ_HANDLED;
1045 }
1046
1047 /* ---------- SCB handling ---------- */
1048
asd_ascb_alloc(struct asd_ha_struct * asd_ha,gfp_t gfp_flags)1049 static struct asd_ascb *asd_ascb_alloc(struct asd_ha_struct *asd_ha,
1050 gfp_t gfp_flags)
1051 {
1052 extern struct kmem_cache *asd_ascb_cache;
1053 struct asd_seq_data *seq = &asd_ha->seq;
1054 struct asd_ascb *ascb;
1055 unsigned long flags;
1056
1057 ascb = kmem_cache_zalloc(asd_ascb_cache, gfp_flags);
1058
1059 if (ascb) {
1060 ascb->dma_scb.size = sizeof(struct scb);
1061 ascb->dma_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool,
1062 gfp_flags,
1063 &ascb->dma_scb.dma_handle);
1064 if (!ascb->dma_scb.vaddr) {
1065 kmem_cache_free(asd_ascb_cache, ascb);
1066 return NULL;
1067 }
1068 memset(ascb->dma_scb.vaddr, 0, sizeof(struct scb));
1069 asd_init_ascb(asd_ha, ascb);
1070
1071 spin_lock_irqsave(&seq->tc_index_lock, flags);
1072 ascb->tc_index = asd_tc_index_get(seq, ascb);
1073 spin_unlock_irqrestore(&seq->tc_index_lock, flags);
1074 if (ascb->tc_index == -1)
1075 goto undo;
1076
1077 ascb->scb->header.index = cpu_to_le16((u16)ascb->tc_index);
1078 }
1079
1080 return ascb;
1081 undo:
1082 dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
1083 ascb->dma_scb.dma_handle);
1084 kmem_cache_free(asd_ascb_cache, ascb);
1085 ASD_DPRINTK("no index for ascb\n");
1086 return NULL;
1087 }
1088
1089 /**
1090 * asd_ascb_alloc_list -- allocate a list of aSCBs
1091 * @asd_ha: pointer to host adapter structure
1092 * @num: pointer to integer number of aSCBs
1093 * @gfp_flags: GFP_ flags.
1094 *
1095 * This is the only function which is used to allocate aSCBs.
1096 * It can allocate one or many. If more than one, then they form
1097 * a linked list in two ways: by their list field of the ascb struct
1098 * and by the next_scb field of the scb_header.
1099 *
1100 * Returns NULL if no memory was available, else pointer to a list
1101 * of ascbs. When this function returns, @num would be the number
1102 * of SCBs which were not able to be allocated, 0 if all requested
1103 * were able to be allocated.
1104 */
asd_ascb_alloc_list(struct asd_ha_struct * asd_ha,int * num,gfp_t gfp_flags)1105 struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
1106 *asd_ha, int *num,
1107 gfp_t gfp_flags)
1108 {
1109 struct asd_ascb *first = NULL;
1110
1111 for ( ; *num > 0; --*num) {
1112 struct asd_ascb *ascb = asd_ascb_alloc(asd_ha, gfp_flags);
1113
1114 if (!ascb)
1115 break;
1116 else if (!first)
1117 first = ascb;
1118 else {
1119 struct asd_ascb *last = list_entry(first->list.prev,
1120 struct asd_ascb,
1121 list);
1122 list_add_tail(&ascb->list, &first->list);
1123 last->scb->header.next_scb =
1124 cpu_to_le64(((u64)ascb->dma_scb.dma_handle));
1125 }
1126 }
1127
1128 return first;
1129 }
1130
1131 /**
1132 * asd_swap_head_scb -- swap the head scb
1133 * @asd_ha: pointer to host adapter structure
1134 * @ascb: pointer to the head of an ascb list
1135 *
1136 * The sequencer knows the DMA address of the next SCB to be DMAed to
1137 * the host adapter, from initialization or from the last list DMAed.
1138 * seq->next_scb keeps the address of this SCB. The sequencer will
1139 * DMA to the host adapter this list of SCBs. But the head (first
1140 * element) of this list is not known to the sequencer. Here we swap
1141 * the head of the list with the known SCB (memcpy()).
1142 * Only one memcpy() is required per list so it is in our interest
1143 * to keep the list of SCB as long as possible so that the ratio
1144 * of number of memcpy calls to the number of SCB DMA-ed is as small
1145 * as possible.
1146 *
1147 * LOCKING: called with the pending list lock held.
1148 */
asd_swap_head_scb(struct asd_ha_struct * asd_ha,struct asd_ascb * ascb)1149 static void asd_swap_head_scb(struct asd_ha_struct *asd_ha,
1150 struct asd_ascb *ascb)
1151 {
1152 struct asd_seq_data *seq = &asd_ha->seq;
1153 struct asd_ascb *last = list_entry(ascb->list.prev,
1154 struct asd_ascb,
1155 list);
1156 struct asd_dma_tok t = ascb->dma_scb;
1157
1158 memcpy(seq->next_scb.vaddr, ascb->scb, sizeof(*ascb->scb));
1159 ascb->dma_scb = seq->next_scb;
1160 ascb->scb = ascb->dma_scb.vaddr;
1161 seq->next_scb = t;
1162 last->scb->header.next_scb =
1163 cpu_to_le64(((u64)seq->next_scb.dma_handle));
1164 }
1165
1166 /**
1167 * asd_start_timers -- (add and) start timers of SCBs
1168 * @list: pointer to struct list_head of the scbs
1169 * @to: timeout in jiffies
1170 *
1171 * If an SCB in the @list has no timer function, assign the default
1172 * one, then start the timer of the SCB. This function is
1173 * intended to be called from asd_post_ascb_list(), just prior to
1174 * posting the SCBs to the sequencer.
1175 */
asd_start_scb_timers(struct list_head * list)1176 static void asd_start_scb_timers(struct list_head *list)
1177 {
1178 struct asd_ascb *ascb;
1179 list_for_each_entry(ascb, list, list) {
1180 if (!ascb->uldd_timer) {
1181 ascb->timer.data = (unsigned long) ascb;
1182 ascb->timer.function = asd_ascb_timedout;
1183 ascb->timer.expires = jiffies + AIC94XX_SCB_TIMEOUT;
1184 add_timer(&ascb->timer);
1185 }
1186 }
1187 }
1188
1189 /**
1190 * asd_post_ascb_list -- post a list of 1 or more aSCBs to the host adapter
1191 * @asd_ha: pointer to a host adapter structure
1192 * @ascb: pointer to the first aSCB in the list
1193 * @num: number of aSCBs in the list (to be posted)
1194 *
1195 * See queueing comment in asd_post_escb_list().
1196 *
1197 * Additional note on queuing: In order to minimize the ratio of memcpy()
1198 * to the number of ascbs sent, we try to batch-send as many ascbs as possible
1199 * in one go.
1200 * Two cases are possible:
1201 * A) can_queue >= num,
1202 * B) can_queue < num.
1203 * Case A: we can send the whole batch at once. Increment "pending"
1204 * in the beginning of this function, when it is checked, in order to
1205 * eliminate races when this function is called by multiple processes.
1206 * Case B: should never happen.
1207 */
asd_post_ascb_list(struct asd_ha_struct * asd_ha,struct asd_ascb * ascb,int num)1208 int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1209 int num)
1210 {
1211 unsigned long flags;
1212 LIST_HEAD(list);
1213 int can_queue;
1214
1215 spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1216 can_queue = asd_ha->hw_prof.max_scbs - asd_ha->seq.pending;
1217 if (can_queue >= num)
1218 asd_ha->seq.pending += num;
1219 else
1220 can_queue = 0;
1221
1222 if (!can_queue) {
1223 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1224 asd_printk("%s: scb queue full\n", pci_name(asd_ha->pcidev));
1225 return -SAS_QUEUE_FULL;
1226 }
1227
1228 asd_swap_head_scb(asd_ha, ascb);
1229
1230 __list_add(&list, ascb->list.prev, &ascb->list);
1231
1232 asd_start_scb_timers(&list);
1233
1234 asd_ha->seq.scbpro += num;
1235 list_splice_init(&list, asd_ha->seq.pend_q.prev);
1236 asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1237 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1238
1239 return 0;
1240 }
1241
1242 /**
1243 * asd_post_escb_list -- post a list of 1 or more empty scb
1244 * @asd_ha: pointer to a host adapter structure
1245 * @ascb: pointer to the first empty SCB in the list
1246 * @num: number of aSCBs in the list (to be posted)
1247 *
1248 * This is essentially the same as asd_post_ascb_list, but we do not
1249 * increment pending, add those to the pending list or get indexes.
1250 * See asd_init_escbs() and asd_init_post_escbs().
1251 *
1252 * Since sending a list of ascbs is a superset of sending a single
1253 * ascb, this function exists to generalize this. More specifically,
1254 * when sending a list of those, we want to do only a _single_
1255 * memcpy() at swap head, as opposed to for each ascb sent (in the
1256 * case of sending them one by one). That is, we want to minimize the
1257 * ratio of memcpy() operations to the number of ascbs sent. The same
1258 * logic applies to asd_post_ascb_list().
1259 */
asd_post_escb_list(struct asd_ha_struct * asd_ha,struct asd_ascb * ascb,int num)1260 int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1261 int num)
1262 {
1263 unsigned long flags;
1264
1265 spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1266 asd_swap_head_scb(asd_ha, ascb);
1267 asd_ha->seq.scbpro += num;
1268 asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1269 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1270
1271 return 0;
1272 }
1273
1274 /* ---------- LED ---------- */
1275
1276 /**
1277 * asd_turn_led -- turn on/off an LED
1278 * @asd_ha: pointer to host adapter structure
1279 * @phy_id: the PHY id whose LED we want to manupulate
1280 * @op: 1 to turn on, 0 to turn off
1281 */
asd_turn_led(struct asd_ha_struct * asd_ha,int phy_id,int op)1282 void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1283 {
1284 if (phy_id < ASD_MAX_PHYS) {
1285 u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id));
1286 if (op)
1287 v |= LEDPOL;
1288 else
1289 v &= ~LEDPOL;
1290 asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v);
1291 }
1292 }
1293
1294 /**
1295 * asd_control_led -- enable/disable an LED on the board
1296 * @asd_ha: pointer to host adapter structure
1297 * @phy_id: integer, the phy id
1298 * @op: integer, 1 to enable, 0 to disable the LED
1299 *
1300 * First we output enable the LED, then we set the source
1301 * to be an external module.
1302 */
asd_control_led(struct asd_ha_struct * asd_ha,int phy_id,int op)1303 void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1304 {
1305 if (phy_id < ASD_MAX_PHYS) {
1306 u32 v;
1307
1308 v = asd_read_reg_dword(asd_ha, GPIOOER);
1309 if (op)
1310 v |= (1 << phy_id);
1311 else
1312 v &= ~(1 << phy_id);
1313 asd_write_reg_dword(asd_ha, GPIOOER, v);
1314
1315 v = asd_read_reg_dword(asd_ha, GPIOCNFGR);
1316 if (op)
1317 v |= (1 << phy_id);
1318 else
1319 v &= ~(1 << phy_id);
1320 asd_write_reg_dword(asd_ha, GPIOCNFGR, v);
1321 }
1322 }
1323
1324 /* ---------- PHY enable ---------- */
1325
asd_enable_phy(struct asd_ha_struct * asd_ha,int phy_id)1326 static int asd_enable_phy(struct asd_ha_struct *asd_ha, int phy_id)
1327 {
1328 struct asd_phy *phy = &asd_ha->phys[phy_id];
1329
1330 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0);
1331 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY),
1332 HOTPLUG_DELAY_TIMEOUT);
1333
1334 /* Get defaults from manuf. sector */
1335 /* XXX we need defaults for those in case MS is broken. */
1336 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0),
1337 phy->phy_desc->phy_control_0);
1338 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1),
1339 phy->phy_desc->phy_control_1);
1340 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2),
1341 phy->phy_desc->phy_control_2);
1342 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3),
1343 phy->phy_desc->phy_control_3);
1344
1345 asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(phy_id),
1346 ASD_COMINIT_TIMEOUT);
1347
1348 asd_write_reg_addr(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(phy_id),
1349 phy->id_frm_tok->dma_handle);
1350
1351 asd_control_led(asd_ha, phy_id, 1);
1352
1353 return 0;
1354 }
1355
asd_enable_phys(struct asd_ha_struct * asd_ha,const u8 phy_mask)1356 int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask)
1357 {
1358 u8 phy_m;
1359 u8 i;
1360 int num = 0, k;
1361 struct asd_ascb *ascb;
1362 struct asd_ascb *ascb_list;
1363
1364 if (!phy_mask) {
1365 asd_printk("%s called with phy_mask of 0!?\n", __func__);
1366 return 0;
1367 }
1368
1369 for_each_phy(phy_mask, phy_m, i) {
1370 num++;
1371 asd_enable_phy(asd_ha, i);
1372 }
1373
1374 k = num;
1375 ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL);
1376 if (!ascb_list) {
1377 asd_printk("no memory for control phy ascb list\n");
1378 return -ENOMEM;
1379 }
1380 num -= k;
1381
1382 ascb = ascb_list;
1383 for_each_phy(phy_mask, phy_m, i) {
1384 asd_build_control_phy(ascb, i, ENABLE_PHY);
1385 ascb = list_entry(ascb->list.next, struct asd_ascb, list);
1386 }
1387 ASD_DPRINTK("posting %d control phy scbs\n", num);
1388 k = asd_post_ascb_list(asd_ha, ascb_list, num);
1389 if (k)
1390 asd_ascb_free_list(ascb_list);
1391
1392 return k;
1393 }
1394