1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <linux/etherdevice.h>
23 #include <linux/gpio.h>
24 #include <asm/unaligned.h>
25
26 #include "hw.h"
27 #include "hw-ops.h"
28 #include "ar9003_mac.h"
29 #include "ar9003_mci.h"
30 #include "ar9003_phy.h"
31 #include "ath9k.h"
32
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
ath9k_hw_set_clockrate(struct ath_hw * ah)40 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
41 {
42 struct ath_common *common = ath9k_hw_common(ah);
43 struct ath9k_channel *chan = ah->curchan;
44 unsigned int clockrate;
45
46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
49 else if (!chan) /* should really check for CCK instead */
50 clockrate = ATH9K_CLOCK_RATE_CCK;
51 else if (IS_CHAN_2GHZ(chan))
52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
55 else
56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
61 if (IS_CHAN_HALF_RATE(chan))
62 clockrate /= 2;
63 if (IS_CHAN_QUARTER_RATE(chan))
64 clockrate /= 4;
65 }
66
67 common->clockrate = clockrate;
68 }
69
ath9k_hw_mac_to_clks(struct ath_hw * ah,u32 usecs)70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
71 {
72 struct ath_common *common = ath9k_hw_common(ah);
73
74 return usecs * common->clockrate;
75 }
76
ath9k_hw_wait(struct ath_hw * ah,u32 reg,u32 mask,u32 val,u32 timeout)77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
78 {
79 int i;
80
81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
89
90 ath_dbg(ath9k_hw_common(ah), ANY,
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
93
94 return false;
95 }
96 EXPORT_SYMBOL(ath9k_hw_wait);
97
ath9k_hw_synth_delay(struct ath_hw * ah,struct ath9k_channel * chan,int hw_delay)98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100 {
101 hw_delay /= 10;
102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109 }
110
ath9k_hw_write_array(struct ath_hw * ah,const struct ar5416IniArray * array,int column,unsigned int * writecnt)111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
112 int column, unsigned int *writecnt)
113 {
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123 }
124
ath9k_hw_read_array(struct ath_hw * ah,u32 array[][2],int size)125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126 {
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151 error_tmp_data:
152 kfree(tmp_reg_list);
153 }
154
ath9k_hw_reverse_bits(u32 val,u32 n)155 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156 {
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165 }
166
ath9k_hw_computetxtime(struct ath_hw * ah,u8 phy,int kbps,u32 frameLen,u16 rateix,bool shortPreamble)167 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
168 u8 phy, int kbps,
169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
171 {
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
173
174 if (kbps == 0)
175 return 0;
176
177 switch (phy) {
178 case WLAN_RC_PHY_CCK:
179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
180 if (shortPreamble)
181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
185 case WLAN_RC_PHY_OFDM:
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
212 txTime = 0;
213 break;
214 }
215
216 return txTime;
217 }
218 EXPORT_SYMBOL(ath9k_hw_computetxtime);
219
ath9k_hw_get_channel_centers(struct ath_hw * ah,struct ath9k_channel * chan,struct chan_centers * centers)220 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
223 {
224 int8_t extoff;
225
226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
230 }
231
232 if (IS_CHAN_HT40PLUS(chan)) {
233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
241
242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
244 /* 25 MHz spacing is supported by hw but not on upper layers */
245 centers->ext_center =
246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 }
248
249 /******************/
250 /* Chip Revisions */
251 /******************/
252
ath9k_hw_read_revisions(struct ath_hw * ah)253 static bool ath9k_hw_read_revisions(struct ath_hw *ah)
254 {
255 u32 srev;
256 u32 val;
257
258 if (ah->get_mac_revision)
259 ah->hw_version.macRev = ah->get_mac_revision();
260
261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 break;
265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
267 if (!ah->get_mac_revision) {
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
270 }
271 return true;
272 case AR9300_DEVID_AR9340:
273 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
274 return true;
275 case AR9300_DEVID_QCA955X:
276 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
277 return true;
278 case AR9300_DEVID_AR953X:
279 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
280 return true;
281 case AR9300_DEVID_QCA956X:
282 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
283 return true;
284 }
285
286 srev = REG_READ(ah, AR_SREV);
287
288 if (srev == -EIO) {
289 ath_err(ath9k_hw_common(ah),
290 "Failed to read SREV register");
291 return false;
292 }
293
294 val = srev & AR_SREV_ID;
295
296 if (val == 0xFF) {
297 val = srev;
298 ah->hw_version.macVersion =
299 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
300 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
301
302 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
303 ah->is_pciexpress = true;
304 else
305 ah->is_pciexpress = (val &
306 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
307 } else {
308 if (!AR_SREV_9100(ah))
309 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
310
311 ah->hw_version.macRev = val & AR_SREV_REVISION;
312
313 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
314 ah->is_pciexpress = true;
315 }
316
317 return true;
318 }
319
320 /************************************/
321 /* HW Attach, Detach, Init Routines */
322 /************************************/
323
ath9k_hw_disablepcie(struct ath_hw * ah)324 static void ath9k_hw_disablepcie(struct ath_hw *ah)
325 {
326 if (!AR_SREV_5416(ah))
327 return;
328
329 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
336 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
338
339 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
340 }
341
342 /* This should work for all families including legacy */
ath9k_hw_chip_test(struct ath_hw * ah)343 static bool ath9k_hw_chip_test(struct ath_hw *ah)
344 {
345 struct ath_common *common = ath9k_hw_common(ah);
346 u32 regAddr[2] = { AR_STA_ID0 };
347 u32 regHold[2];
348 static const u32 patternData[4] = {
349 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
350 };
351 int i, j, loop_max;
352
353 if (!AR_SREV_9300_20_OR_LATER(ah)) {
354 loop_max = 2;
355 regAddr[1] = AR_PHY_BASE + (8 << 2);
356 } else
357 loop_max = 1;
358
359 for (i = 0; i < loop_max; i++) {
360 u32 addr = regAddr[i];
361 u32 wrData, rdData;
362
363 regHold[i] = REG_READ(ah, addr);
364 for (j = 0; j < 0x100; j++) {
365 wrData = (j << 16) | j;
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (rdData != wrData) {
369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
372 return false;
373 }
374 }
375 for (j = 0; j < 4; j++) {
376 wrData = patternData[j];
377 REG_WRITE(ah, addr, wrData);
378 rdData = REG_READ(ah, addr);
379 if (wrData != rdData) {
380 ath_err(common,
381 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
382 addr, wrData, rdData);
383 return false;
384 }
385 }
386 REG_WRITE(ah, regAddr[i], regHold[i]);
387 }
388 udelay(100);
389
390 return true;
391 }
392
ath9k_hw_init_config(struct ath_hw * ah)393 static void ath9k_hw_init_config(struct ath_hw *ah)
394 {
395 struct ath_common *common = ath9k_hw_common(ah);
396
397 ah->config.dma_beacon_response_time = 1;
398 ah->config.sw_beacon_response_time = 6;
399 ah->config.cwm_ignore_extcca = false;
400 ah->config.analog_shiftreg = 1;
401
402 ah->config.rx_intr_mitigation = true;
403
404 if (AR_SREV_9300_20_OR_LATER(ah)) {
405 ah->config.rimt_last = 500;
406 ah->config.rimt_first = 2000;
407 } else {
408 ah->config.rimt_last = 250;
409 ah->config.rimt_first = 700;
410 }
411
412 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
413 ah->config.pll_pwrsave = 7;
414
415 /*
416 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
417 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
418 * This means we use it for all AR5416 devices, and the few
419 * minor PCI AR9280 devices out there.
420 *
421 * Serialization is required because these devices do not handle
422 * well the case of two concurrent reads/writes due to the latency
423 * involved. During one read/write another read/write can be issued
424 * on another CPU while the previous read/write may still be working
425 * on our hardware, if we hit this case the hardware poops in a loop.
426 * We prevent this by serializing reads and writes.
427 *
428 * This issue is not present on PCI-Express devices or pre-AR5416
429 * devices (legacy, 802.11abg).
430 */
431 if (num_possible_cpus() > 1)
432 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
433
434 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
435 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
436 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
437 !ah->is_pciexpress)) {
438 ah->config.serialize_regmode = SER_REG_MODE_ON;
439 } else {
440 ah->config.serialize_regmode = SER_REG_MODE_OFF;
441 }
442 }
443
444 ath_dbg(common, RESET, "serialize_regmode is %d\n",
445 ah->config.serialize_regmode);
446
447 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
448 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
449 else
450 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
451 }
452
ath9k_hw_init_defaults(struct ath_hw * ah)453 static void ath9k_hw_init_defaults(struct ath_hw *ah)
454 {
455 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
456
457 regulatory->country_code = CTRY_DEFAULT;
458 regulatory->power_limit = MAX_RATE_POWER;
459
460 ah->hw_version.magic = AR5416_MAGIC;
461 ah->hw_version.subvendorid = 0;
462
463 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
464 AR_STA_ID1_MCAST_KSRCH;
465 if (AR_SREV_9100(ah))
466 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
467
468 ah->slottime = 9;
469 ah->globaltxtimeout = (u32) -1;
470 ah->power_mode = ATH9K_PM_UNDEFINED;
471 ah->htc_reset_init = true;
472
473 ah->tpc_enabled = false;
474
475 ah->ani_function = ATH9K_ANI_ALL;
476 if (!AR_SREV_9300_20_OR_LATER(ah))
477 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
478
479 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
480 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
481 else
482 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
483 }
484
ath9k_hw_init_macaddr(struct ath_hw * ah)485 static void ath9k_hw_init_macaddr(struct ath_hw *ah)
486 {
487 struct ath_common *common = ath9k_hw_common(ah);
488 int i;
489 u16 eeval;
490 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
491
492 /* MAC address may already be loaded via ath9k_platform_data */
493 if (is_valid_ether_addr(common->macaddr))
494 return;
495
496 for (i = 0; i < 3; i++) {
497 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
498 common->macaddr[2 * i] = eeval >> 8;
499 common->macaddr[2 * i + 1] = eeval & 0xff;
500 }
501
502 if (is_valid_ether_addr(common->macaddr))
503 return;
504
505 ath_err(common, "eeprom contains invalid mac address: %pM\n",
506 common->macaddr);
507
508 random_ether_addr(common->macaddr);
509 ath_err(common, "random mac address will be used: %pM\n",
510 common->macaddr);
511
512 return;
513 }
514
ath9k_hw_post_init(struct ath_hw * ah)515 static int ath9k_hw_post_init(struct ath_hw *ah)
516 {
517 struct ath_common *common = ath9k_hw_common(ah);
518 int ecode;
519
520 if (common->bus_ops->ath_bus_type != ATH_USB) {
521 if (!ath9k_hw_chip_test(ah))
522 return -ENODEV;
523 }
524
525 if (!AR_SREV_9300_20_OR_LATER(ah)) {
526 ecode = ar9002_hw_rf_claim(ah);
527 if (ecode != 0)
528 return ecode;
529 }
530
531 ecode = ath9k_hw_eeprom_init(ah);
532 if (ecode != 0)
533 return ecode;
534
535 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
536 ah->eep_ops->get_eeprom_ver(ah),
537 ah->eep_ops->get_eeprom_rev(ah));
538
539 ath9k_hw_ani_init(ah);
540
541 /*
542 * EEPROM needs to be initialized before we do this.
543 * This is required for regulatory compliance.
544 */
545 if (AR_SREV_9300_20_OR_LATER(ah)) {
546 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
547 if ((regdmn & 0xF0) == CTL_FCC) {
548 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
549 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
550 }
551 }
552
553 return 0;
554 }
555
ath9k_hw_attach_ops(struct ath_hw * ah)556 static int ath9k_hw_attach_ops(struct ath_hw *ah)
557 {
558 if (!AR_SREV_9300_20_OR_LATER(ah))
559 return ar9002_hw_attach_ops(ah);
560
561 ar9003_hw_attach_ops(ah);
562 return 0;
563 }
564
565 /* Called for all hardware families */
__ath9k_hw_init(struct ath_hw * ah)566 static int __ath9k_hw_init(struct ath_hw *ah)
567 {
568 struct ath_common *common = ath9k_hw_common(ah);
569 int r = 0;
570
571 if (!ath9k_hw_read_revisions(ah)) {
572 ath_err(common, "Could not read hardware revisions");
573 return -EOPNOTSUPP;
574 }
575
576 switch (ah->hw_version.macVersion) {
577 case AR_SREV_VERSION_5416_PCI:
578 case AR_SREV_VERSION_5416_PCIE:
579 case AR_SREV_VERSION_9160:
580 case AR_SREV_VERSION_9100:
581 case AR_SREV_VERSION_9280:
582 case AR_SREV_VERSION_9285:
583 case AR_SREV_VERSION_9287:
584 case AR_SREV_VERSION_9271:
585 case AR_SREV_VERSION_9300:
586 case AR_SREV_VERSION_9330:
587 case AR_SREV_VERSION_9485:
588 case AR_SREV_VERSION_9340:
589 case AR_SREV_VERSION_9462:
590 case AR_SREV_VERSION_9550:
591 case AR_SREV_VERSION_9565:
592 case AR_SREV_VERSION_9531:
593 case AR_SREV_VERSION_9561:
594 break;
595 default:
596 ath_err(common,
597 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
598 ah->hw_version.macVersion, ah->hw_version.macRev);
599 return -EOPNOTSUPP;
600 }
601
602 /*
603 * Read back AR_WA into a permanent copy and set bits 14 and 17.
604 * We need to do this to avoid RMW of this register. We cannot
605 * read the reg when chip is asleep.
606 */
607 if (AR_SREV_9300_20_OR_LATER(ah)) {
608 ah->WARegVal = REG_READ(ah, AR_WA);
609 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
610 AR_WA_ASPM_TIMER_BASED_DISABLE);
611 }
612
613 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
614 ath_err(common, "Couldn't reset chip\n");
615 return -EIO;
616 }
617
618 if (AR_SREV_9565(ah)) {
619 ah->WARegVal |= AR_WA_BIT22;
620 REG_WRITE(ah, AR_WA, ah->WARegVal);
621 }
622
623 ath9k_hw_init_defaults(ah);
624 ath9k_hw_init_config(ah);
625
626 r = ath9k_hw_attach_ops(ah);
627 if (r)
628 return r;
629
630 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
631 ath_err(common, "Couldn't wakeup chip\n");
632 return -EIO;
633 }
634
635 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
636 AR_SREV_9330(ah) || AR_SREV_9550(ah))
637 ah->is_pciexpress = false;
638
639 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
640 ath9k_hw_init_cal_settings(ah);
641
642 if (!ah->is_pciexpress)
643 ath9k_hw_disablepcie(ah);
644
645 r = ath9k_hw_post_init(ah);
646 if (r)
647 return r;
648
649 ath9k_hw_init_mode_gain_regs(ah);
650 r = ath9k_hw_fill_cap_info(ah);
651 if (r)
652 return r;
653
654 ath9k_hw_init_macaddr(ah);
655 ath9k_hw_init_hang_checks(ah);
656
657 common->state = ATH_HW_INITIALIZED;
658
659 return 0;
660 }
661
ath9k_hw_init(struct ath_hw * ah)662 int ath9k_hw_init(struct ath_hw *ah)
663 {
664 int ret;
665 struct ath_common *common = ath9k_hw_common(ah);
666
667 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
668 switch (ah->hw_version.devid) {
669 case AR5416_DEVID_PCI:
670 case AR5416_DEVID_PCIE:
671 case AR5416_AR9100_DEVID:
672 case AR9160_DEVID_PCI:
673 case AR9280_DEVID_PCI:
674 case AR9280_DEVID_PCIE:
675 case AR9285_DEVID_PCIE:
676 case AR9287_DEVID_PCI:
677 case AR9287_DEVID_PCIE:
678 case AR2427_DEVID_PCIE:
679 case AR9300_DEVID_PCIE:
680 case AR9300_DEVID_AR9485_PCIE:
681 case AR9300_DEVID_AR9330:
682 case AR9300_DEVID_AR9340:
683 case AR9300_DEVID_QCA955X:
684 case AR9300_DEVID_AR9580:
685 case AR9300_DEVID_AR9462:
686 case AR9485_DEVID_AR1111:
687 case AR9300_DEVID_AR9565:
688 case AR9300_DEVID_AR953X:
689 case AR9300_DEVID_QCA956X:
690 break;
691 default:
692 if (common->bus_ops->ath_bus_type == ATH_USB)
693 break;
694 ath_err(common, "Hardware device ID 0x%04x not supported\n",
695 ah->hw_version.devid);
696 return -EOPNOTSUPP;
697 }
698
699 ret = __ath9k_hw_init(ah);
700 if (ret) {
701 ath_err(common,
702 "Unable to initialize hardware; initialization status: %d\n",
703 ret);
704 return ret;
705 }
706
707 ath_dynack_init(ah);
708
709 return 0;
710 }
711 EXPORT_SYMBOL(ath9k_hw_init);
712
ath9k_hw_init_qos(struct ath_hw * ah)713 static void ath9k_hw_init_qos(struct ath_hw *ah)
714 {
715 ENABLE_REGWRITE_BUFFER(ah);
716
717 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
718 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
719
720 REG_WRITE(ah, AR_QOS_NO_ACK,
721 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
722 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
723 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
724
725 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
726 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
727 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
728 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
729 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
730
731 REGWRITE_BUFFER_FLUSH(ah);
732 }
733
ar9003_get_pll_sqsum_dvc(struct ath_hw * ah)734 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
735 {
736 struct ath_common *common = ath9k_hw_common(ah);
737 int i = 0;
738
739 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
740 udelay(100);
741 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
742
743 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
744
745 udelay(100);
746
747 if (WARN_ON_ONCE(i >= 100)) {
748 ath_err(common, "PLL4 measurement not done\n");
749 break;
750 }
751
752 i++;
753 }
754
755 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
756 }
757 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
758
ath9k_hw_init_pll(struct ath_hw * ah,struct ath9k_channel * chan)759 static void ath9k_hw_init_pll(struct ath_hw *ah,
760 struct ath9k_channel *chan)
761 {
762 u32 pll;
763
764 pll = ath9k_hw_compute_pll_control(ah, chan);
765
766 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
767 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
769 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 AR_CH0_DPLL2_KD, 0x40);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_DPLL2_KI, 0x4);
774
775 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
776 AR_CH0_BB_DPLL1_REFDIV, 0x5);
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
778 AR_CH0_BB_DPLL1_NINI, 0x58);
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
780 AR_CH0_BB_DPLL1_NFRAC, 0x0);
781
782 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
783 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
785 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
787 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
788
789 /* program BB PLL phase_shift to 0x6 */
790 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
791 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
792
793 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
794 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
795 udelay(1000);
796 } else if (AR_SREV_9330(ah)) {
797 u32 ddr_dpll2, pll_control2, kd;
798
799 if (ah->is_clk_25mhz) {
800 ddr_dpll2 = 0x18e82f01;
801 pll_control2 = 0xe04a3d;
802 kd = 0x1d;
803 } else {
804 ddr_dpll2 = 0x19e82f01;
805 pll_control2 = 0x886666;
806 kd = 0x3d;
807 }
808
809 /* program DDR PLL ki and kd value */
810 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
811
812 /* program DDR PLL phase_shift */
813 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
814 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
815
816 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
817 pll | AR_RTC_9300_PLL_BYPASS);
818 udelay(1000);
819
820 /* program refdiv, nint, frac to RTC register */
821 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
822
823 /* program BB PLL kd and ki value */
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
826
827 /* program BB PLL phase_shift */
828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
829 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
830 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
831 AR_SREV_9561(ah)) {
832 u32 regval, pll2_divint, pll2_divfrac, refdiv;
833
834 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
835 pll | AR_RTC_9300_SOC_PLL_BYPASS);
836 udelay(1000);
837
838 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
839 udelay(100);
840
841 if (ah->is_clk_25mhz) {
842 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
843 pll2_divint = 0x1c;
844 pll2_divfrac = 0xa3d2;
845 refdiv = 1;
846 } else {
847 pll2_divint = 0x54;
848 pll2_divfrac = 0x1eb85;
849 refdiv = 3;
850 }
851 } else {
852 if (AR_SREV_9340(ah)) {
853 pll2_divint = 88;
854 pll2_divfrac = 0;
855 refdiv = 5;
856 } else {
857 pll2_divint = 0x11;
858 pll2_divfrac = (AR_SREV_9531(ah) ||
859 AR_SREV_9561(ah)) ?
860 0x26665 : 0x26666;
861 refdiv = 1;
862 }
863 }
864
865 regval = REG_READ(ah, AR_PHY_PLL_MODE);
866 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
867 regval |= (0x1 << 22);
868 else
869 regval |= (0x1 << 16);
870 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
871 udelay(100);
872
873 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
874 (pll2_divint << 18) | pll2_divfrac);
875 udelay(100);
876
877 regval = REG_READ(ah, AR_PHY_PLL_MODE);
878 if (AR_SREV_9340(ah))
879 regval = (regval & 0x80071fff) |
880 (0x1 << 30) |
881 (0x1 << 13) |
882 (0x4 << 26) |
883 (0x18 << 19);
884 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
885 regval = (regval & 0x01c00fff) |
886 (0x1 << 31) |
887 (0x2 << 29) |
888 (0xa << 25) |
889 (0x1 << 19);
890
891 if (AR_SREV_9531(ah))
892 regval |= (0x6 << 12);
893 } else
894 regval = (regval & 0x80071fff) |
895 (0x3 << 30) |
896 (0x1 << 13) |
897 (0x4 << 26) |
898 (0x60 << 19);
899 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
900
901 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
902 REG_WRITE(ah, AR_PHY_PLL_MODE,
903 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
904 else
905 REG_WRITE(ah, AR_PHY_PLL_MODE,
906 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
907
908 udelay(1000);
909 }
910
911 if (AR_SREV_9565(ah))
912 pll |= 0x40000;
913 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
914
915 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
916 AR_SREV_9550(ah))
917 udelay(1000);
918
919 /* Switch the core clock for ar9271 to 117Mhz */
920 if (AR_SREV_9271(ah)) {
921 udelay(500);
922 REG_WRITE(ah, 0x50040, 0x304);
923 }
924
925 udelay(RTC_PLL_SETTLE_DELAY);
926
927 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
928 }
929
ath9k_hw_init_interrupt_masks(struct ath_hw * ah,enum nl80211_iftype opmode)930 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
931 enum nl80211_iftype opmode)
932 {
933 u32 sync_default = AR_INTR_SYNC_DEFAULT;
934 u32 imr_reg = AR_IMR_TXERR |
935 AR_IMR_TXURN |
936 AR_IMR_RXERR |
937 AR_IMR_RXORN |
938 AR_IMR_BCNMISC;
939
940 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
941 AR_SREV_9561(ah))
942 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
943
944 if (AR_SREV_9300_20_OR_LATER(ah)) {
945 imr_reg |= AR_IMR_RXOK_HP;
946 if (ah->config.rx_intr_mitigation)
947 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
948 else
949 imr_reg |= AR_IMR_RXOK_LP;
950
951 } else {
952 if (ah->config.rx_intr_mitigation)
953 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
954 else
955 imr_reg |= AR_IMR_RXOK;
956 }
957
958 if (ah->config.tx_intr_mitigation)
959 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
960 else
961 imr_reg |= AR_IMR_TXOK;
962
963 ENABLE_REGWRITE_BUFFER(ah);
964
965 REG_WRITE(ah, AR_IMR, imr_reg);
966 ah->imrs2_reg |= AR_IMR_S2_GTT;
967 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
968
969 if (!AR_SREV_9100(ah)) {
970 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
971 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
972 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
973 }
974
975 REGWRITE_BUFFER_FLUSH(ah);
976
977 if (AR_SREV_9300_20_OR_LATER(ah)) {
978 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
979 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
980 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
981 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
982 }
983 }
984
ath9k_hw_set_sifs_time(struct ath_hw * ah,u32 us)985 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
986 {
987 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
988 val = min(val, (u32) 0xFFFF);
989 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
990 }
991
ath9k_hw_setslottime(struct ath_hw * ah,u32 us)992 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
993 {
994 u32 val = ath9k_hw_mac_to_clks(ah, us);
995 val = min(val, (u32) 0xFFFF);
996 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
997 }
998
ath9k_hw_set_ack_timeout(struct ath_hw * ah,u32 us)999 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1000 {
1001 u32 val = ath9k_hw_mac_to_clks(ah, us);
1002 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1003 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1004 }
1005
ath9k_hw_set_cts_timeout(struct ath_hw * ah,u32 us)1006 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1007 {
1008 u32 val = ath9k_hw_mac_to_clks(ah, us);
1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1011 }
1012
ath9k_hw_set_global_txtimeout(struct ath_hw * ah,u32 tu)1013 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1014 {
1015 if (tu > 0xFFFF) {
1016 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1017 tu);
1018 ah->globaltxtimeout = (u32) -1;
1019 return false;
1020 } else {
1021 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1022 ah->globaltxtimeout = tu;
1023 return true;
1024 }
1025 }
1026
ath9k_hw_init_global_settings(struct ath_hw * ah)1027 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1028 {
1029 struct ath_common *common = ath9k_hw_common(ah);
1030 const struct ath9k_channel *chan = ah->curchan;
1031 int acktimeout, ctstimeout, ack_offset = 0;
1032 int slottime;
1033 int sifstime;
1034 int rx_lat = 0, tx_lat = 0, eifs = 0;
1035 u32 reg;
1036
1037 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1038 ah->misc_mode);
1039
1040 if (!chan)
1041 return;
1042
1043 if (ah->misc_mode != 0)
1044 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1045
1046 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1047 rx_lat = 41;
1048 else
1049 rx_lat = 37;
1050 tx_lat = 54;
1051
1052 if (IS_CHAN_5GHZ(chan))
1053 sifstime = 16;
1054 else
1055 sifstime = 10;
1056
1057 if (IS_CHAN_HALF_RATE(chan)) {
1058 eifs = 175;
1059 rx_lat *= 2;
1060 tx_lat *= 2;
1061 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1062 tx_lat += 11;
1063
1064 sifstime = 32;
1065 ack_offset = 16;
1066 slottime = 13;
1067 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1068 eifs = 340;
1069 rx_lat = (rx_lat * 4) - 1;
1070 tx_lat *= 4;
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 tx_lat += 22;
1073
1074 sifstime = 64;
1075 ack_offset = 32;
1076 slottime = 21;
1077 } else {
1078 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1079 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1080 reg = AR_USEC_ASYNC_FIFO;
1081 } else {
1082 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1083 common->clockrate;
1084 reg = REG_READ(ah, AR_USEC);
1085 }
1086 rx_lat = MS(reg, AR_USEC_RX_LAT);
1087 tx_lat = MS(reg, AR_USEC_TX_LAT);
1088
1089 slottime = ah->slottime;
1090 }
1091
1092 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1093 slottime += 3 * ah->coverage_class;
1094 acktimeout = slottime + sifstime + ack_offset;
1095 ctstimeout = acktimeout;
1096
1097 /*
1098 * Workaround for early ACK timeouts, add an offset to match the
1099 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1100 * This was initially only meant to work around an issue with delayed
1101 * BA frames in some implementations, but it has been found to fix ACK
1102 * timeout issues in other cases as well.
1103 */
1104 if (IS_CHAN_2GHZ(chan) &&
1105 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1106 acktimeout += 64 - sifstime - ah->slottime;
1107 ctstimeout += 48 - sifstime - ah->slottime;
1108 }
1109
1110 if (ah->dynack.enabled) {
1111 acktimeout = ah->dynack.ackto;
1112 ctstimeout = acktimeout;
1113 slottime = (acktimeout - 3) / 2;
1114 } else {
1115 ah->dynack.ackto = acktimeout;
1116 }
1117
1118 ath9k_hw_set_sifs_time(ah, sifstime);
1119 ath9k_hw_setslottime(ah, slottime);
1120 ath9k_hw_set_ack_timeout(ah, acktimeout);
1121 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1122 if (ah->globaltxtimeout != (u32) -1)
1123 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1124
1125 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1126 REG_RMW(ah, AR_USEC,
1127 (common->clockrate - 1) |
1128 SM(rx_lat, AR_USEC_RX_LAT) |
1129 SM(tx_lat, AR_USEC_TX_LAT),
1130 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1131
1132 }
1133 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1134
ath9k_hw_deinit(struct ath_hw * ah)1135 void ath9k_hw_deinit(struct ath_hw *ah)
1136 {
1137 struct ath_common *common = ath9k_hw_common(ah);
1138
1139 if (common->state < ATH_HW_INITIALIZED)
1140 return;
1141
1142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1143 }
1144 EXPORT_SYMBOL(ath9k_hw_deinit);
1145
1146 /*******/
1147 /* INI */
1148 /*******/
1149
ath9k_regd_get_ctl(struct ath_regulatory * reg,struct ath9k_channel * chan)1150 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1151 {
1152 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1153
1154 if (IS_CHAN_2GHZ(chan))
1155 ctl |= CTL_11G;
1156 else
1157 ctl |= CTL_11A;
1158
1159 return ctl;
1160 }
1161
1162 /****************************************/
1163 /* Reset and Channel Switching Routines */
1164 /****************************************/
1165
ath9k_hw_set_dma(struct ath_hw * ah)1166 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1167 {
1168 struct ath_common *common = ath9k_hw_common(ah);
1169 int txbuf_size;
1170
1171 ENABLE_REGWRITE_BUFFER(ah);
1172
1173 /*
1174 * set AHB_MODE not to do cacheline prefetches
1175 */
1176 if (!AR_SREV_9300_20_OR_LATER(ah))
1177 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1178
1179 /*
1180 * let mac dma reads be in 128 byte chunks
1181 */
1182 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1183
1184 REGWRITE_BUFFER_FLUSH(ah);
1185
1186 /*
1187 * Restore TX Trigger Level to its pre-reset value.
1188 * The initial value depends on whether aggregation is enabled, and is
1189 * adjusted whenever underruns are detected.
1190 */
1191 if (!AR_SREV_9300_20_OR_LATER(ah))
1192 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1193
1194 ENABLE_REGWRITE_BUFFER(ah);
1195
1196 /*
1197 * let mac dma writes be in 128 byte chunks
1198 */
1199 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1200
1201 /*
1202 * Setup receive FIFO threshold to hold off TX activities
1203 */
1204 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1205
1206 if (AR_SREV_9300_20_OR_LATER(ah)) {
1207 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1208 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1209
1210 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1211 ah->caps.rx_status_len);
1212 }
1213
1214 /*
1215 * reduce the number of usable entries in PCU TXBUF to avoid
1216 * wrap around issues.
1217 */
1218 if (AR_SREV_9285(ah)) {
1219 /* For AR9285 the number of Fifos are reduced to half.
1220 * So set the usable tx buf size also to half to
1221 * avoid data/delimiter underruns
1222 */
1223 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1224 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1225 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1226 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1227 } else {
1228 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1229 }
1230
1231 if (!AR_SREV_9271(ah))
1232 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1233
1234 REGWRITE_BUFFER_FLUSH(ah);
1235
1236 if (AR_SREV_9300_20_OR_LATER(ah))
1237 ath9k_hw_reset_txstatus_ring(ah);
1238 }
1239
ath9k_hw_set_operating_mode(struct ath_hw * ah,int opmode)1240 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1241 {
1242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1243 u32 set = AR_STA_ID1_KSRCH_MODE;
1244
1245 ENABLE_REG_RMW_BUFFER(ah);
1246 switch (opmode) {
1247 case NL80211_IFTYPE_ADHOC:
1248 if (!AR_SREV_9340_13(ah)) {
1249 set |= AR_STA_ID1_ADHOC;
1250 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1251 break;
1252 }
1253 /* fall through */
1254 case NL80211_IFTYPE_OCB:
1255 case NL80211_IFTYPE_MESH_POINT:
1256 case NL80211_IFTYPE_AP:
1257 set |= AR_STA_ID1_STA_AP;
1258 /* fall through */
1259 case NL80211_IFTYPE_STATION:
1260 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1261 break;
1262 default:
1263 if (!ah->is_monitoring)
1264 set = 0;
1265 break;
1266 }
1267 REG_RMW(ah, AR_STA_ID1, set, mask);
1268 REG_RMW_BUFFER_FLUSH(ah);
1269 }
1270
ath9k_hw_get_delta_slope_vals(struct ath_hw * ah,u32 coef_scaled,u32 * coef_mantissa,u32 * coef_exponent)1271 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1272 u32 *coef_mantissa, u32 *coef_exponent)
1273 {
1274 u32 coef_exp, coef_man;
1275
1276 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1277 if ((coef_scaled >> coef_exp) & 0x1)
1278 break;
1279
1280 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1281
1282 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1283
1284 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1285 *coef_exponent = coef_exp - 16;
1286 }
1287
1288 /* AR9330 WAR:
1289 * call external reset function to reset WMAC if:
1290 * - doing a cold reset
1291 * - we have pending frames in the TX queues.
1292 */
ath9k_hw_ar9330_reset_war(struct ath_hw * ah,int type)1293 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1294 {
1295 int i, npend = 0;
1296
1297 for (i = 0; i < AR_NUM_QCU; i++) {
1298 npend = ath9k_hw_numtxpending(ah, i);
1299 if (npend)
1300 break;
1301 }
1302
1303 if (ah->external_reset &&
1304 (npend || type == ATH9K_RESET_COLD)) {
1305 int reset_err = 0;
1306
1307 ath_dbg(ath9k_hw_common(ah), RESET,
1308 "reset MAC via external reset\n");
1309
1310 reset_err = ah->external_reset();
1311 if (reset_err) {
1312 ath_err(ath9k_hw_common(ah),
1313 "External reset failed, err=%d\n",
1314 reset_err);
1315 return false;
1316 }
1317
1318 REG_WRITE(ah, AR_RTC_RESET, 1);
1319 }
1320
1321 return true;
1322 }
1323
ath9k_hw_set_reset(struct ath_hw * ah,int type)1324 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1325 {
1326 u32 rst_flags;
1327 u32 tmpReg;
1328
1329 if (AR_SREV_9100(ah)) {
1330 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1331 AR_RTC_DERIVED_CLK_PERIOD, 1);
1332 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1333 }
1334
1335 ENABLE_REGWRITE_BUFFER(ah);
1336
1337 if (AR_SREV_9300_20_OR_LATER(ah)) {
1338 REG_WRITE(ah, AR_WA, ah->WARegVal);
1339 udelay(10);
1340 }
1341
1342 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1343 AR_RTC_FORCE_WAKE_ON_INT);
1344
1345 if (AR_SREV_9100(ah)) {
1346 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1347 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1348 } else {
1349 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1350 if (AR_SREV_9340(ah))
1351 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1352 else
1353 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1354 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1355
1356 if (tmpReg) {
1357 u32 val;
1358 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1359
1360 val = AR_RC_HOSTIF;
1361 if (!AR_SREV_9300_20_OR_LATER(ah))
1362 val |= AR_RC_AHB;
1363 REG_WRITE(ah, AR_RC, val);
1364
1365 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1366 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1367
1368 rst_flags = AR_RTC_RC_MAC_WARM;
1369 if (type == ATH9K_RESET_COLD)
1370 rst_flags |= AR_RTC_RC_MAC_COLD;
1371 }
1372
1373 if (AR_SREV_9330(ah)) {
1374 if (!ath9k_hw_ar9330_reset_war(ah, type))
1375 return false;
1376 }
1377
1378 if (ath9k_hw_mci_is_enabled(ah))
1379 ar9003_mci_check_gpm_offset(ah);
1380
1381 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1382 * RTC_RC reg read
1383 */
1384 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1385 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1386 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1387 20 * AH_WAIT_TIMEOUT);
1388 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1389 }
1390
1391 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1392
1393 REGWRITE_BUFFER_FLUSH(ah);
1394
1395 if (AR_SREV_9300_20_OR_LATER(ah))
1396 udelay(50);
1397 else if (AR_SREV_9100(ah))
1398 mdelay(10);
1399 else
1400 udelay(100);
1401
1402 REG_WRITE(ah, AR_RTC_RC, 0);
1403 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1404 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1405 return false;
1406 }
1407
1408 if (!AR_SREV_9100(ah))
1409 REG_WRITE(ah, AR_RC, 0);
1410
1411 if (AR_SREV_9100(ah))
1412 udelay(50);
1413
1414 return true;
1415 }
1416
ath9k_hw_set_reset_power_on(struct ath_hw * ah)1417 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1418 {
1419 ENABLE_REGWRITE_BUFFER(ah);
1420
1421 if (AR_SREV_9300_20_OR_LATER(ah)) {
1422 REG_WRITE(ah, AR_WA, ah->WARegVal);
1423 udelay(10);
1424 }
1425
1426 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1427 AR_RTC_FORCE_WAKE_ON_INT);
1428
1429 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1430 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1431
1432 REG_WRITE(ah, AR_RTC_RESET, 0);
1433
1434 REGWRITE_BUFFER_FLUSH(ah);
1435
1436 udelay(2);
1437
1438 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1439 REG_WRITE(ah, AR_RC, 0);
1440
1441 REG_WRITE(ah, AR_RTC_RESET, 1);
1442
1443 if (!ath9k_hw_wait(ah,
1444 AR_RTC_STATUS,
1445 AR_RTC_STATUS_M,
1446 AR_RTC_STATUS_ON,
1447 AH_WAIT_TIMEOUT)) {
1448 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1449 return false;
1450 }
1451
1452 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1453 }
1454
ath9k_hw_set_reset_reg(struct ath_hw * ah,u32 type)1455 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1456 {
1457 bool ret = false;
1458
1459 if (AR_SREV_9300_20_OR_LATER(ah)) {
1460 REG_WRITE(ah, AR_WA, ah->WARegVal);
1461 udelay(10);
1462 }
1463
1464 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1465 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1466
1467 if (!ah->reset_power_on)
1468 type = ATH9K_RESET_POWER_ON;
1469
1470 switch (type) {
1471 case ATH9K_RESET_POWER_ON:
1472 ret = ath9k_hw_set_reset_power_on(ah);
1473 if (ret)
1474 ah->reset_power_on = true;
1475 break;
1476 case ATH9K_RESET_WARM:
1477 case ATH9K_RESET_COLD:
1478 ret = ath9k_hw_set_reset(ah, type);
1479 break;
1480 default:
1481 break;
1482 }
1483
1484 return ret;
1485 }
1486
ath9k_hw_chip_reset(struct ath_hw * ah,struct ath9k_channel * chan)1487 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1488 struct ath9k_channel *chan)
1489 {
1490 int reset_type = ATH9K_RESET_WARM;
1491
1492 if (AR_SREV_9280(ah)) {
1493 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1494 reset_type = ATH9K_RESET_POWER_ON;
1495 else
1496 reset_type = ATH9K_RESET_COLD;
1497 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1498 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1499 reset_type = ATH9K_RESET_COLD;
1500
1501 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1502 return false;
1503
1504 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1505 return false;
1506
1507 ah->chip_fullsleep = false;
1508
1509 if (AR_SREV_9330(ah))
1510 ar9003_hw_internal_regulator_apply(ah);
1511 ath9k_hw_init_pll(ah, chan);
1512
1513 return true;
1514 }
1515
ath9k_hw_channel_change(struct ath_hw * ah,struct ath9k_channel * chan)1516 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1517 struct ath9k_channel *chan)
1518 {
1519 struct ath_common *common = ath9k_hw_common(ah);
1520 struct ath9k_hw_capabilities *pCap = &ah->caps;
1521 bool band_switch = false, mode_diff = false;
1522 u8 ini_reloaded = 0;
1523 u32 qnum;
1524 int r;
1525
1526 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1527 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1528 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1529 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1530 }
1531
1532 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1533 if (ath9k_hw_numtxpending(ah, qnum)) {
1534 ath_dbg(common, QUEUE,
1535 "Transmit frames pending on queue %d\n", qnum);
1536 return false;
1537 }
1538 }
1539
1540 if (!ath9k_hw_rfbus_req(ah)) {
1541 ath_err(common, "Could not kill baseband RX\n");
1542 return false;
1543 }
1544
1545 if (band_switch || mode_diff) {
1546 ath9k_hw_mark_phy_inactive(ah);
1547 udelay(5);
1548
1549 if (band_switch)
1550 ath9k_hw_init_pll(ah, chan);
1551
1552 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1553 ath_err(common, "Failed to do fast channel change\n");
1554 return false;
1555 }
1556 }
1557
1558 ath9k_hw_set_channel_regs(ah, chan);
1559
1560 r = ath9k_hw_rf_set_freq(ah, chan);
1561 if (r) {
1562 ath_err(common, "Failed to set channel\n");
1563 return false;
1564 }
1565 ath9k_hw_set_clockrate(ah);
1566 ath9k_hw_apply_txpower(ah, chan, false);
1567
1568 ath9k_hw_set_delta_slope(ah, chan);
1569 ath9k_hw_spur_mitigate_freq(ah, chan);
1570
1571 if (band_switch || ini_reloaded)
1572 ah->eep_ops->set_board_values(ah, chan);
1573
1574 ath9k_hw_init_bb(ah, chan);
1575 ath9k_hw_rfbus_done(ah);
1576
1577 if (band_switch || ini_reloaded) {
1578 ah->ah_flags |= AH_FASTCC;
1579 ath9k_hw_init_cal(ah, chan);
1580 ah->ah_flags &= ~AH_FASTCC;
1581 }
1582
1583 return true;
1584 }
1585
ath9k_hw_apply_gpio_override(struct ath_hw * ah)1586 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1587 {
1588 u32 gpio_mask = ah->gpio_mask;
1589 int i;
1590
1591 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1592 if (!(gpio_mask & 1))
1593 continue;
1594
1595 ath9k_hw_gpio_request_out(ah, i, NULL,
1596 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1597 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1598 ath9k_hw_gpio_free(ah, i);
1599 }
1600 }
1601
ath9k_hw_check_nav(struct ath_hw * ah)1602 void ath9k_hw_check_nav(struct ath_hw *ah)
1603 {
1604 struct ath_common *common = ath9k_hw_common(ah);
1605 u32 val;
1606
1607 val = REG_READ(ah, AR_NAV);
1608 if (val != 0xdeadbeef && val > 0x7fff) {
1609 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1610 REG_WRITE(ah, AR_NAV, 0);
1611 }
1612 }
1613 EXPORT_SYMBOL(ath9k_hw_check_nav);
1614
ath9k_hw_check_alive(struct ath_hw * ah)1615 bool ath9k_hw_check_alive(struct ath_hw *ah)
1616 {
1617 int count = 50;
1618 u32 reg, last_val;
1619
1620 /* Check if chip failed to wake up */
1621 if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
1622 return false;
1623
1624 if (AR_SREV_9300(ah))
1625 return !ath9k_hw_detect_mac_hang(ah);
1626
1627 if (AR_SREV_9285_12_OR_LATER(ah))
1628 return true;
1629
1630 last_val = REG_READ(ah, AR_OBS_BUS_1);
1631 do {
1632 reg = REG_READ(ah, AR_OBS_BUS_1);
1633 if (reg != last_val)
1634 return true;
1635
1636 udelay(1);
1637 last_val = reg;
1638 if ((reg & 0x7E7FFFEF) == 0x00702400)
1639 continue;
1640
1641 switch (reg & 0x7E000B00) {
1642 case 0x1E000000:
1643 case 0x52000B00:
1644 case 0x18000B00:
1645 continue;
1646 default:
1647 return true;
1648 }
1649 } while (count-- > 0);
1650
1651 return false;
1652 }
1653 EXPORT_SYMBOL(ath9k_hw_check_alive);
1654
ath9k_hw_init_mfp(struct ath_hw * ah)1655 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1656 {
1657 /* Setup MFP options for CCMP */
1658 if (AR_SREV_9280_20_OR_LATER(ah)) {
1659 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1660 * frames when constructing CCMP AAD. */
1661 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1662 0xc7ff);
1663 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1664 ah->sw_mgmt_crypto_tx = true;
1665 else
1666 ah->sw_mgmt_crypto_tx = false;
1667 ah->sw_mgmt_crypto_rx = false;
1668 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1669 /* Disable hardware crypto for management frames */
1670 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1671 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1672 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1673 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1674 ah->sw_mgmt_crypto_tx = true;
1675 ah->sw_mgmt_crypto_rx = true;
1676 } else {
1677 ah->sw_mgmt_crypto_tx = true;
1678 ah->sw_mgmt_crypto_rx = true;
1679 }
1680 }
1681
ath9k_hw_reset_opmode(struct ath_hw * ah,u32 macStaId1,u32 saveDefAntenna)1682 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1683 u32 macStaId1, u32 saveDefAntenna)
1684 {
1685 struct ath_common *common = ath9k_hw_common(ah);
1686
1687 ENABLE_REGWRITE_BUFFER(ah);
1688
1689 REG_RMW(ah, AR_STA_ID1, macStaId1
1690 | AR_STA_ID1_RTS_USE_DEF
1691 | ah->sta_id1_defaults,
1692 ~AR_STA_ID1_SADH_MASK);
1693 ath_hw_setbssidmask(common);
1694 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1695 ath9k_hw_write_associd(ah);
1696 REG_WRITE(ah, AR_ISR, ~0);
1697 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1698
1699 REGWRITE_BUFFER_FLUSH(ah);
1700
1701 ath9k_hw_set_operating_mode(ah, ah->opmode);
1702 }
1703
ath9k_hw_init_queues(struct ath_hw * ah)1704 static void ath9k_hw_init_queues(struct ath_hw *ah)
1705 {
1706 int i;
1707
1708 ENABLE_REGWRITE_BUFFER(ah);
1709
1710 for (i = 0; i < AR_NUM_DCU; i++)
1711 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1712
1713 REGWRITE_BUFFER_FLUSH(ah);
1714
1715 ah->intr_txqs = 0;
1716 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1717 ath9k_hw_resettxqueue(ah, i);
1718 }
1719
1720 /*
1721 * For big endian systems turn on swapping for descriptors
1722 */
ath9k_hw_init_desc(struct ath_hw * ah)1723 static void ath9k_hw_init_desc(struct ath_hw *ah)
1724 {
1725 struct ath_common *common = ath9k_hw_common(ah);
1726
1727 if (AR_SREV_9100(ah)) {
1728 u32 mask;
1729 mask = REG_READ(ah, AR_CFG);
1730 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1731 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1732 mask);
1733 } else {
1734 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1735 REG_WRITE(ah, AR_CFG, mask);
1736 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1737 REG_READ(ah, AR_CFG));
1738 }
1739 } else {
1740 if (common->bus_ops->ath_bus_type == ATH_USB) {
1741 /* Configure AR9271 target WLAN */
1742 if (AR_SREV_9271(ah))
1743 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1744 else
1745 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1746 }
1747 #ifdef __BIG_ENDIAN
1748 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1749 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1750 AR_SREV_9561(ah))
1751 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1752 else
1753 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1754 #endif
1755 }
1756 }
1757
1758 /*
1759 * Fast channel change:
1760 * (Change synthesizer based on channel freq without resetting chip)
1761 */
ath9k_hw_do_fastcc(struct ath_hw * ah,struct ath9k_channel * chan)1762 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1763 {
1764 struct ath_common *common = ath9k_hw_common(ah);
1765 struct ath9k_hw_capabilities *pCap = &ah->caps;
1766 int ret;
1767
1768 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1769 goto fail;
1770
1771 if (ah->chip_fullsleep)
1772 goto fail;
1773
1774 if (!ah->curchan)
1775 goto fail;
1776
1777 if (chan->channel == ah->curchan->channel)
1778 goto fail;
1779
1780 if ((ah->curchan->channelFlags | chan->channelFlags) &
1781 (CHANNEL_HALF | CHANNEL_QUARTER))
1782 goto fail;
1783
1784 /*
1785 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1786 */
1787 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1788 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1789 goto fail;
1790
1791 if (!ath9k_hw_check_alive(ah))
1792 goto fail;
1793
1794 /*
1795 * For AR9462, make sure that calibration data for
1796 * re-using are present.
1797 */
1798 if (AR_SREV_9462(ah) && (ah->caldata &&
1799 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1800 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1801 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1802 goto fail;
1803
1804 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1805 ah->curchan->channel, chan->channel);
1806
1807 ret = ath9k_hw_channel_change(ah, chan);
1808 if (!ret)
1809 goto fail;
1810
1811 if (ath9k_hw_mci_is_enabled(ah))
1812 ar9003_mci_2g5g_switch(ah, false);
1813
1814 ath9k_hw_loadnf(ah, ah->curchan);
1815 ath9k_hw_start_nfcal(ah, true);
1816
1817 if (AR_SREV_9271(ah))
1818 ar9002_hw_load_ani_reg(ah, chan);
1819
1820 return 0;
1821 fail:
1822 return -EINVAL;
1823 }
1824
ath9k_hw_get_tsf_offset(struct timespec * last,struct timespec * cur)1825 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1826 {
1827 struct timespec ts;
1828 s64 usec;
1829
1830 if (!cur) {
1831 getrawmonotonic(&ts);
1832 cur = &ts;
1833 }
1834
1835 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1836 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1837
1838 return (u32) usec;
1839 }
1840 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1841
ath9k_hw_reset(struct ath_hw * ah,struct ath9k_channel * chan,struct ath9k_hw_cal_data * caldata,bool fastcc)1842 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1843 struct ath9k_hw_cal_data *caldata, bool fastcc)
1844 {
1845 struct ath_common *common = ath9k_hw_common(ah);
1846 u32 saveLedState;
1847 u32 saveDefAntenna;
1848 u32 macStaId1;
1849 struct timespec tsf_ts;
1850 u32 tsf_offset;
1851 u64 tsf = 0;
1852 int r;
1853 bool start_mci_reset = false;
1854 bool save_fullsleep = ah->chip_fullsleep;
1855
1856 if (ath9k_hw_mci_is_enabled(ah)) {
1857 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1858 if (start_mci_reset)
1859 return 0;
1860 }
1861
1862 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1863 return -EIO;
1864
1865 if (ah->curchan && !ah->chip_fullsleep)
1866 ath9k_hw_getnf(ah, ah->curchan);
1867
1868 ah->caldata = caldata;
1869 if (caldata && (chan->channel != caldata->channel ||
1870 chan->channelFlags != caldata->channelFlags)) {
1871 /* Operating channel changed, reset channel calibration data */
1872 memset(caldata, 0, sizeof(*caldata));
1873 ath9k_init_nfcal_hist_buffer(ah, chan);
1874 } else if (caldata) {
1875 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1876 }
1877 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1878
1879 if (fastcc) {
1880 r = ath9k_hw_do_fastcc(ah, chan);
1881 if (!r)
1882 return r;
1883 }
1884
1885 if (ath9k_hw_mci_is_enabled(ah))
1886 ar9003_mci_stop_bt(ah, save_fullsleep);
1887
1888 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1889 if (saveDefAntenna == 0)
1890 saveDefAntenna = 1;
1891
1892 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1893
1894 /* Save TSF before chip reset, a cold reset clears it */
1895 getrawmonotonic(&tsf_ts);
1896 tsf = ath9k_hw_gettsf64(ah);
1897
1898 saveLedState = REG_READ(ah, AR_CFG_LED) &
1899 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1900 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1901
1902 ath9k_hw_mark_phy_inactive(ah);
1903
1904 ah->paprd_table_write_done = false;
1905
1906 /* Only required on the first reset */
1907 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1908 REG_WRITE(ah,
1909 AR9271_RESET_POWER_DOWN_CONTROL,
1910 AR9271_RADIO_RF_RST);
1911 udelay(50);
1912 }
1913
1914 if (!ath9k_hw_chip_reset(ah, chan)) {
1915 ath_err(common, "Chip reset failed\n");
1916 return -EINVAL;
1917 }
1918
1919 /* Only required on the first reset */
1920 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1921 ah->htc_reset_init = false;
1922 REG_WRITE(ah,
1923 AR9271_RESET_POWER_DOWN_CONTROL,
1924 AR9271_GATE_MAC_CTL);
1925 udelay(50);
1926 }
1927
1928 /* Restore TSF */
1929 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1930 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1931
1932 if (AR_SREV_9280_20_OR_LATER(ah))
1933 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1934
1935 if (!AR_SREV_9300_20_OR_LATER(ah))
1936 ar9002_hw_enable_async_fifo(ah);
1937
1938 r = ath9k_hw_process_ini(ah, chan);
1939 if (r)
1940 return r;
1941
1942 ath9k_hw_set_rfmode(ah, chan);
1943
1944 if (ath9k_hw_mci_is_enabled(ah))
1945 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1946
1947 /*
1948 * Some AR91xx SoC devices frequently fail to accept TSF writes
1949 * right after the chip reset. When that happens, write a new
1950 * value after the initvals have been applied.
1951 */
1952 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1953 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1954 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1955 }
1956
1957 ath9k_hw_init_mfp(ah);
1958
1959 ath9k_hw_set_delta_slope(ah, chan);
1960 ath9k_hw_spur_mitigate_freq(ah, chan);
1961 ah->eep_ops->set_board_values(ah, chan);
1962
1963 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1964
1965 r = ath9k_hw_rf_set_freq(ah, chan);
1966 if (r)
1967 return r;
1968
1969 ath9k_hw_set_clockrate(ah);
1970
1971 ath9k_hw_init_queues(ah);
1972 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1973 ath9k_hw_ani_cache_ini_regs(ah);
1974 ath9k_hw_init_qos(ah);
1975
1976 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1977 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
1978
1979 ath9k_hw_init_global_settings(ah);
1980
1981 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1982 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1983 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1984 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1985 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1986 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1987 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1988 }
1989
1990 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1991
1992 ath9k_hw_set_dma(ah);
1993
1994 if (!ath9k_hw_mci_is_enabled(ah))
1995 REG_WRITE(ah, AR_OBS, 8);
1996
1997 ENABLE_REG_RMW_BUFFER(ah);
1998 if (ah->config.rx_intr_mitigation) {
1999 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
2000 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
2001 }
2002
2003 if (ah->config.tx_intr_mitigation) {
2004 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2005 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2006 }
2007 REG_RMW_BUFFER_FLUSH(ah);
2008
2009 ath9k_hw_init_bb(ah, chan);
2010
2011 if (caldata) {
2012 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2013 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
2014 }
2015 if (!ath9k_hw_init_cal(ah, chan))
2016 return -EIO;
2017
2018 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2019 return -EIO;
2020
2021 ENABLE_REGWRITE_BUFFER(ah);
2022
2023 ath9k_hw_restore_chainmask(ah);
2024 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2025
2026 REGWRITE_BUFFER_FLUSH(ah);
2027
2028 ath9k_hw_gen_timer_start_tsf2(ah);
2029
2030 ath9k_hw_init_desc(ah);
2031
2032 if (ath9k_hw_btcoex_is_enabled(ah))
2033 ath9k_hw_btcoex_enable(ah);
2034
2035 if (ath9k_hw_mci_is_enabled(ah))
2036 ar9003_mci_check_bt(ah);
2037
2038 if (AR_SREV_9300_20_OR_LATER(ah)) {
2039 ath9k_hw_loadnf(ah, chan);
2040 ath9k_hw_start_nfcal(ah, true);
2041 }
2042
2043 if (AR_SREV_9300_20_OR_LATER(ah))
2044 ar9003_hw_bb_watchdog_config(ah);
2045
2046 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2047 ar9003_hw_disable_phy_restart(ah);
2048
2049 ath9k_hw_apply_gpio_override(ah);
2050
2051 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2052 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2053
2054 if (ah->hw->conf.radar_enabled) {
2055 /* set HW specific DFS configuration */
2056 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2057 ath9k_hw_set_radar_params(ah);
2058 }
2059
2060 return 0;
2061 }
2062 EXPORT_SYMBOL(ath9k_hw_reset);
2063
2064 /******************************/
2065 /* Power Management (Chipset) */
2066 /******************************/
2067
2068 /*
2069 * Notify Power Mgt is disabled in self-generated frames.
2070 * If requested, force chip to sleep.
2071 */
ath9k_set_power_sleep(struct ath_hw * ah)2072 static void ath9k_set_power_sleep(struct ath_hw *ah)
2073 {
2074 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2075
2076 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2077 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2078 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2079 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2080 /* xxx Required for WLAN only case ? */
2081 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2082 udelay(100);
2083 }
2084
2085 /*
2086 * Clear the RTC force wake bit to allow the
2087 * mac to go to sleep.
2088 */
2089 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2090
2091 if (ath9k_hw_mci_is_enabled(ah))
2092 udelay(100);
2093
2094 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2095 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2096
2097 /* Shutdown chip. Active low */
2098 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2099 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2100 udelay(2);
2101 }
2102
2103 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2104 if (AR_SREV_9300_20_OR_LATER(ah))
2105 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2106 }
2107
2108 /*
2109 * Notify Power Management is enabled in self-generating
2110 * frames. If request, set power mode of chip to
2111 * auto/normal. Duration in units of 128us (1/8 TU).
2112 */
ath9k_set_power_network_sleep(struct ath_hw * ah)2113 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2114 {
2115 struct ath9k_hw_capabilities *pCap = &ah->caps;
2116
2117 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2118
2119 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2120 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2121 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2122 AR_RTC_FORCE_WAKE_ON_INT);
2123 } else {
2124
2125 /* When chip goes into network sleep, it could be waken
2126 * up by MCI_INT interrupt caused by BT's HW messages
2127 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2128 * rate (~100us). This will cause chip to leave and
2129 * re-enter network sleep mode frequently, which in
2130 * consequence will have WLAN MCI HW to generate lots of
2131 * SYS_WAKING and SYS_SLEEPING messages which will make
2132 * BT CPU to busy to process.
2133 */
2134 if (ath9k_hw_mci_is_enabled(ah))
2135 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2136 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2137 /*
2138 * Clear the RTC force wake bit to allow the
2139 * mac to go to sleep.
2140 */
2141 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2142
2143 if (ath9k_hw_mci_is_enabled(ah))
2144 udelay(30);
2145 }
2146
2147 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2148 if (AR_SREV_9300_20_OR_LATER(ah))
2149 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2150 }
2151
ath9k_hw_set_power_awake(struct ath_hw * ah)2152 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2153 {
2154 u32 val;
2155 int i;
2156
2157 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2158 if (AR_SREV_9300_20_OR_LATER(ah)) {
2159 REG_WRITE(ah, AR_WA, ah->WARegVal);
2160 udelay(10);
2161 }
2162
2163 if ((REG_READ(ah, AR_RTC_STATUS) &
2164 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2165 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2166 return false;
2167 }
2168 if (!AR_SREV_9300_20_OR_LATER(ah))
2169 ath9k_hw_init_pll(ah, NULL);
2170 }
2171 if (AR_SREV_9100(ah))
2172 REG_SET_BIT(ah, AR_RTC_RESET,
2173 AR_RTC_RESET_EN);
2174
2175 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2176 AR_RTC_FORCE_WAKE_EN);
2177 if (AR_SREV_9100(ah))
2178 mdelay(10);
2179 else
2180 udelay(50);
2181
2182 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2183 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2184 if (val == AR_RTC_STATUS_ON)
2185 break;
2186 udelay(50);
2187 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2188 AR_RTC_FORCE_WAKE_EN);
2189 }
2190 if (i == 0) {
2191 ath_err(ath9k_hw_common(ah),
2192 "Failed to wakeup in %uus\n",
2193 POWER_UP_TIME / 20);
2194 return false;
2195 }
2196
2197 if (ath9k_hw_mci_is_enabled(ah))
2198 ar9003_mci_set_power_awake(ah);
2199
2200 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2201
2202 return true;
2203 }
2204
ath9k_hw_setpower(struct ath_hw * ah,enum ath9k_power_mode mode)2205 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2206 {
2207 struct ath_common *common = ath9k_hw_common(ah);
2208 int status = true;
2209 static const char *modes[] = {
2210 "AWAKE",
2211 "FULL-SLEEP",
2212 "NETWORK SLEEP",
2213 "UNDEFINED"
2214 };
2215
2216 if (ah->power_mode == mode)
2217 return status;
2218
2219 ath_dbg(common, RESET, "%s -> %s\n",
2220 modes[ah->power_mode], modes[mode]);
2221
2222 switch (mode) {
2223 case ATH9K_PM_AWAKE:
2224 status = ath9k_hw_set_power_awake(ah);
2225 break;
2226 case ATH9K_PM_FULL_SLEEP:
2227 if (ath9k_hw_mci_is_enabled(ah))
2228 ar9003_mci_set_full_sleep(ah);
2229
2230 ath9k_set_power_sleep(ah);
2231 ah->chip_fullsleep = true;
2232 break;
2233 case ATH9K_PM_NETWORK_SLEEP:
2234 ath9k_set_power_network_sleep(ah);
2235 break;
2236 default:
2237 ath_err(common, "Unknown power mode %u\n", mode);
2238 return false;
2239 }
2240 ah->power_mode = mode;
2241
2242 /*
2243 * XXX: If this warning never comes up after a while then
2244 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2245 * ath9k_hw_setpower() return type void.
2246 */
2247
2248 if (!(ah->ah_flags & AH_UNPLUGGED))
2249 ATH_DBG_WARN_ON_ONCE(!status);
2250
2251 return status;
2252 }
2253 EXPORT_SYMBOL(ath9k_hw_setpower);
2254
2255 /*******************/
2256 /* Beacon Handling */
2257 /*******************/
2258
ath9k_hw_beaconinit(struct ath_hw * ah,u32 next_beacon,u32 beacon_period)2259 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2260 {
2261 int flags = 0;
2262
2263 ENABLE_REGWRITE_BUFFER(ah);
2264
2265 switch (ah->opmode) {
2266 case NL80211_IFTYPE_ADHOC:
2267 REG_SET_BIT(ah, AR_TXCFG,
2268 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2269 case NL80211_IFTYPE_MESH_POINT:
2270 case NL80211_IFTYPE_AP:
2271 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2272 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2273 TU_TO_USEC(ah->config.dma_beacon_response_time));
2274 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2275 TU_TO_USEC(ah->config.sw_beacon_response_time));
2276 flags |=
2277 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2278 break;
2279 default:
2280 ath_dbg(ath9k_hw_common(ah), BEACON,
2281 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2282 return;
2283 break;
2284 }
2285
2286 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2287 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2288 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2289
2290 REGWRITE_BUFFER_FLUSH(ah);
2291
2292 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2293 }
2294 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2295
ath9k_hw_set_sta_beacon_timers(struct ath_hw * ah,const struct ath9k_beacon_state * bs)2296 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2297 const struct ath9k_beacon_state *bs)
2298 {
2299 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2300 struct ath9k_hw_capabilities *pCap = &ah->caps;
2301 struct ath_common *common = ath9k_hw_common(ah);
2302
2303 ENABLE_REGWRITE_BUFFER(ah);
2304
2305 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2306 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2307 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2308
2309 REGWRITE_BUFFER_FLUSH(ah);
2310
2311 REG_RMW_FIELD(ah, AR_RSSI_THR,
2312 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2313
2314 beaconintval = bs->bs_intval;
2315
2316 if (bs->bs_sleepduration > beaconintval)
2317 beaconintval = bs->bs_sleepduration;
2318
2319 dtimperiod = bs->bs_dtimperiod;
2320 if (bs->bs_sleepduration > dtimperiod)
2321 dtimperiod = bs->bs_sleepduration;
2322
2323 if (beaconintval == dtimperiod)
2324 nextTbtt = bs->bs_nextdtim;
2325 else
2326 nextTbtt = bs->bs_nexttbtt;
2327
2328 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2329 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2330 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2331 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
2332
2333 ENABLE_REGWRITE_BUFFER(ah);
2334
2335 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2336 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2337
2338 REG_WRITE(ah, AR_SLEEP1,
2339 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2340 | AR_SLEEP1_ASSUME_DTIM);
2341
2342 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2343 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2344 else
2345 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2346
2347 REG_WRITE(ah, AR_SLEEP2,
2348 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2349
2350 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2351 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2352
2353 REGWRITE_BUFFER_FLUSH(ah);
2354
2355 REG_SET_BIT(ah, AR_TIMER_MODE,
2356 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2357 AR_DTIM_TIMER_EN);
2358
2359 /* TSF Out of Range Threshold */
2360 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2361 }
2362 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2363
2364 /*******************/
2365 /* HW Capabilities */
2366 /*******************/
2367
fixup_chainmask(u8 chip_chainmask,u8 eeprom_chainmask)2368 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2369 {
2370 eeprom_chainmask &= chip_chainmask;
2371 if (eeprom_chainmask)
2372 return eeprom_chainmask;
2373 else
2374 return chip_chainmask;
2375 }
2376
2377 /**
2378 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2379 * @ah: the atheros hardware data structure
2380 *
2381 * We enable DFS support upstream on chipsets which have passed a series
2382 * of tests. The testing requirements are going to be documented. Desired
2383 * test requirements are documented at:
2384 *
2385 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2386 *
2387 * Once a new chipset gets properly tested an individual commit can be used
2388 * to document the testing for DFS for that chipset.
2389 */
ath9k_hw_dfs_tested(struct ath_hw * ah)2390 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2391 {
2392
2393 switch (ah->hw_version.macVersion) {
2394 /* for temporary testing DFS with 9280 */
2395 case AR_SREV_VERSION_9280:
2396 /* AR9580 will likely be our first target to get testing on */
2397 case AR_SREV_VERSION_9580:
2398 return true;
2399 default:
2400 return false;
2401 }
2402 }
2403
ath9k_gpio_cap_init(struct ath_hw * ah)2404 static void ath9k_gpio_cap_init(struct ath_hw *ah)
2405 {
2406 struct ath9k_hw_capabilities *pCap = &ah->caps;
2407
2408 if (AR_SREV_9271(ah)) {
2409 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2410 pCap->gpio_mask = AR9271_GPIO_MASK;
2411 } else if (AR_DEVID_7010(ah)) {
2412 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2413 pCap->gpio_mask = AR7010_GPIO_MASK;
2414 } else if (AR_SREV_9287(ah)) {
2415 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2416 pCap->gpio_mask = AR9287_GPIO_MASK;
2417 } else if (AR_SREV_9285(ah)) {
2418 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2419 pCap->gpio_mask = AR9285_GPIO_MASK;
2420 } else if (AR_SREV_9280(ah)) {
2421 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2422 pCap->gpio_mask = AR9280_GPIO_MASK;
2423 } else if (AR_SREV_9300(ah)) {
2424 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2425 pCap->gpio_mask = AR9300_GPIO_MASK;
2426 } else if (AR_SREV_9330(ah)) {
2427 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2428 pCap->gpio_mask = AR9330_GPIO_MASK;
2429 } else if (AR_SREV_9340(ah)) {
2430 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2431 pCap->gpio_mask = AR9340_GPIO_MASK;
2432 } else if (AR_SREV_9462(ah)) {
2433 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2434 pCap->gpio_mask = AR9462_GPIO_MASK;
2435 } else if (AR_SREV_9485(ah)) {
2436 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2437 pCap->gpio_mask = AR9485_GPIO_MASK;
2438 } else if (AR_SREV_9531(ah)) {
2439 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2440 pCap->gpio_mask = AR9531_GPIO_MASK;
2441 } else if (AR_SREV_9550(ah)) {
2442 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2443 pCap->gpio_mask = AR9550_GPIO_MASK;
2444 } else if (AR_SREV_9561(ah)) {
2445 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2446 pCap->gpio_mask = AR9561_GPIO_MASK;
2447 } else if (AR_SREV_9565(ah)) {
2448 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2449 pCap->gpio_mask = AR9565_GPIO_MASK;
2450 } else if (AR_SREV_9580(ah)) {
2451 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2452 pCap->gpio_mask = AR9580_GPIO_MASK;
2453 } else {
2454 pCap->num_gpio_pins = AR_NUM_GPIO;
2455 pCap->gpio_mask = AR_GPIO_MASK;
2456 }
2457 }
2458
ath9k_hw_fill_cap_info(struct ath_hw * ah)2459 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2460 {
2461 struct ath9k_hw_capabilities *pCap = &ah->caps;
2462 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2463 struct ath_common *common = ath9k_hw_common(ah);
2464
2465 u16 eeval;
2466 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2467
2468 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2469 regulatory->current_rd = eeval;
2470
2471 if (ah->opmode != NL80211_IFTYPE_AP &&
2472 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2473 if (regulatory->current_rd == 0x64 ||
2474 regulatory->current_rd == 0x65)
2475 regulatory->current_rd += 5;
2476 else if (regulatory->current_rd == 0x41)
2477 regulatory->current_rd = 0x43;
2478 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2479 regulatory->current_rd);
2480 }
2481
2482 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2483
2484 if (eeval & AR5416_OPFLAGS_11A) {
2485 if (ah->disable_5ghz)
2486 ath_warn(common, "disabling 5GHz band\n");
2487 else
2488 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2489 }
2490
2491 if (eeval & AR5416_OPFLAGS_11G) {
2492 if (ah->disable_2ghz)
2493 ath_warn(common, "disabling 2GHz band\n");
2494 else
2495 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2496 }
2497
2498 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2499 ath_err(common, "both bands are disabled\n");
2500 return -EINVAL;
2501 }
2502
2503 ath9k_gpio_cap_init(ah);
2504
2505 if (AR_SREV_9485(ah) ||
2506 AR_SREV_9285(ah) ||
2507 AR_SREV_9330(ah) ||
2508 AR_SREV_9565(ah))
2509 pCap->chip_chainmask = 1;
2510 else if (!AR_SREV_9280_20_OR_LATER(ah))
2511 pCap->chip_chainmask = 7;
2512 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2513 AR_SREV_9340(ah) ||
2514 AR_SREV_9462(ah) ||
2515 AR_SREV_9531(ah))
2516 pCap->chip_chainmask = 3;
2517 else
2518 pCap->chip_chainmask = 7;
2519
2520 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2521 /*
2522 * For AR9271 we will temporarilly uses the rx chainmax as read from
2523 * the EEPROM.
2524 */
2525 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2526 !(eeval & AR5416_OPFLAGS_11A) &&
2527 !(AR_SREV_9271(ah)))
2528 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2529 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2530 else if (AR_SREV_9100(ah))
2531 pCap->rx_chainmask = 0x7;
2532 else
2533 /* Use rx_chainmask from EEPROM. */
2534 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2535
2536 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2537 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2538 ah->txchainmask = pCap->tx_chainmask;
2539 ah->rxchainmask = pCap->rx_chainmask;
2540
2541 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2542
2543 /* enable key search for every frame in an aggregate */
2544 if (AR_SREV_9300_20_OR_LATER(ah))
2545 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2546
2547 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2548
2549 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2550 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2551 else
2552 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2553
2554 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2555 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2556 else
2557 pCap->rts_aggr_limit = (8 * 1024);
2558
2559 #ifdef CONFIG_ATH9K_RFKILL
2560 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2561 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2562 ah->rfkill_gpio =
2563 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2564 ah->rfkill_polarity =
2565 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2566
2567 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2568 }
2569 #endif
2570 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2571 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2572 else
2573 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2574
2575 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2576 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2577 else
2578 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2579
2580 if (AR_SREV_9300_20_OR_LATER(ah)) {
2581 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2582 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2583 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2584 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2585
2586 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2587 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2588 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2589 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2590 pCap->txs_len = sizeof(struct ar9003_txs);
2591 } else {
2592 pCap->tx_desc_len = sizeof(struct ath_desc);
2593 if (AR_SREV_9280_20(ah))
2594 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2595 }
2596
2597 if (AR_SREV_9300_20_OR_LATER(ah))
2598 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2599
2600 if (AR_SREV_9561(ah))
2601 ah->ent_mode = 0x3BDA000;
2602 else if (AR_SREV_9300_20_OR_LATER(ah))
2603 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2604
2605 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2606 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2607
2608 if (AR_SREV_9285(ah)) {
2609 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2610 ant_div_ctl1 =
2611 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2612 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2613 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2614 ath_info(common, "Enable LNA combining\n");
2615 }
2616 }
2617 }
2618
2619 if (AR_SREV_9300_20_OR_LATER(ah)) {
2620 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2621 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2622 }
2623
2624 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2625 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2626 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2627 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2628 ath_info(common, "Enable LNA combining\n");
2629 }
2630 }
2631
2632 if (ath9k_hw_dfs_tested(ah))
2633 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2634
2635 tx_chainmask = pCap->tx_chainmask;
2636 rx_chainmask = pCap->rx_chainmask;
2637 while (tx_chainmask || rx_chainmask) {
2638 if (tx_chainmask & BIT(0))
2639 pCap->max_txchains++;
2640 if (rx_chainmask & BIT(0))
2641 pCap->max_rxchains++;
2642
2643 tx_chainmask >>= 1;
2644 rx_chainmask >>= 1;
2645 }
2646
2647 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2648 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2649 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2650
2651 if (AR_SREV_9462_20_OR_LATER(ah))
2652 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2653 }
2654
2655 if (AR_SREV_9300_20_OR_LATER(ah) &&
2656 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2657 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2658
2659 #ifdef CONFIG_ATH9K_WOW
2660 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2661 ah->wow.max_patterns = MAX_NUM_PATTERN;
2662 else
2663 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2664 #endif
2665
2666 return 0;
2667 }
2668
2669 /****************************/
2670 /* GPIO / RFKILL / Antennae */
2671 /****************************/
2672
ath9k_hw_gpio_cfg_output_mux(struct ath_hw * ah,u32 gpio,u32 type)2673 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
2674 {
2675 int addr;
2676 u32 gpio_shift, tmp;
2677
2678 if (gpio > 11)
2679 addr = AR_GPIO_OUTPUT_MUX3;
2680 else if (gpio > 5)
2681 addr = AR_GPIO_OUTPUT_MUX2;
2682 else
2683 addr = AR_GPIO_OUTPUT_MUX1;
2684
2685 gpio_shift = (gpio % 6) * 5;
2686
2687 if (AR_SREV_9280_20_OR_LATER(ah) ||
2688 (addr != AR_GPIO_OUTPUT_MUX1)) {
2689 REG_RMW(ah, addr, (type << gpio_shift),
2690 (0x1f << gpio_shift));
2691 } else {
2692 tmp = REG_READ(ah, addr);
2693 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2694 tmp &= ~(0x1f << gpio_shift);
2695 tmp |= (type << gpio_shift);
2696 REG_WRITE(ah, addr, tmp);
2697 }
2698 }
2699
2700 /* BSP should set the corresponding MUX register correctly.
2701 */
ath9k_hw_gpio_cfg_soc(struct ath_hw * ah,u32 gpio,bool out,const char * label)2702 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2703 const char *label)
2704 {
2705 if (ah->caps.gpio_requested & BIT(gpio))
2706 return;
2707
2708 /* may be requested by BSP, free anyway */
2709 gpio_free(gpio);
2710
2711 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
2712 return;
2713
2714 ah->caps.gpio_requested |= BIT(gpio);
2715 }
2716
ath9k_hw_gpio_cfg_wmac(struct ath_hw * ah,u32 gpio,bool out,u32 ah_signal_type)2717 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2718 u32 ah_signal_type)
2719 {
2720 u32 gpio_set, gpio_shift = gpio;
2721
2722 if (AR_DEVID_7010(ah)) {
2723 gpio_set = out ?
2724 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2725 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2726 AR7010_GPIO_OE_MASK << gpio_shift);
2727 } else if (AR_SREV_SOC(ah)) {
2728 gpio_set = out ? 1 : 0;
2729 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2730 gpio_set << gpio_shift);
2731 } else {
2732 gpio_shift = gpio << 1;
2733 gpio_set = out ?
2734 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2735 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2736 AR_GPIO_OE_OUT_DRV << gpio_shift);
2737
2738 if (out)
2739 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2740 }
2741 }
2742
ath9k_hw_gpio_request(struct ath_hw * ah,u32 gpio,bool out,const char * label,u32 ah_signal_type)2743 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2744 const char *label, u32 ah_signal_type)
2745 {
2746 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2747
2748 if (BIT(gpio) & ah->caps.gpio_mask)
2749 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2750 else if (AR_SREV_SOC(ah))
2751 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2752 else
2753 WARN_ON(1);
2754 }
2755
ath9k_hw_gpio_request_in(struct ath_hw * ah,u32 gpio,const char * label)2756 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2757 {
2758 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
2759 }
2760 EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
2761
ath9k_hw_gpio_request_out(struct ath_hw * ah,u32 gpio,const char * label,u32 ah_signal_type)2762 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2763 u32 ah_signal_type)
2764 {
2765 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2766 }
2767 EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2768
ath9k_hw_gpio_free(struct ath_hw * ah,u32 gpio)2769 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2770 {
2771 if (!AR_SREV_SOC(ah))
2772 return;
2773
2774 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2775
2776 if (ah->caps.gpio_requested & BIT(gpio)) {
2777 gpio_free(gpio);
2778 ah->caps.gpio_requested &= ~BIT(gpio);
2779 }
2780 }
2781 EXPORT_SYMBOL(ath9k_hw_gpio_free);
2782
ath9k_hw_gpio_get(struct ath_hw * ah,u32 gpio)2783 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2784 {
2785 u32 val = 0xffffffff;
2786
2787 #define MS_REG_READ(x, y) \
2788 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
2789
2790 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2791
2792 if (BIT(gpio) & ah->caps.gpio_mask) {
2793 if (AR_SREV_9271(ah))
2794 val = MS_REG_READ(AR9271, gpio);
2795 else if (AR_SREV_9287(ah))
2796 val = MS_REG_READ(AR9287, gpio);
2797 else if (AR_SREV_9285(ah))
2798 val = MS_REG_READ(AR9285, gpio);
2799 else if (AR_SREV_9280(ah))
2800 val = MS_REG_READ(AR928X, gpio);
2801 else if (AR_DEVID_7010(ah))
2802 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2803 else if (AR_SREV_9300_20_OR_LATER(ah))
2804 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2805 else
2806 val = MS_REG_READ(AR, gpio);
2807 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2808 val = gpio_get_value(gpio) & BIT(gpio);
2809 } else {
2810 WARN_ON(1);
2811 }
2812
2813 return !!val;
2814 }
2815 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2816
ath9k_hw_set_gpio(struct ath_hw * ah,u32 gpio,u32 val)2817 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2818 {
2819 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2820
2821 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2822 val = !val;
2823 else
2824 val = !!val;
2825
2826 if (BIT(gpio) & ah->caps.gpio_mask) {
2827 u32 out_addr = AR_DEVID_7010(ah) ?
2828 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2829
2830 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2831 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2832 gpio_set_value(gpio, val);
2833 } else {
2834 WARN_ON(1);
2835 }
2836 }
2837 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2838
ath9k_hw_setantenna(struct ath_hw * ah,u32 antenna)2839 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2840 {
2841 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2842 }
2843 EXPORT_SYMBOL(ath9k_hw_setantenna);
2844
2845 /*********************/
2846 /* General Operation */
2847 /*********************/
2848
ath9k_hw_getrxfilter(struct ath_hw * ah)2849 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2850 {
2851 u32 bits = REG_READ(ah, AR_RX_FILTER);
2852 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2853
2854 if (phybits & AR_PHY_ERR_RADAR)
2855 bits |= ATH9K_RX_FILTER_PHYRADAR;
2856 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2857 bits |= ATH9K_RX_FILTER_PHYERR;
2858
2859 return bits;
2860 }
2861 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2862
ath9k_hw_setrxfilter(struct ath_hw * ah,u32 bits)2863 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2864 {
2865 u32 phybits;
2866
2867 ENABLE_REGWRITE_BUFFER(ah);
2868
2869 REG_WRITE(ah, AR_RX_FILTER, bits);
2870
2871 phybits = 0;
2872 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2873 phybits |= AR_PHY_ERR_RADAR;
2874 if (bits & ATH9K_RX_FILTER_PHYERR)
2875 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2876 REG_WRITE(ah, AR_PHY_ERR, phybits);
2877
2878 if (phybits)
2879 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2880 else
2881 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2882
2883 REGWRITE_BUFFER_FLUSH(ah);
2884 }
2885 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2886
ath9k_hw_phy_disable(struct ath_hw * ah)2887 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2888 {
2889 if (ath9k_hw_mci_is_enabled(ah))
2890 ar9003_mci_bt_gain_ctrl(ah);
2891
2892 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2893 return false;
2894
2895 ath9k_hw_init_pll(ah, NULL);
2896 ah->htc_reset_init = true;
2897 return true;
2898 }
2899 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2900
ath9k_hw_disable(struct ath_hw * ah)2901 bool ath9k_hw_disable(struct ath_hw *ah)
2902 {
2903 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2904 return false;
2905
2906 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2907 return false;
2908
2909 ath9k_hw_init_pll(ah, NULL);
2910 return true;
2911 }
2912 EXPORT_SYMBOL(ath9k_hw_disable);
2913
get_antenna_gain(struct ath_hw * ah,struct ath9k_channel * chan)2914 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2915 {
2916 enum eeprom_param gain_param;
2917
2918 if (IS_CHAN_2GHZ(chan))
2919 gain_param = EEP_ANTENNA_GAIN_2G;
2920 else
2921 gain_param = EEP_ANTENNA_GAIN_5G;
2922
2923 return ah->eep_ops->get_eeprom(ah, gain_param);
2924 }
2925
ath9k_hw_apply_txpower(struct ath_hw * ah,struct ath9k_channel * chan,bool test)2926 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2927 bool test)
2928 {
2929 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2930 struct ieee80211_channel *channel;
2931 int chan_pwr, new_pwr;
2932 u16 ctl = NO_CTL;
2933
2934 if (!chan)
2935 return;
2936
2937 if (!test)
2938 ctl = ath9k_regd_get_ctl(reg, chan);
2939
2940 channel = chan->chan;
2941 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2942 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2943
2944 ah->eep_ops->set_txpower(ah, chan, ctl,
2945 get_antenna_gain(ah, chan), new_pwr, test);
2946 }
2947
ath9k_hw_set_txpowerlimit(struct ath_hw * ah,u32 limit,bool test)2948 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2949 {
2950 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2951 struct ath9k_channel *chan = ah->curchan;
2952 struct ieee80211_channel *channel = chan->chan;
2953
2954 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2955 if (test)
2956 channel->max_power = MAX_RATE_POWER / 2;
2957
2958 ath9k_hw_apply_txpower(ah, chan, test);
2959
2960 if (test)
2961 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2962 }
2963 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2964
ath9k_hw_setopmode(struct ath_hw * ah)2965 void ath9k_hw_setopmode(struct ath_hw *ah)
2966 {
2967 ath9k_hw_set_operating_mode(ah, ah->opmode);
2968 }
2969 EXPORT_SYMBOL(ath9k_hw_setopmode);
2970
ath9k_hw_setmcastfilter(struct ath_hw * ah,u32 filter0,u32 filter1)2971 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2972 {
2973 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2974 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2975 }
2976 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2977
ath9k_hw_write_associd(struct ath_hw * ah)2978 void ath9k_hw_write_associd(struct ath_hw *ah)
2979 {
2980 struct ath_common *common = ath9k_hw_common(ah);
2981
2982 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2983 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2984 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2985 }
2986 EXPORT_SYMBOL(ath9k_hw_write_associd);
2987
2988 #define ATH9K_MAX_TSF_READ 10
2989
ath9k_hw_gettsf64(struct ath_hw * ah)2990 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2991 {
2992 u32 tsf_lower, tsf_upper1, tsf_upper2;
2993 int i;
2994
2995 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2996 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2997 tsf_lower = REG_READ(ah, AR_TSF_L32);
2998 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2999 if (tsf_upper2 == tsf_upper1)
3000 break;
3001 tsf_upper1 = tsf_upper2;
3002 }
3003
3004 WARN_ON( i == ATH9K_MAX_TSF_READ );
3005
3006 return (((u64)tsf_upper1 << 32) | tsf_lower);
3007 }
3008 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3009
ath9k_hw_settsf64(struct ath_hw * ah,u64 tsf64)3010 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3011 {
3012 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3013 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3014 }
3015 EXPORT_SYMBOL(ath9k_hw_settsf64);
3016
ath9k_hw_reset_tsf(struct ath_hw * ah)3017 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3018 {
3019 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3020 AH_TSF_WRITE_TIMEOUT))
3021 ath_dbg(ath9k_hw_common(ah), RESET,
3022 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3023
3024 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3025 }
3026 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3027
ath9k_hw_set_tsfadjust(struct ath_hw * ah,bool set)3028 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3029 {
3030 if (set)
3031 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3032 else
3033 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3034 }
3035 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3036
ath9k_hw_set11nmac2040(struct ath_hw * ah,struct ath9k_channel * chan)3037 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
3038 {
3039 u32 macmode;
3040
3041 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
3042 macmode = AR_2040_JOINED_RX_CLEAR;
3043 else
3044 macmode = 0;
3045
3046 REG_WRITE(ah, AR_2040_MODE, macmode);
3047 }
3048
3049 /* HW Generic timers configuration */
3050
3051 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3052 {
3053 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3054 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3055 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3056 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3057 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3058 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3059 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3060 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3061 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3062 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3063 AR_NDP2_TIMER_MODE, 0x0002},
3064 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3065 AR_NDP2_TIMER_MODE, 0x0004},
3066 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3067 AR_NDP2_TIMER_MODE, 0x0008},
3068 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3069 AR_NDP2_TIMER_MODE, 0x0010},
3070 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3071 AR_NDP2_TIMER_MODE, 0x0020},
3072 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3073 AR_NDP2_TIMER_MODE, 0x0040},
3074 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3075 AR_NDP2_TIMER_MODE, 0x0080}
3076 };
3077
3078 /* HW generic timer primitives */
3079
ath9k_hw_gettsf32(struct ath_hw * ah)3080 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3081 {
3082 return REG_READ(ah, AR_TSF_L32);
3083 }
3084 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3085
ath9k_hw_gen_timer_start_tsf2(struct ath_hw * ah)3086 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3087 {
3088 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3089
3090 if (timer_table->tsf2_enabled) {
3091 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3092 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3093 }
3094 }
3095
ath_gen_timer_alloc(struct ath_hw * ah,void (* trigger)(void *),void (* overflow)(void *),void * arg,u8 timer_index)3096 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3097 void (*trigger)(void *),
3098 void (*overflow)(void *),
3099 void *arg,
3100 u8 timer_index)
3101 {
3102 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3103 struct ath_gen_timer *timer;
3104
3105 if ((timer_index < AR_FIRST_NDP_TIMER) ||
3106 (timer_index >= ATH_MAX_GEN_TIMER))
3107 return NULL;
3108
3109 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3110 !AR_SREV_9300_20_OR_LATER(ah))
3111 return NULL;
3112
3113 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3114 if (timer == NULL)
3115 return NULL;
3116
3117 /* allocate a hardware generic timer slot */
3118 timer_table->timers[timer_index] = timer;
3119 timer->index = timer_index;
3120 timer->trigger = trigger;
3121 timer->overflow = overflow;
3122 timer->arg = arg;
3123
3124 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3125 timer_table->tsf2_enabled = true;
3126 ath9k_hw_gen_timer_start_tsf2(ah);
3127 }
3128
3129 return timer;
3130 }
3131 EXPORT_SYMBOL(ath_gen_timer_alloc);
3132
ath9k_hw_gen_timer_start(struct ath_hw * ah,struct ath_gen_timer * timer,u32 timer_next,u32 timer_period)3133 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3134 struct ath_gen_timer *timer,
3135 u32 timer_next,
3136 u32 timer_period)
3137 {
3138 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3139 u32 mask = 0;
3140
3141 timer_table->timer_mask |= BIT(timer->index);
3142
3143 /*
3144 * Program generic timer registers
3145 */
3146 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3147 timer_next);
3148 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3149 timer_period);
3150 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3151 gen_tmr_configuration[timer->index].mode_mask);
3152
3153 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3154 /*
3155 * Starting from AR9462, each generic timer can select which tsf
3156 * to use. But we still follow the old rule, 0 - 7 use tsf and
3157 * 8 - 15 use tsf2.
3158 */
3159 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3160 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3161 (1 << timer->index));
3162 else
3163 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3164 (1 << timer->index));
3165 }
3166
3167 if (timer->trigger)
3168 mask |= SM(AR_GENTMR_BIT(timer->index),
3169 AR_IMR_S5_GENTIMER_TRIG);
3170 if (timer->overflow)
3171 mask |= SM(AR_GENTMR_BIT(timer->index),
3172 AR_IMR_S5_GENTIMER_THRESH);
3173
3174 REG_SET_BIT(ah, AR_IMR_S5, mask);
3175
3176 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3177 ah->imask |= ATH9K_INT_GENTIMER;
3178 ath9k_hw_set_interrupts(ah);
3179 }
3180 }
3181 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3182
ath9k_hw_gen_timer_stop(struct ath_hw * ah,struct ath_gen_timer * timer)3183 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3184 {
3185 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3186
3187 /* Clear generic timer enable bits. */
3188 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3189 gen_tmr_configuration[timer->index].mode_mask);
3190
3191 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3192 /*
3193 * Need to switch back to TSF if it was using TSF2.
3194 */
3195 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3196 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3197 (1 << timer->index));
3198 }
3199 }
3200
3201 /* Disable both trigger and thresh interrupt masks */
3202 REG_CLR_BIT(ah, AR_IMR_S5,
3203 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3204 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3205
3206 timer_table->timer_mask &= ~BIT(timer->index);
3207
3208 if (timer_table->timer_mask == 0) {
3209 ah->imask &= ~ATH9K_INT_GENTIMER;
3210 ath9k_hw_set_interrupts(ah);
3211 }
3212 }
3213 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3214
ath_gen_timer_free(struct ath_hw * ah,struct ath_gen_timer * timer)3215 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3216 {
3217 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3218
3219 /* free the hardware generic timer slot */
3220 timer_table->timers[timer->index] = NULL;
3221 kfree(timer);
3222 }
3223 EXPORT_SYMBOL(ath_gen_timer_free);
3224
3225 /*
3226 * Generic Timer Interrupts handling
3227 */
ath_gen_timer_isr(struct ath_hw * ah)3228 void ath_gen_timer_isr(struct ath_hw *ah)
3229 {
3230 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3231 struct ath_gen_timer *timer;
3232 unsigned long trigger_mask, thresh_mask;
3233 unsigned int index;
3234
3235 /* get hardware generic timer interrupt status */
3236 trigger_mask = ah->intr_gen_timer_trigger;
3237 thresh_mask = ah->intr_gen_timer_thresh;
3238 trigger_mask &= timer_table->timer_mask;
3239 thresh_mask &= timer_table->timer_mask;
3240
3241 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3242 timer = timer_table->timers[index];
3243 if (!timer)
3244 continue;
3245 if (!timer->overflow)
3246 continue;
3247
3248 trigger_mask &= ~BIT(index);
3249 timer->overflow(timer->arg);
3250 }
3251
3252 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3253 timer = timer_table->timers[index];
3254 if (!timer)
3255 continue;
3256 if (!timer->trigger)
3257 continue;
3258 timer->trigger(timer->arg);
3259 }
3260 }
3261 EXPORT_SYMBOL(ath_gen_timer_isr);
3262
3263 /********/
3264 /* HTC */
3265 /********/
3266
3267 static struct {
3268 u32 version;
3269 const char * name;
3270 } ath_mac_bb_names[] = {
3271 /* Devices with external radios */
3272 { AR_SREV_VERSION_5416_PCI, "5416" },
3273 { AR_SREV_VERSION_5416_PCIE, "5418" },
3274 { AR_SREV_VERSION_9100, "9100" },
3275 { AR_SREV_VERSION_9160, "9160" },
3276 /* Single-chip solutions */
3277 { AR_SREV_VERSION_9280, "9280" },
3278 { AR_SREV_VERSION_9285, "9285" },
3279 { AR_SREV_VERSION_9287, "9287" },
3280 { AR_SREV_VERSION_9271, "9271" },
3281 { AR_SREV_VERSION_9300, "9300" },
3282 { AR_SREV_VERSION_9330, "9330" },
3283 { AR_SREV_VERSION_9340, "9340" },
3284 { AR_SREV_VERSION_9485, "9485" },
3285 { AR_SREV_VERSION_9462, "9462" },
3286 { AR_SREV_VERSION_9550, "9550" },
3287 { AR_SREV_VERSION_9565, "9565" },
3288 { AR_SREV_VERSION_9531, "9531" },
3289 { AR_SREV_VERSION_9561, "9561" },
3290 };
3291
3292 /* For devices with external radios */
3293 static struct {
3294 u16 version;
3295 const char * name;
3296 } ath_rf_names[] = {
3297 { 0, "5133" },
3298 { AR_RAD5133_SREV_MAJOR, "5133" },
3299 { AR_RAD5122_SREV_MAJOR, "5122" },
3300 { AR_RAD2133_SREV_MAJOR, "2133" },
3301 { AR_RAD2122_SREV_MAJOR, "2122" }
3302 };
3303
3304 /*
3305 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3306 */
ath9k_hw_mac_bb_name(u32 mac_bb_version)3307 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3308 {
3309 int i;
3310
3311 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3312 if (ath_mac_bb_names[i].version == mac_bb_version) {
3313 return ath_mac_bb_names[i].name;
3314 }
3315 }
3316
3317 return "????";
3318 }
3319
3320 /*
3321 * Return the RF name. "????" is returned if the RF is unknown.
3322 * Used for devices with external radios.
3323 */
ath9k_hw_rf_name(u16 rf_version)3324 static const char *ath9k_hw_rf_name(u16 rf_version)
3325 {
3326 int i;
3327
3328 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3329 if (ath_rf_names[i].version == rf_version) {
3330 return ath_rf_names[i].name;
3331 }
3332 }
3333
3334 return "????";
3335 }
3336
ath9k_hw_name(struct ath_hw * ah,char * hw_name,size_t len)3337 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3338 {
3339 int used;
3340
3341 /* chipsets >= AR9280 are single-chip */
3342 if (AR_SREV_9280_20_OR_LATER(ah)) {
3343 used = scnprintf(hw_name, len,
3344 "Atheros AR%s Rev:%x",
3345 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3346 ah->hw_version.macRev);
3347 }
3348 else {
3349 used = scnprintf(hw_name, len,
3350 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3351 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3352 ah->hw_version.macRev,
3353 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3354 & AR_RADIO_SREV_MAJOR)),
3355 ah->hw_version.phyRev);
3356 }
3357
3358 hw_name[used] = '\0';
3359 }
3360 EXPORT_SYMBOL(ath9k_hw_name);
3361