1/* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 * 14 * Linux interrupt vectors. 15 */ 16 17#include <linux/linkage.h> 18#include <linux/errno.h> 19#include <linux/init.h> 20#include <linux/unistd.h> 21#include <asm/ptrace.h> 22#include <asm/thread_info.h> 23#include <asm/irqflags.h> 24#include <asm/atomic_32.h> 25#include <asm/asm-offsets.h> 26#include <hv/hypervisor.h> 27#include <arch/abi.h> 28#include <arch/interrupts.h> 29#include <arch/spr_def.h> 30 31#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg) 32 33#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR) 34 35 .macro push_reg reg, ptr=sp, delta=-4 36 { 37 sw \ptr, \reg 38 addli \ptr, \ptr, \delta 39 } 40 .endm 41 42 .macro pop_reg reg, ptr=sp, delta=4 43 { 44 lw \reg, \ptr 45 addli \ptr, \ptr, \delta 46 } 47 .endm 48 49 .macro pop_reg_zero reg, zreg, ptr=sp, delta=4 50 { 51 move \zreg, zero 52 lw \reg, \ptr 53 addi \ptr, \ptr, \delta 54 } 55 .endm 56 57 .macro push_extra_callee_saves reg 58 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51)) 59 push_reg r51, \reg 60 push_reg r50, \reg 61 push_reg r49, \reg 62 push_reg r48, \reg 63 push_reg r47, \reg 64 push_reg r46, \reg 65 push_reg r45, \reg 66 push_reg r44, \reg 67 push_reg r43, \reg 68 push_reg r42, \reg 69 push_reg r41, \reg 70 push_reg r40, \reg 71 push_reg r39, \reg 72 push_reg r38, \reg 73 push_reg r37, \reg 74 push_reg r36, \reg 75 push_reg r35, \reg 76 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34) 77 .endm 78 79 .macro panic str 80 .pushsection .rodata, "a" 811: 82 .asciz "\str" 83 .popsection 84 { 85 moveli r0, lo16(1b) 86 } 87 { 88 auli r0, r0, ha16(1b) 89 jal panic 90 } 91 .endm 92 93#ifdef __COLLECT_LINKER_FEEDBACK__ 94 .pushsection .text.intvec_feedback,"ax" 95intvec_feedback: 96 .popsection 97#endif 98 99 /* 100 * Default interrupt handler. 101 * 102 * vecnum is where we'll put this code. 103 * c_routine is the C routine we'll call. 104 * 105 * The C routine is passed two arguments: 106 * - A pointer to the pt_regs state. 107 * - The interrupt vector number. 108 * 109 * The "processing" argument specifies the code for processing 110 * the interrupt. Defaults to "handle_interrupt". 111 */ 112 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt 113 .org (\vecnum << 8) 114intvec_\vecname: 115 .ifc \vecnum, INT_SWINT_1 116 blz TREG_SYSCALL_NR_NAME, sys_cmpxchg 117 .endif 118 119 /* Temporarily save a register so we have somewhere to work. */ 120 121 mtspr SPR_SYSTEM_SAVE_K_1, r0 122 mfspr r0, SPR_EX_CONTEXT_K_1 123 124 /* The cmpxchg code clears sp to force us to reset it here on fault. */ 125 { 126 bz sp, 2f 127 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 128 } 129 130 .ifc \vecnum, INT_DOUBLE_FAULT 131 /* 132 * For double-faults from user-space, fall through to the normal 133 * register save and stack setup path. Otherwise, it's the 134 * hypervisor giving us one last chance to dump diagnostics, and we 135 * branch to the kernel_double_fault routine to do so. 136 */ 137 bz r0, 1f 138 j _kernel_double_fault 1391: 140 .else 141 /* 142 * If we're coming from user-space, then set sp to the top of 143 * the kernel stack. Otherwise, assume sp is already valid. 144 */ 145 { 146 bnz r0, 0f 147 move r0, sp 148 } 149 .endif 150 151 .ifc \c_routine, do_page_fault 152 /* 153 * The page_fault handler may be downcalled directly by the 154 * hypervisor even when Linux is running and has ICS set. 155 * 156 * In this case the contents of EX_CONTEXT_K_1 reflect the 157 * previous fault and can't be relied on to choose whether or 158 * not to reinitialize the stack pointer. So we add a test 159 * to see whether SYSTEM_SAVE_K_2 has the high bit set, 160 * and if so we don't reinitialize sp, since we must be coming 161 * from Linux. (In fact the precise case is !(val & ~1), 162 * but any Linux PC has to have the high bit set.) 163 * 164 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for 165 * any path that turns into a downcall to one of our TLB handlers. 166 */ 167 mfspr r0, SPR_SYSTEM_SAVE_K_2 168 { 169 blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */ 170 move r0, sp 171 } 172 .endif 173 1742: 175 /* 176 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and 177 * the current stack top in the higher bits. So we recover 178 * our stack top by just masking off the low bits, then 179 * point sp at the top aligned address on the actual stack page. 180 */ 181 mfspr r0, SPR_SYSTEM_SAVE_K_0 182 mm r0, r0, zero, LOG2_NR_CPU_IDS, 31 183 1840: 185 /* 186 * Align the stack mod 64 so we can properly predict what 187 * cache lines we need to write-hint to reduce memory fetch 188 * latency as we enter the kernel. The layout of memory is 189 * as follows, with cache line 0 at the lowest VA, and cache 190 * line 4 just below the r0 value this "andi" computes. 191 * Note that we never write to cache line 4, and we skip 192 * cache line 1 for syscalls. 193 * 194 * cache line 4: ptregs padding (two words) 195 * cache line 3: r46...lr, pc, ex1, faultnum, orig_r0, flags, pad 196 * cache line 2: r30...r45 197 * cache line 1: r14...r29 198 * cache line 0: 2 x frame, r0..r13 199 */ 200#if STACK_TOP_DELTA != 64 201#error STACK_TOP_DELTA must be 64 for assumptions here and in task_pt_regs() 202#endif 203 andi r0, r0, -64 204 205 /* 206 * Push the first four registers on the stack, so that we can set 207 * them to vector-unique values before we jump to the common code. 208 * 209 * Registers are pushed on the stack as a struct pt_regs, 210 * with the sp initially just above the struct, and when we're 211 * done, sp points to the base of the struct, minus 212 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code. 213 * 214 * This routine saves just the first four registers, plus the 215 * stack context so we can do proper backtracing right away, 216 * and defers to handle_interrupt to save the rest. 217 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum. 218 */ 219 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP) 220 wh64 r0 /* cache line 3 */ 221 { 222 sw r0, lr 223 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR 224 } 225 { 226 sw r0, sp 227 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP 228 } 229 { 230 sw sp, r52 231 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52) 232 } 233 wh64 sp /* cache line 0 */ 234 { 235 sw sp, r1 236 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1) 237 } 238 { 239 sw sp, r2 240 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2) 241 } 242 { 243 sw sp, r3 244 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3) 245 } 246 mfspr r0, SPR_EX_CONTEXT_K_0 247 .ifc \processing,handle_syscall 248 /* 249 * Bump the saved PC by one bundle so that when we return, we won't 250 * execute the same swint instruction again. We need to do this while 251 * we're in the critical section. 252 */ 253 addi r0, r0, 8 254 .endif 255 { 256 sw sp, r0 257 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC 258 } 259 mfspr r0, SPR_EX_CONTEXT_K_1 260 { 261 sw sp, r0 262 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1 263 /* 264 * Use r0 for syscalls so it's a temporary; use r1 for interrupts 265 * so that it gets passed through unchanged to the handler routine. 266 * Note that the .if conditional confusingly spans bundles. 267 */ 268 .ifc \processing,handle_syscall 269 movei r0, \vecnum 270 } 271 { 272 sw sp, r0 273 .else 274 movei r1, \vecnum 275 } 276 { 277 sw sp, r1 278 .endif 279 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM 280 } 281 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */ 282 { 283 sw sp, r0 284 addi sp, sp, -PTREGS_OFFSET_REG(0) - 4 285 } 286 { 287 sw sp, zero /* write zero into "Next SP" frame pointer */ 288 addi sp, sp, -4 /* leave SP pointing at bottom of frame */ 289 } 290 .ifc \processing,handle_syscall 291 j handle_syscall 292 .else 293 /* 294 * Capture per-interrupt SPR context to registers. 295 * We overload the meaning of r3 on this path such that if its bit 31 296 * is set, we have to mask all interrupts including NMIs before 297 * clearing the interrupt critical section bit. 298 * See discussion below at "finish_interrupt_save". 299 */ 300 .ifc \c_routine, do_page_fault 301 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */ 302 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */ 303 .else 304 .ifc \vecnum, INT_DOUBLE_FAULT 305 { 306 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */ 307 movei r3, 0 308 } 309 .else 310 .ifc \c_routine, do_trap 311 { 312 mfspr r2, GPV_REASON 313 movei r3, 0 314 } 315 .else 316 .ifc \c_routine, handle_perf_interrupt 317 { 318 mfspr r2, PERF_COUNT_STS 319 movei r3, -1 /* not used, but set for consistency */ 320 } 321 .else 322 .ifc \c_routine, handle_perf_interrupt 323 { 324 mfspr r2, AUX_PERF_COUNT_STS 325 movei r3, -1 /* not used, but set for consistency */ 326 } 327 .else 328 movei r3, 0 329 .endif 330 .endif 331 .endif 332 .endif 333 .endif 334 /* Put function pointer in r0 */ 335 moveli r0, lo16(\c_routine) 336 { 337 auli r0, r0, ha16(\c_routine) 338 j \processing 339 } 340 .endif 341 ENDPROC(intvec_\vecname) 342 343#ifdef __COLLECT_LINKER_FEEDBACK__ 344 .pushsection .text.intvec_feedback,"ax" 345 .org (\vecnum << 5) 346 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt, 1 << 8) 347 jrp lr 348 .popsection 349#endif 350 351 .endm 352 353 354 /* 355 * Save the rest of the registers that we didn't save in the actual 356 * vector itself. We can't use r0-r10 inclusive here. 357 */ 358 .macro finish_interrupt_save, function 359 360 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */ 361 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0) 362 { 363 .ifc \function,handle_syscall 364 sw r52, r0 365 .else 366 sw r52, zero 367 .endif 368 PTREGS_PTR(r52, PTREGS_OFFSET_TP) 369 } 370 371 /* 372 * For ordinary syscalls, we save neither caller- nor callee- 373 * save registers, since the syscall invoker doesn't expect the 374 * caller-saves to be saved, and the called kernel functions will 375 * take care of saving the callee-saves for us. 376 * 377 * For interrupts we save just the caller-save registers. Saving 378 * them is required (since the "caller" can't save them). Again, 379 * the called kernel functions will restore the callee-save 380 * registers for us appropriately. 381 * 382 * On return, we normally restore nothing special for syscalls, 383 * and just the caller-save registers for interrupts. 384 * 385 * However, there are some important caveats to all this: 386 * 387 * - We always save a few callee-save registers to give us 388 * some scratchpad registers to carry across function calls. 389 * 390 * - fork/vfork/etc require us to save all the callee-save 391 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below. 392 * 393 * - We always save r0..r5 and r10 for syscalls, since we need 394 * to reload them a bit later for the actual kernel call, and 395 * since we might need them for -ERESTARTNOINTR, etc. 396 * 397 * - Before invoking a signal handler, we save the unsaved 398 * callee-save registers so they are visible to the 399 * signal handler or any ptracer. 400 * 401 * - If the unsaved callee-save registers are modified, we set 402 * a bit in pt_regs so we know to reload them from pt_regs 403 * and not just rely on the kernel function unwinding. 404 * (Done for ptrace register writes and SA_SIGINFO handler.) 405 */ 406 { 407 sw r52, tp 408 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33)) 409 } 410 wh64 r52 /* cache line 2 */ 411 push_reg r33, r52 412 push_reg r32, r52 413 push_reg r31, r52 414 .ifc \function,handle_syscall 415 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30) 416 push_reg TREG_SYSCALL_NR_NAME, r52, \ 417 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL 418 .else 419 420 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30) 421 wh64 r52 /* cache line 1 */ 422 push_reg r29, r52 423 push_reg r28, r52 424 push_reg r27, r52 425 push_reg r26, r52 426 push_reg r25, r52 427 push_reg r24, r52 428 push_reg r23, r52 429 push_reg r22, r52 430 push_reg r21, r52 431 push_reg r20, r52 432 push_reg r19, r52 433 push_reg r18, r52 434 push_reg r17, r52 435 push_reg r16, r52 436 push_reg r15, r52 437 push_reg r14, r52 438 push_reg r13, r52 439 push_reg r12, r52 440 push_reg r11, r52 441 push_reg r10, r52 442 push_reg r9, r52 443 push_reg r8, r52 444 push_reg r7, r52 445 push_reg r6, r52 446 447 .endif 448 449 push_reg r5, r52 450 sw r52, r4 451 452 /* Load tp with our per-cpu offset. */ 453#ifdef CONFIG_SMP 454 { 455 mfspr r20, SPR_SYSTEM_SAVE_K_0 456 moveli r21, lo16(__per_cpu_offset) 457 } 458 { 459 auli r21, r21, ha16(__per_cpu_offset) 460 mm r20, r20, zero, 0, LOG2_NR_CPU_IDS-1 461 } 462 s2a r20, r20, r21 463 lw tp, r20 464#else 465 move tp, zero 466#endif 467 468 /* 469 * If we will be returning to the kernel, we will need to 470 * reset the interrupt masks to the state they had before. 471 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled. 472 * We load flags in r32 here so we can jump to .Lrestore_regs 473 * directly after do_page_fault_ics() if necessary. 474 */ 475 mfspr r32, SPR_EX_CONTEXT_K_1 476 { 477 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 478 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) 479 } 480 bzt r32, 1f /* zero if from user space */ 481 IRQS_DISABLED(r32) /* zero if irqs enabled */ 482#if PT_FLAGS_DISABLE_IRQ != 1 483# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix 484#endif 4851: 486 .ifnc \function,handle_syscall 487 /* Record the fact that we saved the caller-save registers above. */ 488 ori r32, r32, PT_FLAGS_CALLER_SAVES 489 .endif 490 sw r21, r32 491 492#ifdef __COLLECT_LINKER_FEEDBACK__ 493 /* 494 * Notify the feedback routines that we were in the 495 * appropriate fixed interrupt vector area. Note that we 496 * still have ICS set at this point, so we can't invoke any 497 * atomic operations or we will panic. The feedback 498 * routines internally preserve r0..r10 and r30 up. 499 */ 500 .ifnc \function,handle_syscall 501 shli r20, r1, 5 502 .else 503 moveli r20, INT_SWINT_1 << 5 504 .endif 505 addli r20, r20, lo16(intvec_feedback) 506 auli r20, r20, ha16(intvec_feedback) 507 jalr r20 508 509 /* And now notify the feedback routines that we are here. */ 510 FEEDBACK_ENTER(\function) 511#endif 512 513 /* 514 * we've captured enough state to the stack (including in 515 * particular our EX_CONTEXT state) that we can now release 516 * the interrupt critical section and replace it with our 517 * standard "interrupts disabled" mask value. This allows 518 * synchronous interrupts (and profile interrupts) to punch 519 * through from this point onwards. 520 * 521 * If bit 31 of r3 is set during a non-NMI interrupt, we know we 522 * are on the path where the hypervisor has punched through our 523 * ICS with a page fault, so we call out to do_page_fault_ics() 524 * to figure out what to do with it. If the fault was in 525 * an atomic op, we unlock the atomic lock, adjust the 526 * saved register state a little, and return "zero" in r4, 527 * falling through into the normal page-fault interrupt code. 528 * If the fault was in a kernel-space atomic operation, then 529 * do_page_fault_ics() resolves it itself, returns "one" in r4, 530 * and as a result goes directly to restoring registers and iret, 531 * without trying to adjust the interrupt masks at all. 532 * The do_page_fault_ics() API involves passing and returning 533 * a five-word struct (in registers) to avoid writing the 534 * save and restore code here. 535 */ 536 .ifc \function,handle_nmi 537 IRQ_DISABLE_ALL(r20) 538 .else 539 .ifnc \function,handle_syscall 540 bgezt r3, 1f 541 { 542 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 543 jal do_page_fault_ics 544 } 545 FEEDBACK_REENTER(\function) 546 bzt r4, 1f 547 j .Lrestore_regs 5481: 549 .endif 550 IRQ_DISABLE(r20, r21) 551 .endif 552 mtspr INTERRUPT_CRITICAL_SECTION, zero 553 554 /* 555 * Prepare the first 256 stack bytes to be rapidly accessible 556 * without having to fetch the background data. We don't really 557 * know how far to write-hint, but kernel stacks generally 558 * aren't that big, and write-hinting here does take some time. 559 */ 560 addi r52, sp, -64 561 { 562 wh64 r52 563 addi r52, r52, -64 564 } 565 { 566 wh64 r52 567 addi r52, r52, -64 568 } 569 { 570 wh64 r52 571 addi r52, r52, -64 572 } 573 wh64 r52 574 575#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING) 576 .ifnc \function,handle_nmi 577 /* 578 * We finally have enough state set up to notify the irq 579 * tracing code that irqs were disabled on entry to the handler. 580 * The TRACE_IRQS_OFF call clobbers registers r0-r29. 581 * For syscalls, we already have the register state saved away 582 * on the stack, so we don't bother to do any register saves here, 583 * and later we pop the registers back off the kernel stack. 584 * For interrupt handlers, save r0-r3 in callee-saved registers. 585 */ 586 .ifnc \function,handle_syscall 587 { move r30, r0; move r31, r1 } 588 { move r32, r2; move r33, r3 } 589 .endif 590 TRACE_IRQS_OFF 591#ifdef CONFIG_CONTEXT_TRACKING 592 jal context_tracking_user_exit 593#endif 594 .ifnc \function,handle_syscall 595 { move r0, r30; move r1, r31 } 596 { move r2, r32; move r3, r33 } 597 .endif 598 .endif 599#endif 600 601 .endm 602 603 .macro check_single_stepping, kind, not_single_stepping 604 /* 605 * Check for single stepping in user-level priv 606 * kind can be "normal", "ill", or "syscall" 607 * At end, if fall-thru 608 * r29: thread_info->step_state 609 * r28: &pt_regs->pc 610 * r27: pt_regs->pc 611 * r26: thread_info->step_state->buffer 612 */ 613 614 /* Check for single stepping */ 615 GET_THREAD_INFO(r29) 616 { 617 /* Get pointer to field holding step state */ 618 addi r29, r29, THREAD_INFO_STEP_STATE_OFFSET 619 620 /* Get pointer to EX1 in register state */ 621 PTREGS_PTR(r27, PTREGS_OFFSET_EX1) 622 } 623 { 624 /* Get pointer to field holding PC */ 625 PTREGS_PTR(r28, PTREGS_OFFSET_PC) 626 627 /* Load the pointer to the step state */ 628 lw r29, r29 629 } 630 /* Load EX1 */ 631 lw r27, r27 632 { 633 /* Points to flags */ 634 addi r23, r29, SINGLESTEP_STATE_FLAGS_OFFSET 635 636 /* No single stepping if there is no step state structure */ 637 bzt r29, \not_single_stepping 638 } 639 { 640 /* mask off ICS and any other high bits */ 641 andi r27, r27, SPR_EX_CONTEXT_1_1__PL_MASK 642 643 /* Load pointer to single step instruction buffer */ 644 lw r26, r29 645 } 646 /* Check priv state */ 647 bnz r27, \not_single_stepping 648 649 /* Get flags */ 650 lw r22, r23 651 { 652 /* Branch if single-step mode not enabled */ 653 bbnst r22, \not_single_stepping 654 655 /* Clear enabled flag */ 656 andi r22, r22, ~SINGLESTEP_STATE_MASK_IS_ENABLED 657 } 658 .ifc \kind,normal 659 { 660 /* Load PC */ 661 lw r27, r28 662 663 /* Point to the entry containing the original PC */ 664 addi r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET 665 } 666 { 667 /* Disable single stepping flag */ 668 sw r23, r22 669 } 670 { 671 /* Get the original pc */ 672 lw r24, r24 673 674 /* See if the PC is at the start of the single step buffer */ 675 seq r25, r26, r27 676 } 677 /* 678 * NOTE: it is really expected that the PC be in the single step buffer 679 * at this point 680 */ 681 bzt r25, \not_single_stepping 682 683 /* Restore the original PC */ 684 sw r28, r24 685 .else 686 .ifc \kind,syscall 687 { 688 /* Load PC */ 689 lw r27, r28 690 691 /* Point to the entry containing the next PC */ 692 addi r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET 693 } 694 { 695 /* Increment the stopped PC by the bundle size */ 696 addi r26, r26, 8 697 698 /* Disable single stepping flag */ 699 sw r23, r22 700 } 701 { 702 /* Get the next pc */ 703 lw r24, r24 704 705 /* 706 * See if the PC is one bundle past the start of the 707 * single step buffer 708 */ 709 seq r25, r26, r27 710 } 711 { 712 /* 713 * NOTE: it is really expected that the PC be in the 714 * single step buffer at this point 715 */ 716 bzt r25, \not_single_stepping 717 } 718 /* Set to the next PC */ 719 sw r28, r24 720 .else 721 { 722 /* Point to 3rd bundle in buffer */ 723 addi r25, r26, 16 724 725 /* Load PC */ 726 lw r27, r28 727 } 728 { 729 /* Disable single stepping flag */ 730 sw r23, r22 731 732 /* See if the PC is in the single step buffer */ 733 slte_u r24, r26, r27 734 } 735 { 736 slte_u r25, r27, r25 737 738 /* 739 * NOTE: it is really expected that the PC be in the 740 * single step buffer at this point 741 */ 742 bzt r24, \not_single_stepping 743 } 744 bzt r25, \not_single_stepping 745 .endif 746 .endif 747 .endm 748 749 /* 750 * Redispatch a downcall. 751 */ 752 .macro dc_dispatch vecnum, vecname 753 .org (\vecnum << 8) 754intvec_\vecname: 755 j _hv_downcall_dispatch 756 ENDPROC(intvec_\vecname) 757 .endm 758 759 /* 760 * Common code for most interrupts. The C function we're eventually 761 * going to is in r0, and the faultnum is in r1; the original 762 * values for those registers are on the stack. 763 */ 764 .pushsection .text.handle_interrupt,"ax" 765handle_interrupt: 766 finish_interrupt_save handle_interrupt 767 768 /* 769 * Check for if we are single stepping in user level. If so, then 770 * we need to restore the PC. 771 */ 772 773 check_single_stepping normal, .Ldispatch_interrupt 774.Ldispatch_interrupt: 775 776 /* Jump to the C routine; it should enable irqs as soon as possible. */ 777 { 778 jalr r0 779 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 780 } 781 FEEDBACK_REENTER(handle_interrupt) 782 { 783 movei r30, 0 /* not an NMI */ 784 j interrupt_return 785 } 786 STD_ENDPROC(handle_interrupt) 787 788/* 789 * This routine takes a boolean in r30 indicating if this is an NMI. 790 * If so, we also expect a boolean in r31 indicating whether to 791 * re-enable the oprofile interrupts. 792 * 793 * Note that .Lresume_userspace is jumped to directly in several 794 * places, and we need to make sure r30 is set correctly in those 795 * callers as well. 796 */ 797STD_ENTRY(interrupt_return) 798 /* If we're resuming to kernel space, don't check thread flags. */ 799 { 800 bnz r30, .Lrestore_all /* NMIs don't special-case user-space */ 801 PTREGS_PTR(r29, PTREGS_OFFSET_EX1) 802 } 803 lw r29, r29 804 andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 805 bzt r29, .Lresume_userspace 806 807#ifdef CONFIG_PREEMPT 808 /* Returning to kernel space. Check if we need preemption. */ 809 GET_THREAD_INFO(r29) 810 addli r28, r29, THREAD_INFO_FLAGS_OFFSET 811 { 812 lw r28, r28 813 addli r29, r29, THREAD_INFO_PREEMPT_COUNT_OFFSET 814 } 815 { 816 andi r28, r28, _TIF_NEED_RESCHED 817 lw r29, r29 818 } 819 bzt r28, 1f 820 bnz r29, 1f 821 /* Disable interrupts explicitly for preemption. */ 822 IRQ_DISABLE(r20,r21) 823 TRACE_IRQS_OFF 824 jal preempt_schedule_irq 825 FEEDBACK_REENTER(interrupt_return) 8261: 827#endif 828 829 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */ 830 { 831 PTREGS_PTR(r29, PTREGS_OFFSET_PC) 832 moveli r27, lo16(_cpu_idle_nap) 833 } 834 { 835 lw r28, r29 836 auli r27, r27, ha16(_cpu_idle_nap) 837 } 838 { 839 seq r27, r27, r28 840 } 841 { 842 bbns r27, .Lrestore_all 843 addi r28, r28, 8 844 } 845 sw r29, r28 846 j .Lrestore_all 847 848.Lresume_userspace: 849 FEEDBACK_REENTER(interrupt_return) 850 851 /* 852 * Disable interrupts so as to make sure we don't 853 * miss an interrupt that sets any of the thread flags (like 854 * need_resched or sigpending) between sampling and the iret. 855 * Routines like schedule() or do_signal() may re-enable 856 * interrupts before returning. 857 */ 858 IRQ_DISABLE(r20, r21) 859 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */ 860 861 /* 862 * See if there are any work items (including single-shot items) 863 * to do. If so, save the callee-save registers to pt_regs 864 * and then dispatch to C code. 865 */ 866 GET_THREAD_INFO(r21) 867 { 868 addi r22, r21, THREAD_INFO_FLAGS_OFFSET 869 moveli r20, lo16(_TIF_ALLWORK_MASK) 870 } 871 { 872 lw r22, r22 873 auli r20, r20, ha16(_TIF_ALLWORK_MASK) 874 } 875 and r1, r22, r20 876 { 877 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 878 bzt r1, .Lrestore_all 879 } 880 push_extra_callee_saves r0 881 jal prepare_exit_to_usermode 882 883 /* 884 * In the NMI case we 885 * omit the call to single_process_check_nohz, which normally checks 886 * to see if we should start or stop the scheduler tick, because 887 * we can't call arbitrary Linux code from an NMI context. 888 * We always call the homecache TLB deferral code to re-trigger 889 * the deferral mechanism. 890 * 891 * The other chunk of responsibility this code has is to reset the 892 * interrupt masks appropriately to reset irqs and NMIs. We have 893 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the 894 * lockdep-type stuff, but we can't set ICS until afterwards, since 895 * ICS can only be used in very tight chunks of code to avoid 896 * tripping over various assertions that it is off. 897 * 898 * (There is what looks like a window of vulnerability here since 899 * we might take a profile interrupt between the two SPR writes 900 * that set the mask, but since we write the low SPR word first, 901 * and our interrupt entry code checks the low SPR word, any 902 * profile interrupt will actually disable interrupts in both SPRs 903 * before returning, which is OK.) 904 */ 905.Lrestore_all: 906 PTREGS_PTR(r0, PTREGS_OFFSET_EX1) 907 { 908 lw r0, r0 909 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS) 910 } 911 { 912 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK 913 lw r32, r32 914 } 915 bnz r0, 1f 916 j 2f 917#if PT_FLAGS_DISABLE_IRQ != 1 918# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use bbnst below 919#endif 9201: bbnst r32, 2f 921 IRQ_DISABLE(r20,r21) 922 TRACE_IRQS_OFF 923 movei r0, 1 924 mtspr INTERRUPT_CRITICAL_SECTION, r0 925 bzt r30, .Lrestore_regs 926 j 3f 9272: TRACE_IRQS_ON 928 movei r0, 1 929 mtspr INTERRUPT_CRITICAL_SECTION, r0 930 IRQ_ENABLE(r20, r21) 931 bzt r30, .Lrestore_regs 9323: 933 934 /* We are relying on INT_PERF_COUNT at 33, and AUX_PERF_COUNT at 48 */ 935 { 936 moveli r0, lo16(1 << (INT_PERF_COUNT - 32)) 937 bz r31, .Lrestore_regs 938 } 939 auli r0, r0, ha16(1 << (INT_AUX_PERF_COUNT - 32)) 940 mtspr SPR_INTERRUPT_MASK_RESET_K_1, r0 941 942 /* 943 * We now commit to returning from this interrupt, since we will be 944 * doing things like setting EX_CONTEXT SPRs and unwinding the stack 945 * frame. No calls should be made to any other code after this point. 946 * This code should only be entered with ICS set. 947 * r32 must still be set to ptregs.flags. 948 * We launch loads to each cache line separately first, so we can 949 * get some parallelism out of the memory subsystem. 950 * We start zeroing caller-saved registers throughout, since 951 * that will save some cycles if this turns out to be a syscall. 952 */ 953.Lrestore_regs: 954 FEEDBACK_REENTER(interrupt_return) /* called from elsewhere */ 955 956 /* 957 * Rotate so we have one high bit and one low bit to test. 958 * - low bit says whether to restore all the callee-saved registers, 959 * or just r30-r33, and r52 up. 960 * - high bit (i.e. sign bit) says whether to restore all the 961 * caller-saved registers, or just r0. 962 */ 963#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4 964# error Rotate trick does not work :-) 965#endif 966 { 967 rli r20, r32, 30 968 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0)) 969 } 970 971 /* 972 * Load cache lines 0, 2, and 3 in that order, then use 973 * the last loaded value, which makes it likely that the other 974 * cache lines have also loaded, at which point we should be 975 * able to safely read all the remaining words on those cache 976 * lines without waiting for the memory subsystem. 977 */ 978 pop_reg_zero r0, r28, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0) 979 pop_reg_zero r30, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(30) 980 pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC 981 pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1 982 { 983 mtspr SPR_EX_CONTEXT_K_0, r21 984 move r5, zero 985 } 986 { 987 mtspr SPR_EX_CONTEXT_K_1, lr 988 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 989 } 990 991 /* Restore callee-saveds that we actually use. */ 992 pop_reg_zero r52, r6, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_REG(52) 993 pop_reg_zero r31, r7 994 pop_reg_zero r32, r8 995 pop_reg_zero r33, r9, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33) 996 997 /* 998 * If we modified other callee-saveds, restore them now. 999 * This is rare, but could be via ptrace or signal handler. 1000 */ 1001 { 1002 move r10, zero 1003 bbs r20, .Lrestore_callees 1004 } 1005.Lcontinue_restore_regs: 1006 1007 /* Check if we're returning from a syscall. */ 1008 { 1009 move r11, zero 1010 blzt r20, 1f /* no, so go restore callee-save registers */ 1011 } 1012 1013 /* 1014 * Check if we're returning to userspace. 1015 * Note that if we're not, we don't worry about zeroing everything. 1016 */ 1017 { 1018 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29) 1019 bnz lr, .Lkernel_return 1020 } 1021 1022 /* 1023 * On return from syscall, we've restored r0 from pt_regs, but we 1024 * clear the remainder of the caller-saved registers. We could 1025 * restore the syscall arguments, but there's not much point, 1026 * and it ensures user programs aren't trying to use the 1027 * caller-saves if we clear them, as well as avoiding leaking 1028 * kernel pointers into userspace. 1029 */ 1030 pop_reg_zero lr, r12, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR 1031 pop_reg_zero tp, r13, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP 1032 { 1033 lw sp, sp 1034 move r14, zero 1035 move r15, zero 1036 } 1037 { move r16, zero; move r17, zero } 1038 { move r18, zero; move r19, zero } 1039 { move r20, zero; move r21, zero } 1040 { move r22, zero; move r23, zero } 1041 { move r24, zero; move r25, zero } 1042 { move r26, zero; move r27, zero } 1043 1044 /* Set r1 to errno if we are returning an error, otherwise zero. */ 1045 { 1046 moveli r29, 4096 1047 sub r1, zero, r0 1048 } 1049 slt_u r29, r1, r29 1050 { 1051 mnz r1, r29, r1 1052 move r29, zero 1053 } 1054 iret 1055 1056 /* 1057 * Not a syscall, so restore caller-saved registers. 1058 * First kick off a load for cache line 1, which we're touching 1059 * for the first time here. 1060 */ 1061 .align 64 10621: pop_reg r29, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(29) 1063 pop_reg r1 1064 pop_reg r2 1065 pop_reg r3 1066 pop_reg r4 1067 pop_reg r5 1068 pop_reg r6 1069 pop_reg r7 1070 pop_reg r8 1071 pop_reg r9 1072 pop_reg r10 1073 pop_reg r11 1074 pop_reg r12 1075 pop_reg r13 1076 pop_reg r14 1077 pop_reg r15 1078 pop_reg r16 1079 pop_reg r17 1080 pop_reg r18 1081 pop_reg r19 1082 pop_reg r20 1083 pop_reg r21 1084 pop_reg r22 1085 pop_reg r23 1086 pop_reg r24 1087 pop_reg r25 1088 pop_reg r26 1089 pop_reg r27 1090 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28) 1091 /* r29 already restored above */ 1092 bnz lr, .Lkernel_return 1093 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR 1094 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP 1095 lw sp, sp 1096 iret 1097 1098 /* 1099 * We can't restore tp when in kernel mode, since a thread might 1100 * have migrated from another cpu and brought a stale tp value. 1101 */ 1102.Lkernel_return: 1103 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR 1104 lw sp, sp 1105 iret 1106 1107 /* Restore callee-saved registers from r34 to r51. */ 1108.Lrestore_callees: 1109 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29) 1110 pop_reg r34 1111 pop_reg r35 1112 pop_reg r36 1113 pop_reg r37 1114 pop_reg r38 1115 pop_reg r39 1116 pop_reg r40 1117 pop_reg r41 1118 pop_reg r42 1119 pop_reg r43 1120 pop_reg r44 1121 pop_reg r45 1122 pop_reg r46 1123 pop_reg r47 1124 pop_reg r48 1125 pop_reg r49 1126 pop_reg r50 1127 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51) 1128 j .Lcontinue_restore_regs 1129 STD_ENDPROC(interrupt_return) 1130 1131 /* 1132 * Some interrupts don't check for single stepping 1133 */ 1134 .pushsection .text.handle_interrupt_no_single_step,"ax" 1135handle_interrupt_no_single_step: 1136 finish_interrupt_save handle_interrupt_no_single_step 1137 { 1138 jalr r0 1139 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1140 } 1141 FEEDBACK_REENTER(handle_interrupt_no_single_step) 1142 { 1143 movei r30, 0 /* not an NMI */ 1144 j interrupt_return 1145 } 1146 STD_ENDPROC(handle_interrupt_no_single_step) 1147 1148 /* 1149 * "NMI" interrupts mask ALL interrupts before calling the 1150 * handler, and don't check thread flags, etc., on the way 1151 * back out. In general, the only things we do here for NMIs 1152 * are the register save/restore, fixing the PC if we were 1153 * doing single step, and the dataplane kernel-TLB management. 1154 * We don't (for example) deal with start/stop of the sched tick. 1155 */ 1156 .pushsection .text.handle_nmi,"ax" 1157handle_nmi: 1158 finish_interrupt_save handle_nmi 1159 check_single_stepping normal, .Ldispatch_nmi 1160.Ldispatch_nmi: 1161 { 1162 jalr r0 1163 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1164 } 1165 FEEDBACK_REENTER(handle_nmi) 1166 { 1167 movei r30, 1 1168 seq r31, r0, zero 1169 } 1170 j interrupt_return 1171 STD_ENDPROC(handle_nmi) 1172 1173 /* 1174 * Parallel code for syscalls to handle_interrupt. 1175 */ 1176 .pushsection .text.handle_syscall,"ax" 1177handle_syscall: 1178 finish_interrupt_save handle_syscall 1179 1180 /* 1181 * Check for if we are single stepping in user level. If so, then 1182 * we need to restore the PC. 1183 */ 1184 check_single_stepping syscall, .Ldispatch_syscall 1185.Ldispatch_syscall: 1186 1187 /* Enable irqs. */ 1188 TRACE_IRQS_ON 1189 IRQ_ENABLE(r20, r21) 1190 1191 /* Bump the counter for syscalls made on this tile. */ 1192 moveli r20, lo16(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) 1193 auli r20, r20, ha16(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) 1194 add r20, r20, tp 1195 lw r21, r20 1196 addi r21, r21, 1 1197 { 1198 sw r20, r21 1199 GET_THREAD_INFO(r31) 1200 } 1201 1202 /* Trace syscalls, if requested. */ 1203 addi r31, r31, THREAD_INFO_FLAGS_OFFSET 1204 lw r30, r31 1205 andi r30, r30, _TIF_SYSCALL_TRACE 1206 bzt r30, .Lrestore_syscall_regs 1207 { 1208 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1209 jal do_syscall_trace_enter 1210 } 1211 FEEDBACK_REENTER(handle_syscall) 1212 blz r0, .Lsyscall_sigreturn_skip 1213 1214 /* 1215 * We always reload our registers from the stack at this 1216 * point. They might be valid, if we didn't build with 1217 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not 1218 * doing syscall tracing, but there are enough cases now that it 1219 * seems simplest just to do the reload unconditionally. 1220 */ 1221.Lrestore_syscall_regs: 1222 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0)) 1223 pop_reg r0, r11 1224 pop_reg r1, r11 1225 pop_reg r2, r11 1226 pop_reg r3, r11 1227 pop_reg r4, r11 1228 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5) 1229 pop_reg TREG_SYSCALL_NR_NAME, r11 1230 1231 /* Ensure that the syscall number is within the legal range. */ 1232 moveli r21, __NR_syscalls 1233 { 1234 slt_u r21, TREG_SYSCALL_NR_NAME, r21 1235 moveli r20, lo16(sys_call_table) 1236 } 1237 { 1238 bbns r21, .Linvalid_syscall 1239 auli r20, r20, ha16(sys_call_table) 1240 } 1241 s2a r20, TREG_SYSCALL_NR_NAME, r20 1242 lw r20, r20 1243 1244 /* Jump to syscall handler. */ 1245 jalr r20 1246.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */ 1247 1248 /* 1249 * Write our r0 onto the stack so it gets restored instead 1250 * of whatever the user had there before. 1251 */ 1252 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) 1253 sw r29, r0 1254 1255.Lsyscall_sigreturn_skip: 1256 FEEDBACK_REENTER(handle_syscall) 1257 1258 /* Do syscall trace again, if requested. */ 1259 lw r30, r31 1260 andi r30, r30, _TIF_SYSCALL_TRACE 1261 bzt r30, 1f 1262 { 1263 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1264 jal do_syscall_trace_exit 1265 } 1266 FEEDBACK_REENTER(handle_syscall) 12671: { 1268 movei r30, 0 /* not an NMI */ 1269 j .Lresume_userspace /* jump into middle of interrupt_return */ 1270 } 1271 1272.Linvalid_syscall: 1273 /* Report an invalid syscall back to the user program */ 1274 { 1275 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) 1276 movei r28, -ENOSYS 1277 } 1278 sw r29, r28 1279 { 1280 movei r30, 0 /* not an NMI */ 1281 j .Lresume_userspace /* jump into middle of interrupt_return */ 1282 } 1283 STD_ENDPROC(handle_syscall) 1284 1285 /* Return the address for oprofile to suppress in backtraces. */ 1286STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall) 1287 lnk r0 1288 { 1289 addli r0, r0, .Lhandle_syscall_link - . 1290 jrp lr 1291 } 1292 STD_ENDPROC(handle_syscall_link_address) 1293 1294STD_ENTRY(ret_from_fork) 1295 jal sim_notify_fork 1296 jal schedule_tail 1297 FEEDBACK_REENTER(ret_from_fork) 1298 { 1299 movei r30, 0 /* not an NMI */ 1300 j .Lresume_userspace /* jump into middle of interrupt_return */ 1301 } 1302 STD_ENDPROC(ret_from_fork) 1303 1304STD_ENTRY(ret_from_kernel_thread) 1305 jal sim_notify_fork 1306 jal schedule_tail 1307 FEEDBACK_REENTER(ret_from_fork) 1308 { 1309 move r0, r31 1310 jalr r30 1311 } 1312 FEEDBACK_REENTER(ret_from_kernel_thread) 1313 { 1314 movei r30, 0 /* not an NMI */ 1315 j interrupt_return 1316 } 1317 STD_ENDPROC(ret_from_kernel_thread) 1318 1319 /* 1320 * Code for ill interrupt. 1321 */ 1322 .pushsection .text.handle_ill,"ax" 1323handle_ill: 1324 finish_interrupt_save handle_ill 1325 1326 /* 1327 * Check for if we are single stepping in user level. If so, then 1328 * we need to restore the PC. 1329 */ 1330 check_single_stepping ill, .Ldispatch_normal_ill 1331 1332 { 1333 /* See if the PC is the 1st bundle in the buffer */ 1334 seq r25, r27, r26 1335 1336 /* Point to the 2nd bundle in the buffer */ 1337 addi r26, r26, 8 1338 } 1339 { 1340 /* Point to the original pc */ 1341 addi r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET 1342 1343 /* Branch if the PC is the 1st bundle in the buffer */ 1344 bnz r25, 3f 1345 } 1346 { 1347 /* See if the PC is the 2nd bundle of the buffer */ 1348 seq r25, r27, r26 1349 1350 /* Set PC to next instruction */ 1351 addi r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET 1352 } 1353 { 1354 /* Point to flags */ 1355 addi r25, r29, SINGLESTEP_STATE_FLAGS_OFFSET 1356 1357 /* Branch if PC is in the second bundle */ 1358 bz r25, 2f 1359 } 1360 /* Load flags */ 1361 lw r25, r25 1362 { 1363 /* 1364 * Get the offset for the register to restore 1365 * Note: the lower bound is 2, so we have implicit scaling by 4. 1366 * No multiplication of the register number by the size of a register 1367 * is needed. 1368 */ 1369 mm r27, r25, zero, SINGLESTEP_STATE_TARGET_LB, \ 1370 SINGLESTEP_STATE_TARGET_UB 1371 1372 /* Mask Rewrite_LR */ 1373 andi r25, r25, SINGLESTEP_STATE_MASK_UPDATE 1374 } 1375 { 1376 addi r29, r29, SINGLESTEP_STATE_UPDATE_VALUE_OFFSET 1377 1378 /* Don't rewrite temp register */ 1379 bz r25, 3f 1380 } 1381 { 1382 /* Get the temp value */ 1383 lw r29, r29 1384 1385 /* Point to where the register is stored */ 1386 add r27, r27, sp 1387 } 1388 1389 /* Add in the C ABI save area size to the register offset */ 1390 addi r27, r27, C_ABI_SAVE_AREA_SIZE 1391 1392 /* Restore the user's register with the temp value */ 1393 sw r27, r29 1394 j 3f 1395 13962: 1397 /* Must be in the third bundle */ 1398 addi r24, r29, SINGLESTEP_STATE_BRANCH_NEXT_PC_OFFSET 1399 14003: 1401 /* set PC and continue */ 1402 lw r26, r24 1403 { 1404 sw r28, r26 1405 GET_THREAD_INFO(r0) 1406 } 1407 1408 /* 1409 * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill. 1410 * The normal non-arch flow redundantly clears TIF_SINGLESTEP, but we 1411 * need to clear it here and can't really impose on all other arches. 1412 * So what's another write between friends? 1413 */ 1414 1415 addi r1, r0, THREAD_INFO_FLAGS_OFFSET 1416 { 1417 lw r2, r1 1418 addi r0, r0, THREAD_INFO_TASK_OFFSET /* currently a no-op */ 1419 } 1420 andi r2, r2, ~_TIF_SINGLESTEP 1421 sw r1, r2 1422 1423 /* Issue a sigtrap */ 1424 { 1425 lw r0, r0 /* indirect thru thread_info to get task_info*/ 1426 addi r1, sp, C_ABI_SAVE_AREA_SIZE /* put ptregs pointer into r1 */ 1427 } 1428 1429 jal send_sigtrap /* issue a SIGTRAP */ 1430 FEEDBACK_REENTER(handle_ill) 1431 { 1432 movei r30, 0 /* not an NMI */ 1433 j .Lresume_userspace /* jump into middle of interrupt_return */ 1434 } 1435 1436.Ldispatch_normal_ill: 1437 { 1438 jalr r0 1439 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1440 } 1441 FEEDBACK_REENTER(handle_ill) 1442 { 1443 movei r30, 0 /* not an NMI */ 1444 j interrupt_return 1445 } 1446 STD_ENDPROC(handle_ill) 1447 1448/* Various stub interrupt handlers and syscall handlers */ 1449 1450STD_ENTRY_LOCAL(_kernel_double_fault) 1451 mfspr r1, SPR_EX_CONTEXT_K_0 1452 move r2, lr 1453 move r3, sp 1454 move r4, r52 1455 addi sp, sp, -C_ABI_SAVE_AREA_SIZE 1456 j kernel_double_fault 1457 STD_ENDPROC(_kernel_double_fault) 1458 1459STD_ENTRY_LOCAL(bad_intr) 1460 mfspr r2, SPR_EX_CONTEXT_K_0 1461 panic "Unhandled interrupt %#x: PC %#lx" 1462 STD_ENDPROC(bad_intr) 1463 1464/* 1465 * Special-case sigreturn to not write r0 to the stack on return. 1466 * This is technically more efficient, but it also avoids difficulties 1467 * in the 64-bit OS when handling 32-bit compat code, since we must not 1468 * sign-extend r0 for the sigreturn return-value case. 1469 */ 1470#define PTREGS_SYSCALL_SIGRETURN(x, reg) \ 1471 STD_ENTRY(_##x); \ 1472 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \ 1473 { \ 1474 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \ 1475 j x \ 1476 }; \ 1477 STD_ENDPROC(_##x) 1478 1479PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0) 1480 1481/* Save additional callee-saves to pt_regs and jump to standard function. */ 1482STD_ENTRY(_sys_clone) 1483 push_extra_callee_saves r4 1484 j sys_clone 1485 STD_ENDPROC(_sys_clone) 1486 1487/* 1488 * This entrypoint is taken for the cmpxchg and atomic_update fast 1489 * swints. We may wish to generalize it to other fast swints at some 1490 * point, but for now there are just two very similar ones, which 1491 * makes it faster. 1492 * 1493 * The fast swint code is designed to have a small footprint. It does 1494 * not save or restore any GPRs, counting on the caller-save registers 1495 * to be available to it on entry. It does not modify any callee-save 1496 * registers (including "lr"). It does not check what PL it is being 1497 * called at, so you'd better not call it other than at PL0. 1498 * The <atomic.h> wrapper assumes it only clobbers r20-r29, so if 1499 * it ever is necessary to use more registers, be aware. 1500 * 1501 * It does not use the stack, but since it might be re-interrupted by 1502 * a page fault which would assume the stack was valid, it does 1503 * save/restore the stack pointer and zero it out to make sure it gets reset. 1504 * Since we always keep interrupts disabled, the hypervisor won't 1505 * clobber our EX_CONTEXT_K_x registers, so we don't save/restore them 1506 * (other than to advance the PC on return). 1507 * 1508 * We have to manually validate the user vs kernel address range 1509 * (since at PL1 we can read/write both), and for performance reasons 1510 * we don't allow cmpxchg on the fc000000 memory region, since we only 1511 * validate that the user address is below PAGE_OFFSET. 1512 * 1513 * We place it in the __HEAD section to ensure it is relatively 1514 * near to the intvec_SWINT_1 code (reachable by a conditional branch). 1515 * 1516 * Our use of ATOMIC_LOCK_REG here must match do_page_fault_ics(). 1517 * 1518 * As we do in lib/atomic_asm_32.S, we bypass a store if the value we 1519 * would store is the same as the value we just loaded. 1520 */ 1521 __HEAD 1522 .align 64 1523 /* Align much later jump on the start of a cache line. */ 1524 nop 1525#if PAGE_SIZE >= 0x10000 1526 nop 1527#endif 1528ENTRY(sys_cmpxchg) 1529 1530 /* 1531 * Save "sp" and set it zero for any possible page fault. 1532 * 1533 * HACK: We want to both zero sp and check r0's alignment, 1534 * so we do both at once. If "sp" becomes nonzero we 1535 * know r0 is unaligned and branch to the error handler that 1536 * restores sp, so this is OK. 1537 * 1538 * ICS is disabled right now so having a garbage but nonzero 1539 * sp is OK, since we won't execute any faulting instructions 1540 * when it is nonzero. 1541 */ 1542 { 1543 move r27, sp 1544 andi sp, r0, 3 1545 } 1546 1547 /* 1548 * Get the lock address in ATOMIC_LOCK_REG, and also validate that the 1549 * address is less than PAGE_OFFSET, since that won't trap at PL1. 1550 * We only use bits less than PAGE_SHIFT to avoid having to worry 1551 * about aliasing among multiple mappings of the same physical page, 1552 * and we ignore the low 3 bits so we have one lock that covers 1553 * both a cmpxchg64() and a cmpxchg() on either its low or high word. 1554 * NOTE: this must match __atomic_hashed_lock() in lib/atomic_32.c. 1555 */ 1556 1557#if (PAGE_OFFSET & 0xffff) != 0 1558# error Code here assumes PAGE_OFFSET can be loaded with just hi16() 1559#endif 1560 1561 { 1562 /* Check for unaligned input. */ 1563 bnz sp, .Lcmpxchg_badaddr 1564 auli r23, zero, hi16(PAGE_OFFSET) /* hugepage-aligned */ 1565 } 1566 { 1567 /* 1568 * Slide bits into position for 'mm'. We want to ignore 1569 * the low 3 bits of r0, and consider only the next 1570 * ATOMIC_HASH_SHIFT bits. 1571 * Because of C pointer arithmetic, we want to compute this: 1572 * 1573 * ((char*)atomic_locks + 1574 * (((r0 >> 3) & ((1 << ATOMIC_HASH_SHIFT) - 1)) << 2)) 1575 * 1576 * Instead of two shifts we just ">> 1", and use 'mm' 1577 * to ignore the low and high bits we don't want. 1578 */ 1579 shri r25, r0, 1 1580 1581 slt_u r23, r0, r23 1582 1583 /* 1584 * Ensure that the TLB is loaded before we take out the lock. 1585 * This will start fetching the value all the way into our L1 1586 * as well (and if it gets modified before we grab the lock, 1587 * it will be invalidated from our cache before we reload it). 1588 */ 1589 lw r26, r0 1590 } 1591 { 1592 auli r21, zero, ha16(atomic_locks) 1593 1594 bbns r23, .Lcmpxchg_badaddr 1595 } 1596#if PAGE_SIZE < 0x10000 1597 /* atomic_locks is page-aligned so for big pages we don't need this. */ 1598 addli r21, r21, lo16(atomic_locks) 1599#endif 1600 { 1601 /* 1602 * Insert the hash bits into the page-aligned pointer. 1603 * ATOMIC_HASH_SHIFT is so big that we don't actually hash 1604 * the unmasked address bits, as that may cause unnecessary 1605 * collisions. 1606 */ 1607 mm ATOMIC_LOCK_REG_NAME, r25, r21, 2, (ATOMIC_HASH_SHIFT + 2) - 1 1608 1609 seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_cmpxchg64 1610 } 1611 { 1612 /* Branch away at this point if we're doing a 64-bit cmpxchg. */ 1613 bbs r23, .Lcmpxchg64 1614 andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */ 1615 } 1616 { 1617 /* 1618 * We very carefully align the code that actually runs with 1619 * the lock held (twelve bundles) so that we know it is all in 1620 * the icache when we start. This instruction (the jump) is 1621 * at the start of the first cache line, address zero mod 64; 1622 * we jump to the very end of the second cache line to get that 1623 * line loaded in the icache, then fall through to issue the tns 1624 * in the third cache line, at which point it's all cached. 1625 * Note that is for performance, not correctness. 1626 */ 1627 j .Lcmpxchg32_tns 1628 } 1629 1630/* Symbol for do_page_fault_ics() to use to compare against the PC. */ 1631.global __sys_cmpxchg_grab_lock 1632__sys_cmpxchg_grab_lock: 1633 1634 /* 1635 * Perform the actual cmpxchg or atomic_update. 1636 */ 1637.Ldo_cmpxchg32: 1638 { 1639 lw r21, r0 1640 seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_atomic_update 1641 move r24, r2 1642 } 1643 { 1644 seq r22, r21, r1 /* See if cmpxchg matches. */ 1645 and r25, r21, r1 /* If atomic_update, compute (*mem & mask) */ 1646 } 1647 { 1648 or r22, r22, r23 /* Skip compare branch for atomic_update. */ 1649 add r25, r25, r2 /* Compute (*mem & mask) + addend. */ 1650 } 1651 { 1652 mvnz r24, r23, r25 /* Use atomic_update value if appropriate. */ 1653 bbns r22, .Lcmpxchg32_nostore 1654 } 1655 seq r22, r24, r21 /* Are we storing the value we loaded? */ 1656 bbs r22, .Lcmpxchg32_nostore 1657 sw r0, r24 1658 1659 /* The following instruction is the start of the second cache line. */ 1660 /* Do slow mtspr here so the following "mf" waits less. */ 1661 { 1662 move sp, r27 1663 mtspr SPR_EX_CONTEXT_K_0, r28 1664 } 1665 mf 1666 1667 { 1668 move r0, r21 1669 sw ATOMIC_LOCK_REG_NAME, zero 1670 } 1671 iret 1672 1673 /* Duplicated code here in the case where we don't overlap "mf" */ 1674.Lcmpxchg32_nostore: 1675 { 1676 move r0, r21 1677 sw ATOMIC_LOCK_REG_NAME, zero 1678 } 1679 { 1680 move sp, r27 1681 mtspr SPR_EX_CONTEXT_K_0, r28 1682 } 1683 iret 1684 1685 /* 1686 * The locking code is the same for 32-bit cmpxchg/atomic_update, 1687 * and for 64-bit cmpxchg. We provide it as a macro and put 1688 * it into both versions. We can't share the code literally 1689 * since it depends on having the right branch-back address. 1690 */ 1691 .macro cmpxchg_lock, bitwidth 1692 1693 /* Lock; if we succeed, jump back up to the read-modify-write. */ 1694#ifdef CONFIG_SMP 1695 tns r21, ATOMIC_LOCK_REG_NAME 1696#else 1697 /* 1698 * Non-SMP preserves all the lock infrastructure, to keep the 1699 * code simpler for the interesting (SMP) case. However, we do 1700 * one small optimization here and in atomic_asm.S, which is 1701 * to fake out acquiring the actual lock in the atomic_lock table. 1702 */ 1703 movei r21, 0 1704#endif 1705 1706 /* Issue the slow SPR here while the tns result is in flight. */ 1707 mfspr r28, SPR_EX_CONTEXT_K_0 1708 1709 { 1710 addi r28, r28, 8 /* return to the instruction after the swint1 */ 1711 bzt r21, .Ldo_cmpxchg\bitwidth 1712 } 1713 /* 1714 * The preceding instruction is the last thing that must be 1715 * hot in the icache before we do the "tns" above. 1716 */ 1717 1718#ifdef CONFIG_SMP 1719 /* 1720 * We failed to acquire the tns lock on our first try. Now use 1721 * bounded exponential backoff to retry, like __atomic_spinlock(). 1722 */ 1723 { 1724 moveli r23, 2048 /* maximum backoff time in cycles */ 1725 moveli r25, 32 /* starting backoff time in cycles */ 1726 } 17271: mfspr r26, CYCLE_LOW /* get start point for this backoff */ 17282: mfspr r22, CYCLE_LOW /* test to see if we've backed off enough */ 1729 sub r22, r22, r26 1730 slt r22, r22, r25 1731 bbst r22, 2b 1732 { 1733 shli r25, r25, 1 /* double the backoff; retry the tns */ 1734 tns r21, ATOMIC_LOCK_REG_NAME 1735 } 1736 slt r26, r23, r25 /* is the proposed backoff too big? */ 1737 { 1738 mvnz r25, r26, r23 1739 bzt r21, .Ldo_cmpxchg\bitwidth 1740 } 1741 j 1b 1742#endif /* CONFIG_SMP */ 1743 .endm 1744 1745.Lcmpxchg32_tns: 1746 /* 1747 * This is the last instruction on the second cache line. 1748 * The nop here loads the second line, then we fall through 1749 * to the tns to load the third line before we take the lock. 1750 */ 1751 nop 1752 cmpxchg_lock 32 1753 1754 /* 1755 * This code is invoked from sys_cmpxchg after most of the 1756 * preconditions have been checked. We still need to check 1757 * that r0 is 8-byte aligned, since if it's not we won't 1758 * actually be atomic. However, ATOMIC_LOCK_REG has the atomic 1759 * lock pointer and r27/r28 have the saved SP/PC. 1760 * r23 is holding "r0 & 7" so we can test for alignment. 1761 * The compare value is in r2/r3; the new value is in r4/r5. 1762 * On return, we must put the old value in r0/r1. 1763 */ 1764 .align 64 1765.Lcmpxchg64: 1766 { 1767 bzt r23, .Lcmpxchg64_tns 1768 } 1769 j .Lcmpxchg_badaddr 1770 1771.Ldo_cmpxchg64: 1772 { 1773 lw r21, r0 1774 addi r25, r0, 4 1775 } 1776 { 1777 lw r1, r25 1778 } 1779 seq r26, r21, r2 1780 { 1781 bz r26, .Lcmpxchg64_mismatch 1782 seq r26, r1, r3 1783 } 1784 { 1785 bz r26, .Lcmpxchg64_mismatch 1786 } 1787 sw r0, r4 1788 sw r25, r5 1789 1790 /* 1791 * The 32-bit path provides optimized "match" and "mismatch" 1792 * iret paths, but we don't have enough bundles in this cache line 1793 * to do that, so we just make even the "mismatch" path do an "mf". 1794 */ 1795.Lcmpxchg64_mismatch: 1796 { 1797 move sp, r27 1798 mtspr SPR_EX_CONTEXT_K_0, r28 1799 } 1800 mf 1801 { 1802 move r0, r21 1803 sw ATOMIC_LOCK_REG_NAME, zero 1804 } 1805 iret 1806 1807.Lcmpxchg64_tns: 1808 cmpxchg_lock 64 1809 1810 1811 /* 1812 * Reset sp and revector to sys_cmpxchg_badaddr(), which will 1813 * just raise the appropriate signal and exit. Doing it this 1814 * way means we don't have to duplicate the code in intvec.S's 1815 * int_hand macro that locates the top of the stack. 1816 */ 1817.Lcmpxchg_badaddr: 1818 { 1819 moveli TREG_SYSCALL_NR_NAME, __NR_cmpxchg_badaddr 1820 move sp, r27 1821 } 1822 j intvec_SWINT_1 1823 ENDPROC(sys_cmpxchg) 1824 ENTRY(__sys_cmpxchg_end) 1825 1826 1827/* The single-step support may need to read all the registers. */ 1828int_unalign: 1829 push_extra_callee_saves r0 1830 j do_trap 1831 1832/* Include .intrpt array of interrupt vectors */ 1833 .section ".intrpt", "ax" 1834 1835#ifndef CONFIG_USE_PMC 1836#define handle_perf_interrupt bad_intr 1837#endif 1838 1839#ifndef CONFIG_HARDWALL 1840#define do_hardwall_trap bad_intr 1841#endif 1842 1843 int_hand INT_ITLB_MISS, ITLB_MISS, \ 1844 do_page_fault, handle_interrupt_no_single_step 1845 int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr 1846 int_hand INT_ILL, ILL, do_trap, handle_ill 1847 int_hand INT_GPV, GPV, do_trap 1848 int_hand INT_SN_ACCESS, SN_ACCESS, do_trap 1849 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap 1850 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap 1851 int_hand INT_IDN_REFILL, IDN_REFILL, bad_intr 1852 int_hand INT_UDN_REFILL, UDN_REFILL, bad_intr 1853 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr 1854 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr 1855 int_hand INT_SWINT_3, SWINT_3, do_trap 1856 int_hand INT_SWINT_2, SWINT_2, do_trap 1857 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall 1858 int_hand INT_SWINT_0, SWINT_0, do_trap 1859 int_hand INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign 1860 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault 1861 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault 1862 int_hand INT_DMATLB_MISS, DMATLB_MISS, do_page_fault 1863 int_hand INT_DMATLB_ACCESS, DMATLB_ACCESS, do_page_fault 1864 int_hand INT_SNITLB_MISS, SNITLB_MISS, do_page_fault 1865 int_hand INT_SN_NOTIFY, SN_NOTIFY, bad_intr 1866 int_hand INT_SN_FIREWALL, SN_FIREWALL, do_hardwall_trap 1867 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr 1868 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap 1869 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt 1870 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr 1871 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr 1872 int_hand INT_DMA_NOTIFY, DMA_NOTIFY, bad_intr 1873 int_hand INT_IDN_CA, IDN_CA, bad_intr 1874 int_hand INT_UDN_CA, UDN_CA, bad_intr 1875 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr 1876 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr 1877 int_hand INT_PERF_COUNT, PERF_COUNT, \ 1878 handle_perf_interrupt, handle_nmi 1879 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr 1880#if CONFIG_KERNEL_PL == 2 1881 dc_dispatch INT_INTCTRL_2, INTCTRL_2 1882 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr 1883#else 1884 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr 1885 dc_dispatch INT_INTCTRL_1, INTCTRL_1 1886#endif 1887 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr 1888 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \ 1889 hv_message_intr 1890 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, \ 1891 tile_dev_intr 1892 int_hand INT_I_ASID, I_ASID, bad_intr 1893 int_hand INT_D_ASID, D_ASID, bad_intr 1894 int_hand INT_DMATLB_MISS_DWNCL, DMATLB_MISS_DWNCL, \ 1895 do_page_fault 1896 int_hand INT_SNITLB_MISS_DWNCL, SNITLB_MISS_DWNCL, \ 1897 do_page_fault 1898 int_hand INT_DMATLB_ACCESS_DWNCL, DMATLB_ACCESS_DWNCL, \ 1899 do_page_fault 1900 int_hand INT_SN_CPL, SN_CPL, bad_intr 1901 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap 1902 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \ 1903 handle_perf_interrupt, handle_nmi 1904 1905 /* Synthetic interrupt delivered only by the simulator */ 1906 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint 1907