• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Simple multiplexer clock implementation
11  */
12 
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/err.h>
18 
19 /*
20  * DOC: basic adjustable multiplexer clock that cannot gate
21  *
22  * Traits of this clock:
23  * prepare - clk_prepare only ensures that parents are prepared
24  * enable - clk_enable only ensures that parents are enabled
25  * rate - rate is only affected by parent switching.  No clk_set_rate support
26  * parent - parent is adjustable through clk_set_parent
27  */
28 
clk_mux_get_parent(struct clk_hw * hw)29 static u8 clk_mux_get_parent(struct clk_hw *hw)
30 {
31 	struct clk_mux *mux = to_clk_mux(hw);
32 	int num_parents = clk_hw_get_num_parents(hw);
33 	u32 val;
34 
35 	/*
36 	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
37 	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
38 	 * to 0x7 (index starts at one)
39 	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
40 	 * val = 0x4 really means "bit 2, index starts at bit 0"
41 	 */
42 	val = clk_readl(mux->reg) >> mux->shift;
43 	val &= mux->mask;
44 
45 	if (mux->table) {
46 		int i;
47 
48 		for (i = 0; i < num_parents; i++)
49 			if (mux->table[i] == val)
50 				return i;
51 		return -EINVAL;
52 	}
53 
54 	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
55 		val = ffs(val) - 1;
56 
57 	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
58 		val--;
59 
60 	if (val >= num_parents)
61 		return -EINVAL;
62 
63 	return val;
64 }
65 
clk_mux_set_parent(struct clk_hw * hw,u8 index)66 static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
67 {
68 	struct clk_mux *mux = to_clk_mux(hw);
69 	u32 val;
70 	unsigned long flags = 0;
71 
72 	if (mux->table) {
73 		index = mux->table[index];
74 	} else {
75 		if (mux->flags & CLK_MUX_INDEX_BIT)
76 			index = 1 << index;
77 
78 		if (mux->flags & CLK_MUX_INDEX_ONE)
79 			index++;
80 	}
81 
82 	if (mux->lock)
83 		spin_lock_irqsave(mux->lock, flags);
84 	else
85 		__acquire(mux->lock);
86 
87 	if (mux->flags & CLK_MUX_HIWORD_MASK) {
88 		val = mux->mask << (mux->shift + 16);
89 	} else {
90 		val = clk_readl(mux->reg);
91 		val &= ~(mux->mask << mux->shift);
92 	}
93 	val |= index << mux->shift;
94 	clk_writel(val, mux->reg);
95 
96 	if (mux->lock)
97 		spin_unlock_irqrestore(mux->lock, flags);
98 	else
99 		__release(mux->lock);
100 
101 	return 0;
102 }
103 
clk_mux_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)104 static int clk_mux_determine_rate(struct clk_hw *hw,
105 				  struct clk_rate_request *req)
106 {
107 	struct clk_mux *mux = to_clk_mux(hw);
108 
109 	return clk_mux_determine_rate_flags(hw, req, mux->flags);
110 }
111 
112 const struct clk_ops clk_mux_ops = {
113 	.get_parent = clk_mux_get_parent,
114 	.set_parent = clk_mux_set_parent,
115 	.determine_rate = clk_mux_determine_rate,
116 };
117 EXPORT_SYMBOL_GPL(clk_mux_ops);
118 
119 const struct clk_ops clk_mux_ro_ops = {
120 	.get_parent = clk_mux_get_parent,
121 };
122 EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
123 
clk_hw_register_mux_table(struct device * dev,const char * name,const char * const * parent_names,u8 num_parents,unsigned long flags,void __iomem * reg,u8 shift,u32 mask,u8 clk_mux_flags,u32 * table,spinlock_t * lock)124 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
125 		const char * const *parent_names, u8 num_parents,
126 		unsigned long flags,
127 		void __iomem *reg, u8 shift, u32 mask,
128 		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
129 {
130 	struct clk_mux *mux;
131 	struct clk_hw *hw;
132 	struct clk_init_data init;
133 	u8 width = 0;
134 	int ret;
135 
136 	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
137 		width = fls(mask) - ffs(mask) + 1;
138 		if (width + shift > 16) {
139 			pr_err("mux value exceeds LOWORD field\n");
140 			return ERR_PTR(-EINVAL);
141 		}
142 	}
143 
144 	/* allocate the mux */
145 	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
146 	if (!mux) {
147 		pr_err("%s: could not allocate mux clk\n", __func__);
148 		return ERR_PTR(-ENOMEM);
149 	}
150 
151 	init.name = name;
152 	if (clk_mux_flags & CLK_MUX_READ_ONLY)
153 		init.ops = &clk_mux_ro_ops;
154 	else
155 		init.ops = &clk_mux_ops;
156 	init.flags = flags | CLK_IS_BASIC;
157 	init.parent_names = parent_names;
158 	init.num_parents = num_parents;
159 
160 	/* struct clk_mux assignments */
161 	mux->reg = reg;
162 	mux->shift = shift;
163 	mux->mask = mask;
164 	mux->flags = clk_mux_flags;
165 	mux->lock = lock;
166 	mux->table = table;
167 	mux->hw.init = &init;
168 
169 	hw = &mux->hw;
170 	ret = clk_hw_register(dev, hw);
171 	if (ret) {
172 		kfree(mux);
173 		hw = ERR_PTR(ret);
174 	}
175 
176 	return hw;
177 }
178 EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
179 
clk_register_mux_table(struct device * dev,const char * name,const char * const * parent_names,u8 num_parents,unsigned long flags,void __iomem * reg,u8 shift,u32 mask,u8 clk_mux_flags,u32 * table,spinlock_t * lock)180 struct clk *clk_register_mux_table(struct device *dev, const char *name,
181 		const char * const *parent_names, u8 num_parents,
182 		unsigned long flags,
183 		void __iomem *reg, u8 shift, u32 mask,
184 		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
185 {
186 	struct clk_hw *hw;
187 
188 	hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
189 				       flags, reg, shift, mask, clk_mux_flags,
190 				       table, lock);
191 	if (IS_ERR(hw))
192 		return ERR_CAST(hw);
193 	return hw->clk;
194 }
195 EXPORT_SYMBOL_GPL(clk_register_mux_table);
196 
clk_register_mux(struct device * dev,const char * name,const char * const * parent_names,u8 num_parents,unsigned long flags,void __iomem * reg,u8 shift,u8 width,u8 clk_mux_flags,spinlock_t * lock)197 struct clk *clk_register_mux(struct device *dev, const char *name,
198 		const char * const *parent_names, u8 num_parents,
199 		unsigned long flags,
200 		void __iomem *reg, u8 shift, u8 width,
201 		u8 clk_mux_flags, spinlock_t *lock)
202 {
203 	u32 mask = BIT(width) - 1;
204 
205 	return clk_register_mux_table(dev, name, parent_names, num_parents,
206 				      flags, reg, shift, mask, clk_mux_flags,
207 				      NULL, lock);
208 }
209 EXPORT_SYMBOL_GPL(clk_register_mux);
210 
clk_hw_register_mux(struct device * dev,const char * name,const char * const * parent_names,u8 num_parents,unsigned long flags,void __iomem * reg,u8 shift,u8 width,u8 clk_mux_flags,spinlock_t * lock)211 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
212 		const char * const *parent_names, u8 num_parents,
213 		unsigned long flags,
214 		void __iomem *reg, u8 shift, u8 width,
215 		u8 clk_mux_flags, spinlock_t *lock)
216 {
217 	u32 mask = BIT(width) - 1;
218 
219 	return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
220 				      flags, reg, shift, mask, clk_mux_flags,
221 				      NULL, lock);
222 }
223 EXPORT_SYMBOL_GPL(clk_hw_register_mux);
224 
clk_unregister_mux(struct clk * clk)225 void clk_unregister_mux(struct clk *clk)
226 {
227 	struct clk_mux *mux;
228 	struct clk_hw *hw;
229 
230 	hw = __clk_get_hw(clk);
231 	if (!hw)
232 		return;
233 
234 	mux = to_clk_mux(hw);
235 
236 	clk_unregister(clk);
237 	kfree(mux);
238 }
239 EXPORT_SYMBOL_GPL(clk_unregister_mux);
240 
clk_hw_unregister_mux(struct clk_hw * hw)241 void clk_hw_unregister_mux(struct clk_hw *hw)
242 {
243 	struct clk_mux *mux;
244 
245 	mux = to_clk_mux(hw);
246 
247 	clk_hw_unregister(hw);
248 	kfree(mux);
249 }
250 EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
251