1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Faraday Technology FTPC100 PCI Controller
4 *
5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
6 *
7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
8 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
9 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
10 * Based on SL2312 PCI controller code
11 * Storlink (C) 2003
12 */
13
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_pci.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/clk.h>
30
31 /*
32 * Special configuration registers directly in the first few words
33 * in I/O space.
34 */
35 #define PCI_IOSIZE 0x00
36 #define PCI_PROT 0x04 /* AHB protection */
37 #define PCI_CTRL 0x08 /* PCI control signal */
38 #define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
39 #define PCI_CONFIG 0x28 /* PCI configuration command register */
40 #define PCI_DATA 0x2C
41
42 #define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */
43 #define FARADAY_PCI_PMC 0x40 /* Power management control */
44 #define FARADAY_PCI_PMCSR 0x44 /* Power management status */
45 #define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */
46 #define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */
47 #define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */
48 #define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */
49 #define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */
50
51 #define PCI_STATUS_66MHZ_CAPABLE BIT(21)
52
53 /* Bits 31..28 gives INTD..INTA status */
54 #define PCI_CTRL2_INTSTS_SHIFT 28
55 #define PCI_CTRL2_INTMASK_CMDERR BIT(27)
56 #define PCI_CTRL2_INTMASK_PARERR BIT(26)
57 /* Bits 25..22 masks INTD..INTA */
58 #define PCI_CTRL2_INTMASK_SHIFT 22
59 #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21)
60 #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20)
61 #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19)
62 #define PCI_CTRL2_INTMASK_RETRY4 BIT(18)
63 #define PCI_CTRL2_INTMASK_SERR_RX BIT(17)
64 #define PCI_CTRL2_INTMASK_PERR_RX BIT(16)
65 /* Bit 15 reserved */
66 #define PCI_CTRL2_MSTPRI_REQ6 BIT(14)
67 #define PCI_CTRL2_MSTPRI_REQ5 BIT(13)
68 #define PCI_CTRL2_MSTPRI_REQ4 BIT(12)
69 #define PCI_CTRL2_MSTPRI_REQ3 BIT(11)
70 #define PCI_CTRL2_MSTPRI_REQ2 BIT(10)
71 #define PCI_CTRL2_MSTPRI_REQ1 BIT(9)
72 #define PCI_CTRL2_MSTPRI_REQ0 BIT(8)
73 /* Bits 7..4 reserved */
74 /* Bits 3..0 TRDYW */
75
76 /*
77 * Memory configs:
78 * Bit 31..20 defines the PCI side memory base
79 * Bit 19..16 (4 bits) defines the size per below
80 */
81 #define FARADAY_PCI_MEMBASE_MASK 0xfff00000
82 #define FARADAY_PCI_MEMSIZE_1MB 0x0
83 #define FARADAY_PCI_MEMSIZE_2MB 0x1
84 #define FARADAY_PCI_MEMSIZE_4MB 0x2
85 #define FARADAY_PCI_MEMSIZE_8MB 0x3
86 #define FARADAY_PCI_MEMSIZE_16MB 0x4
87 #define FARADAY_PCI_MEMSIZE_32MB 0x5
88 #define FARADAY_PCI_MEMSIZE_64MB 0x6
89 #define FARADAY_PCI_MEMSIZE_128MB 0x7
90 #define FARADAY_PCI_MEMSIZE_256MB 0x8
91 #define FARADAY_PCI_MEMSIZE_512MB 0x9
92 #define FARADAY_PCI_MEMSIZE_1GB 0xa
93 #define FARADAY_PCI_MEMSIZE_2GB 0xb
94 #define FARADAY_PCI_MEMSIZE_SHIFT 16
95
96 /*
97 * The DMA base is set to 0x0 for all memory segments, it reflects the
98 * fact that the memory of the host system starts at 0x0.
99 */
100 #define FARADAY_PCI_DMA_MEM1_BASE 0x00000000
101 #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
102 #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
103
104 /* Defines for PCI configuration command register */
105 #define PCI_CONF_ENABLE BIT(31)
106 #define PCI_CONF_WHERE(r) ((r) & 0xFC)
107 #define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
108 #define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
109 #define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
110
111 /**
112 * struct faraday_pci_variant - encodes IP block differences
113 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
114 * embedded in the host bridge.
115 */
116 struct faraday_pci_variant {
117 bool cascaded_irq;
118 };
119
120 struct faraday_pci {
121 struct device *dev;
122 void __iomem *base;
123 struct irq_domain *irqdomain;
124 struct pci_bus *bus;
125 struct clk *bus_clk;
126 };
127
faraday_res_to_memcfg(resource_size_t mem_base,resource_size_t mem_size,u32 * val)128 static int faraday_res_to_memcfg(resource_size_t mem_base,
129 resource_size_t mem_size, u32 *val)
130 {
131 u32 outval;
132
133 switch (mem_size) {
134 case SZ_1M:
135 outval = FARADAY_PCI_MEMSIZE_1MB;
136 break;
137 case SZ_2M:
138 outval = FARADAY_PCI_MEMSIZE_2MB;
139 break;
140 case SZ_4M:
141 outval = FARADAY_PCI_MEMSIZE_4MB;
142 break;
143 case SZ_8M:
144 outval = FARADAY_PCI_MEMSIZE_8MB;
145 break;
146 case SZ_16M:
147 outval = FARADAY_PCI_MEMSIZE_16MB;
148 break;
149 case SZ_32M:
150 outval = FARADAY_PCI_MEMSIZE_32MB;
151 break;
152 case SZ_64M:
153 outval = FARADAY_PCI_MEMSIZE_64MB;
154 break;
155 case SZ_128M:
156 outval = FARADAY_PCI_MEMSIZE_128MB;
157 break;
158 case SZ_256M:
159 outval = FARADAY_PCI_MEMSIZE_256MB;
160 break;
161 case SZ_512M:
162 outval = FARADAY_PCI_MEMSIZE_512MB;
163 break;
164 case SZ_1G:
165 outval = FARADAY_PCI_MEMSIZE_1GB;
166 break;
167 case SZ_2G:
168 outval = FARADAY_PCI_MEMSIZE_2GB;
169 break;
170 default:
171 return -EINVAL;
172 }
173 outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
174
175 /* This is probably not good */
176 if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
177 pr_warn("truncated PCI memory base\n");
178 /* Translate to bridge side address space */
179 outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
180 pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
181 &mem_base, &mem_size, outval);
182
183 *val = outval;
184 return 0;
185 }
186
faraday_raw_pci_read_config(struct faraday_pci * p,int bus_number,unsigned int fn,int config,int size,u32 * value)187 static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
188 unsigned int fn, int config, int size,
189 u32 *value)
190 {
191 writel(PCI_CONF_BUS(bus_number) |
192 PCI_CONF_DEVICE(PCI_SLOT(fn)) |
193 PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
194 PCI_CONF_WHERE(config) |
195 PCI_CONF_ENABLE,
196 p->base + PCI_CONFIG);
197
198 *value = readl(p->base + PCI_DATA);
199
200 if (size == 1)
201 *value = (*value >> (8 * (config & 3))) & 0xFF;
202 else if (size == 2)
203 *value = (*value >> (8 * (config & 3))) & 0xFFFF;
204
205 return PCIBIOS_SUCCESSFUL;
206 }
207
faraday_pci_read_config(struct pci_bus * bus,unsigned int fn,int config,int size,u32 * value)208 static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
209 int config, int size, u32 *value)
210 {
211 struct faraday_pci *p = bus->sysdata;
212
213 dev_dbg(&bus->dev,
214 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
215 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
216
217 return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
218 }
219
faraday_raw_pci_write_config(struct faraday_pci * p,int bus_number,unsigned int fn,int config,int size,u32 value)220 static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
221 unsigned int fn, int config, int size,
222 u32 value)
223 {
224 int ret = PCIBIOS_SUCCESSFUL;
225
226 writel(PCI_CONF_BUS(bus_number) |
227 PCI_CONF_DEVICE(PCI_SLOT(fn)) |
228 PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
229 PCI_CONF_WHERE(config) |
230 PCI_CONF_ENABLE,
231 p->base + PCI_CONFIG);
232
233 switch (size) {
234 case 4:
235 writel(value, p->base + PCI_DATA);
236 break;
237 case 2:
238 writew(value, p->base + PCI_DATA + (config & 3));
239 break;
240 case 1:
241 writeb(value, p->base + PCI_DATA + (config & 3));
242 break;
243 default:
244 ret = PCIBIOS_BAD_REGISTER_NUMBER;
245 }
246
247 return ret;
248 }
249
faraday_pci_write_config(struct pci_bus * bus,unsigned int fn,int config,int size,u32 value)250 static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
251 int config, int size, u32 value)
252 {
253 struct faraday_pci *p = bus->sysdata;
254
255 dev_dbg(&bus->dev,
256 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
257 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
258
259 return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
260 value);
261 }
262
263 static struct pci_ops faraday_pci_ops = {
264 .read = faraday_pci_read_config,
265 .write = faraday_pci_write_config,
266 };
267
faraday_pci_ack_irq(struct irq_data * d)268 static void faraday_pci_ack_irq(struct irq_data *d)
269 {
270 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
271 unsigned int reg;
272
273 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
274 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
275 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
276 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
277 }
278
faraday_pci_mask_irq(struct irq_data * d)279 static void faraday_pci_mask_irq(struct irq_data *d)
280 {
281 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
282 unsigned int reg;
283
284 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
285 reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
286 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
287 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
288 }
289
faraday_pci_unmask_irq(struct irq_data * d)290 static void faraday_pci_unmask_irq(struct irq_data *d)
291 {
292 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
293 unsigned int reg;
294
295 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
296 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
297 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
298 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
299 }
300
faraday_pci_irq_handler(struct irq_desc * desc)301 static void faraday_pci_irq_handler(struct irq_desc *desc)
302 {
303 struct faraday_pci *p = irq_desc_get_handler_data(desc);
304 struct irq_chip *irqchip = irq_desc_get_chip(desc);
305 unsigned int irq_stat, reg, i;
306
307 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
308 irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
309
310 chained_irq_enter(irqchip, desc);
311
312 for (i = 0; i < 4; i++) {
313 if ((irq_stat & BIT(i)) == 0)
314 continue;
315 generic_handle_irq(irq_find_mapping(p->irqdomain, i));
316 }
317
318 chained_irq_exit(irqchip, desc);
319 }
320
321 static struct irq_chip faraday_pci_irq_chip = {
322 .name = "PCI",
323 .irq_ack = faraday_pci_ack_irq,
324 .irq_mask = faraday_pci_mask_irq,
325 .irq_unmask = faraday_pci_unmask_irq,
326 };
327
faraday_pci_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)328 static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
329 irq_hw_number_t hwirq)
330 {
331 irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
332 irq_set_chip_data(irq, domain->host_data);
333
334 return 0;
335 }
336
337 static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
338 .map = faraday_pci_irq_map,
339 };
340
faraday_pci_setup_cascaded_irq(struct faraday_pci * p)341 static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
342 {
343 struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
344 int irq;
345 int i;
346
347 if (!intc) {
348 dev_err(p->dev, "missing child interrupt-controller node\n");
349 return -EINVAL;
350 }
351
352 /* All PCI IRQs cascade off this one */
353 irq = of_irq_get(intc, 0);
354 if (irq <= 0) {
355 dev_err(p->dev, "failed to get parent IRQ\n");
356 of_node_put(intc);
357 return irq ?: -EINVAL;
358 }
359
360 p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
361 &faraday_pci_irqdomain_ops, p);
362 of_node_put(intc);
363 if (!p->irqdomain) {
364 dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
365 return -EINVAL;
366 }
367
368 irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
369
370 for (i = 0; i < 4; i++)
371 irq_create_mapping(p->irqdomain, i);
372
373 return 0;
374 }
375
pci_dma_range_parser_init(struct of_pci_range_parser * parser,struct device_node * node)376 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
377 struct device_node *node)
378 {
379 const int na = 3, ns = 2;
380 int rlen;
381
382 parser->node = node;
383 parser->pna = of_n_addr_cells(node);
384 parser->np = parser->pna + na + ns;
385
386 parser->range = of_get_property(node, "dma-ranges", &rlen);
387 if (!parser->range)
388 return -ENOENT;
389 parser->end = parser->range + rlen / sizeof(__be32);
390
391 return 0;
392 }
393
faraday_pci_parse_map_dma_ranges(struct faraday_pci * p,struct device_node * np)394 static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
395 struct device_node *np)
396 {
397 struct of_pci_range range;
398 struct of_pci_range_parser parser;
399 struct device *dev = p->dev;
400 u32 confreg[3] = {
401 FARADAY_PCI_MEM1_BASE_SIZE,
402 FARADAY_PCI_MEM2_BASE_SIZE,
403 FARADAY_PCI_MEM3_BASE_SIZE,
404 };
405 int i = 0;
406 u32 val;
407
408 if (pci_dma_range_parser_init(&parser, np)) {
409 dev_err(dev, "missing dma-ranges property\n");
410 return -EINVAL;
411 }
412
413 /*
414 * Get the dma-ranges from the device tree
415 */
416 for_each_of_pci_range(&parser, &range) {
417 u64 end = range.pci_addr + range.size - 1;
418 int ret;
419
420 ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
421 if (ret) {
422 dev_err(dev,
423 "DMA range %d: illegal MEM resource size\n", i);
424 return -EINVAL;
425 }
426
427 dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
428 i + 1, range.pci_addr, end, val);
429 if (i <= 2) {
430 faraday_raw_pci_write_config(p, 0, 0, confreg[i],
431 4, val);
432 } else {
433 dev_err(dev, "ignore extraneous dma-range %d\n", i);
434 break;
435 }
436
437 i++;
438 }
439
440 return 0;
441 }
442
faraday_pci_probe(struct platform_device * pdev)443 static int faraday_pci_probe(struct platform_device *pdev)
444 {
445 struct device *dev = &pdev->dev;
446 const struct faraday_pci_variant *variant =
447 of_device_get_match_data(dev);
448 struct resource *regs;
449 resource_size_t io_base;
450 struct resource_entry *win;
451 struct faraday_pci *p;
452 struct resource *mem;
453 struct resource *io;
454 struct pci_host_bridge *host;
455 struct clk *clk;
456 unsigned char max_bus_speed = PCI_SPEED_33MHz;
457 unsigned char cur_bus_speed = PCI_SPEED_33MHz;
458 int ret;
459 u32 val;
460 LIST_HEAD(res);
461
462 host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
463 if (!host)
464 return -ENOMEM;
465
466 host->dev.parent = dev;
467 host->ops = &faraday_pci_ops;
468 host->busnr = 0;
469 host->msi = NULL;
470 host->map_irq = of_irq_parse_and_map_pci;
471 host->swizzle_irq = pci_common_swizzle;
472 p = pci_host_bridge_priv(host);
473 host->sysdata = p;
474 p->dev = dev;
475
476 /* Retrieve and enable optional clocks */
477 clk = devm_clk_get(dev, "PCLK");
478 if (IS_ERR(clk))
479 return PTR_ERR(clk);
480 ret = clk_prepare_enable(clk);
481 if (ret) {
482 dev_err(dev, "could not prepare PCLK\n");
483 return ret;
484 }
485 p->bus_clk = devm_clk_get(dev, "PCICLK");
486 if (IS_ERR(p->bus_clk))
487 return PTR_ERR(clk);
488 ret = clk_prepare_enable(p->bus_clk);
489 if (ret) {
490 dev_err(dev, "could not prepare PCICLK\n");
491 return ret;
492 }
493
494 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
495 p->base = devm_ioremap_resource(dev, regs);
496 if (IS_ERR(p->base))
497 return PTR_ERR(p->base);
498
499 ret = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
500 &res, &io_base);
501 if (ret)
502 return ret;
503
504 ret = devm_request_pci_bus_resources(dev, &res);
505 if (ret)
506 return ret;
507
508 /* Get the I/O and memory ranges from DT */
509 resource_list_for_each_entry(win, &res) {
510 switch (resource_type(win->res)) {
511 case IORESOURCE_IO:
512 io = win->res;
513 io->name = "Gemini PCI I/O";
514 if (!faraday_res_to_memcfg(io->start - win->offset,
515 resource_size(io), &val)) {
516 /* setup I/O space size */
517 writel(val, p->base + PCI_IOSIZE);
518 } else {
519 dev_err(dev, "illegal IO mem size\n");
520 return -EINVAL;
521 }
522 ret = pci_remap_iospace(io, io_base);
523 if (ret) {
524 dev_warn(dev, "error %d: failed to map resource %pR\n",
525 ret, io);
526 continue;
527 }
528 break;
529 case IORESOURCE_MEM:
530 mem = win->res;
531 mem->name = "Gemini PCI MEM";
532 break;
533 case IORESOURCE_BUS:
534 break;
535 default:
536 break;
537 }
538 }
539
540 /* Setup hostbridge */
541 val = readl(p->base + PCI_CTRL);
542 val |= PCI_COMMAND_IO;
543 val |= PCI_COMMAND_MEMORY;
544 val |= PCI_COMMAND_MASTER;
545 writel(val, p->base + PCI_CTRL);
546 /* Mask and clear all interrupts */
547 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
548 if (variant->cascaded_irq) {
549 ret = faraday_pci_setup_cascaded_irq(p);
550 if (ret) {
551 dev_err(dev, "failed to setup cascaded IRQ\n");
552 return ret;
553 }
554 }
555
556 /* Check bus clock if we can gear up to 66 MHz */
557 if (!IS_ERR(p->bus_clk)) {
558 unsigned long rate;
559 u32 val;
560
561 faraday_raw_pci_read_config(p, 0, 0,
562 FARADAY_PCI_STATUS_CMD, 4, &val);
563 rate = clk_get_rate(p->bus_clk);
564
565 if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
566 dev_info(dev, "33MHz bus is 66MHz capable\n");
567 max_bus_speed = PCI_SPEED_66MHz;
568 ret = clk_set_rate(p->bus_clk, 66000000);
569 if (ret)
570 dev_err(dev, "failed to set bus clock\n");
571 } else {
572 dev_info(dev, "33MHz only bus\n");
573 max_bus_speed = PCI_SPEED_33MHz;
574 }
575
576 /* Bumping the clock may fail so read back the rate */
577 rate = clk_get_rate(p->bus_clk);
578 if (rate == 33000000)
579 cur_bus_speed = PCI_SPEED_33MHz;
580 if (rate == 66000000)
581 cur_bus_speed = PCI_SPEED_66MHz;
582 }
583
584 ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
585 if (ret)
586 return ret;
587
588 list_splice_init(&res, &host->windows);
589 ret = pci_scan_root_bus_bridge(host);
590 if (ret) {
591 dev_err(dev, "failed to scan host: %d\n", ret);
592 return ret;
593 }
594 p->bus = host->bus;
595 p->bus->max_bus_speed = max_bus_speed;
596 p->bus->cur_bus_speed = cur_bus_speed;
597
598 pci_bus_assign_resources(p->bus);
599 pci_bus_add_devices(p->bus);
600 pci_free_resource_list(&res);
601
602 return 0;
603 }
604
605 /*
606 * We encode bridge variants here, we have at least two so it doesn't
607 * hurt to have infrastructure to encompass future variants as well.
608 */
609 const struct faraday_pci_variant faraday_regular = {
610 .cascaded_irq = true,
611 };
612
613 const struct faraday_pci_variant faraday_dual = {
614 .cascaded_irq = false,
615 };
616
617 static const struct of_device_id faraday_pci_of_match[] = {
618 {
619 .compatible = "faraday,ftpci100",
620 .data = &faraday_regular,
621 },
622 {
623 .compatible = "faraday,ftpci100-dual",
624 .data = &faraday_dual,
625 },
626 {},
627 };
628
629 static struct platform_driver faraday_pci_driver = {
630 .driver = {
631 .name = "ftpci100",
632 .of_match_table = of_match_ptr(faraday_pci_of_match),
633 .suppress_bind_attrs = true,
634 },
635 .probe = faraday_pci_probe,
636 };
637 builtin_platform_driver(faraday_pci_driver);
638