1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __CXGB4_ULD_H
36 #define __CXGB4_ULD_H
37
38 #include <linux/cache.h>
39 #include <linux/spinlock.h>
40 #include <linux/skbuff.h>
41 #include <linux/inetdevice.h>
42 #include <linux/atomic.h>
43 #include "cxgb4.h"
44
45 #define MAX_ULD_QSETS 16
46
47 /* CPL message priority levels */
48 enum {
49 CPL_PRIORITY_DATA = 0, /* data messages */
50 CPL_PRIORITY_SETUP = 1, /* connection setup messages */
51 CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */
52 CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */
53 CPL_PRIORITY_ACK = 1, /* RX ACK messages */
54 CPL_PRIORITY_CONTROL = 1 /* control messages */
55 };
56
57 #define INIT_TP_WR(w, tid) do { \
58 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \
59 FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \
60 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \
61 FW_WR_FLOWID_V(tid)); \
62 (w)->wr.wr_lo = cpu_to_be64(0); \
63 } while (0)
64
65 #define INIT_TP_WR_CPL(w, cpl, tid) do { \
66 INIT_TP_WR(w, tid); \
67 OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
68 } while (0)
69
70 #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
71 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \
72 FW_WR_ATOMIC_V(atomic)); \
73 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \
74 FW_WR_FLOWID_V(tid)); \
75 (w)->wr.wr_lo = cpu_to_be64(0); \
76 } while (0)
77
78 /* Special asynchronous notification message */
79 #define CXGB4_MSG_AN ((void *)1)
80 #define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\
81 CXGB4_TX_CRYPTO)
82
83 struct serv_entry {
84 void *data;
85 };
86
87 union aopen_entry {
88 void *data;
89 union aopen_entry *next;
90 };
91
92 /*
93 * Holds the size, base address, free list start, etc of the TID, server TID,
94 * and active-open TID tables. The tables themselves are allocated dynamically.
95 */
96 struct tid_info {
97 void **tid_tab;
98 unsigned int ntids;
99
100 struct serv_entry *stid_tab;
101 unsigned long *stid_bmap;
102 unsigned int nstids;
103 unsigned int stid_base;
104 unsigned int hash_base;
105
106 union aopen_entry *atid_tab;
107 unsigned int natids;
108 unsigned int atid_base;
109
110 struct filter_entry *ftid_tab;
111 unsigned long *ftid_bmap;
112 unsigned int nftids;
113 unsigned int ftid_base;
114 unsigned int aftid_base;
115 unsigned int aftid_end;
116 /* Server filter region */
117 unsigned int sftid_base;
118 unsigned int nsftids;
119
120 spinlock_t atid_lock ____cacheline_aligned_in_smp;
121 union aopen_entry *afree;
122 unsigned int atids_in_use;
123
124 spinlock_t stid_lock;
125 unsigned int stids_in_use;
126 unsigned int v6_stids_in_use;
127 unsigned int sftids_in_use;
128
129 /* TIDs in the TCAM */
130 atomic_t tids_in_use;
131 /* TIDs in the HASH */
132 atomic_t hash_tids_in_use;
133 atomic_t conns_in_use;
134 /* lock for setting/clearing filter bitmap */
135 spinlock_t ftid_lock;
136 };
137
lookup_tid(const struct tid_info * t,unsigned int tid)138 static inline void *lookup_tid(const struct tid_info *t, unsigned int tid)
139 {
140 return tid < t->ntids ? t->tid_tab[tid] : NULL;
141 }
142
lookup_atid(const struct tid_info * t,unsigned int atid)143 static inline void *lookup_atid(const struct tid_info *t, unsigned int atid)
144 {
145 return atid < t->natids ? t->atid_tab[atid].data : NULL;
146 }
147
lookup_stid(const struct tid_info * t,unsigned int stid)148 static inline void *lookup_stid(const struct tid_info *t, unsigned int stid)
149 {
150 /* Is it a server filter TID? */
151 if (t->nsftids && (stid >= t->sftid_base)) {
152 stid -= t->sftid_base;
153 stid += t->nstids;
154 } else {
155 stid -= t->stid_base;
156 }
157
158 return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL;
159 }
160
cxgb4_insert_tid(struct tid_info * t,void * data,unsigned int tid,unsigned short family)161 static inline void cxgb4_insert_tid(struct tid_info *t, void *data,
162 unsigned int tid, unsigned short family)
163 {
164 t->tid_tab[tid] = data;
165 if (t->hash_base && (tid >= t->hash_base)) {
166 if (family == AF_INET6)
167 atomic_add(2, &t->hash_tids_in_use);
168 else
169 atomic_inc(&t->hash_tids_in_use);
170 } else {
171 if (family == AF_INET6)
172 atomic_add(2, &t->tids_in_use);
173 else
174 atomic_inc(&t->tids_in_use);
175 }
176 atomic_inc(&t->conns_in_use);
177 }
178
179 int cxgb4_alloc_atid(struct tid_info *t, void *data);
180 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data);
181 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data);
182 void cxgb4_free_atid(struct tid_info *t, unsigned int atid);
183 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family);
184 void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid,
185 unsigned short family);
186 struct in6_addr;
187
188 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
189 __be32 sip, __be16 sport, __be16 vlan,
190 unsigned int queue);
191 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
192 const struct in6_addr *sip, __be16 sport,
193 unsigned int queue);
194 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
195 unsigned int queue, bool ipv6);
196 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
197 __be32 sip, __be16 sport, __be16 vlan,
198 unsigned int queue,
199 unsigned char port, unsigned char mask);
200 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
201 unsigned int queue, bool ipv6);
202
203 /* Filter operation context to allow callers of cxgb4_set_filter() and
204 * cxgb4_del_filter() to wait for an asynchronous completion.
205 */
206 struct filter_ctx {
207 struct completion completion; /* completion rendezvous */
208 void *closure; /* caller's opaque information */
209 int result; /* result of operation */
210 u32 tid; /* to store tid */
211 };
212
213 struct ch_filter_specification;
214
215 int __cxgb4_set_filter(struct net_device *dev, int filter_id,
216 struct ch_filter_specification *fs,
217 struct filter_ctx *ctx);
218 int __cxgb4_del_filter(struct net_device *dev, int filter_id,
219 struct filter_ctx *ctx);
220 int cxgb4_set_filter(struct net_device *dev, int filter_id,
221 struct ch_filter_specification *fs);
222 int cxgb4_del_filter(struct net_device *dev, int filter_id);
223
set_wr_txq(struct sk_buff * skb,int prio,int queue)224 static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue)
225 {
226 skb_set_queue_mapping(skb, (queue << 1) | prio);
227 }
228
229 enum cxgb4_uld {
230 CXGB4_ULD_INIT,
231 CXGB4_ULD_RDMA,
232 CXGB4_ULD_ISCSI,
233 CXGB4_ULD_ISCSIT,
234 CXGB4_ULD_CRYPTO,
235 CXGB4_ULD_MAX
236 };
237
238 enum cxgb4_tx_uld {
239 CXGB4_TX_OFLD,
240 CXGB4_TX_CRYPTO,
241 CXGB4_TX_MAX
242 };
243
244 enum cxgb4_txq_type {
245 CXGB4_TXQ_ETH,
246 CXGB4_TXQ_ULD,
247 CXGB4_TXQ_CTRL,
248 CXGB4_TXQ_MAX
249 };
250
251 enum cxgb4_state {
252 CXGB4_STATE_UP,
253 CXGB4_STATE_START_RECOVERY,
254 CXGB4_STATE_DOWN,
255 CXGB4_STATE_DETACH
256 };
257
258 enum cxgb4_control {
259 CXGB4_CONTROL_DB_FULL,
260 CXGB4_CONTROL_DB_EMPTY,
261 CXGB4_CONTROL_DB_DROP,
262 };
263
264 struct pci_dev;
265 struct l2t_data;
266 struct net_device;
267 struct pkt_gl;
268 struct tp_tcp_stats;
269 struct t4_lro_mgr;
270
271 struct cxgb4_range {
272 unsigned int start;
273 unsigned int size;
274 };
275
276 struct cxgb4_virt_res { /* virtualized HW resources */
277 struct cxgb4_range ddp;
278 struct cxgb4_range iscsi;
279 struct cxgb4_range stag;
280 struct cxgb4_range rq;
281 struct cxgb4_range pbl;
282 struct cxgb4_range qp;
283 struct cxgb4_range cq;
284 struct cxgb4_range ocq;
285 unsigned int ncrypto_fc;
286 };
287
288 struct chcr_stats_debug {
289 atomic_t cipher_rqst;
290 atomic_t digest_rqst;
291 atomic_t aead_rqst;
292 atomic_t complete;
293 atomic_t error;
294 atomic_t fallback;
295 };
296
297 #define OCQ_WIN_OFFSET(pdev, vres) \
298 (pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size))
299
300 /*
301 * Block of information the LLD provides to ULDs attaching to a device.
302 */
303 struct cxgb4_lld_info {
304 struct pci_dev *pdev; /* associated PCI device */
305 struct l2t_data *l2t; /* L2 table */
306 struct tid_info *tids; /* TID table */
307 struct net_device **ports; /* device ports */
308 const struct cxgb4_virt_res *vr; /* assorted HW resources */
309 const unsigned short *mtus; /* MTU table */
310 const unsigned short *rxq_ids; /* the ULD's Rx queue ids */
311 const unsigned short *ciq_ids; /* the ULD's concentrator IQ ids */
312 unsigned short nrxq; /* # of Rx queues */
313 unsigned short ntxq; /* # of Tx queues */
314 unsigned short nciq; /* # of concentrator IQ */
315 unsigned char nchan:4; /* # of channels */
316 unsigned char nports:4; /* # of ports */
317 unsigned char wr_cred; /* WR 16-byte credits */
318 unsigned char adapter_type; /* type of adapter */
319 unsigned char fw_api_ver; /* FW API version */
320 unsigned int fw_vers; /* FW version */
321 unsigned int iscsi_iolen; /* iSCSI max I/O length */
322 unsigned int cclk_ps; /* Core clock period in psec */
323 unsigned short udb_density; /* # of user DB/page */
324 unsigned short ucq_density; /* # of user CQs/page */
325 unsigned short filt_mode; /* filter optional components */
326 unsigned short tx_modq[NCHAN]; /* maps each tx channel to a */
327 /* scheduler queue */
328 void __iomem *gts_reg; /* address of GTS register */
329 void __iomem *db_reg; /* address of kernel doorbell */
330 int dbfifo_int_thresh; /* doorbell fifo int threshold */
331 unsigned int sge_ingpadboundary; /* SGE ingress padding boundary */
332 unsigned int sge_egrstatuspagesize; /* SGE egress status page size */
333 unsigned int sge_pktshift; /* Padding between CPL and */
334 /* packet data */
335 unsigned int pf; /* Physical Function we're using */
336 bool enable_fw_ofld_conn; /* Enable connection through fw */
337 /* WR */
338 unsigned int max_ordird_qp; /* Max ORD/IRD depth per RDMA QP */
339 unsigned int max_ird_adapter; /* Max IRD memory per adapter */
340 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
341 unsigned int iscsi_tagmask; /* iscsi ddp tag mask */
342 unsigned int iscsi_pgsz_order; /* iscsi ddp page size orders */
343 unsigned int iscsi_llimit; /* chip's iscsi region llimit */
344 unsigned int ulp_crypto; /* crypto lookaside support */
345 void **iscsi_ppm; /* iscsi page pod manager */
346 int nodeid; /* device numa node id */
347 bool fr_nsmr_tpte_wr_support; /* FW supports FR_NSMR_TPTE_WR */
348 };
349
350 struct cxgb4_uld_info {
351 const char *name;
352 void *handle;
353 unsigned int nrxq;
354 unsigned int rxq_size;
355 unsigned int ntxq;
356 bool ciq;
357 bool lro;
358 void *(*add)(const struct cxgb4_lld_info *p);
359 int (*rx_handler)(void *handle, const __be64 *rsp,
360 const struct pkt_gl *gl);
361 int (*state_change)(void *handle, enum cxgb4_state new_state);
362 int (*control)(void *handle, enum cxgb4_control control, ...);
363 int (*lro_rx_handler)(void *handle, const __be64 *rsp,
364 const struct pkt_gl *gl,
365 struct t4_lro_mgr *lro_mgr,
366 struct napi_struct *napi);
367 void (*lro_flush)(struct t4_lro_mgr *);
368 };
369
370 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
371 int cxgb4_unregister_uld(enum cxgb4_uld type);
372 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb);
373 int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb);
374 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo);
375 unsigned int cxgb4_port_chan(const struct net_device *dev);
376 unsigned int cxgb4_port_viid(const struct net_device *dev);
377 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid);
378 unsigned int cxgb4_port_idx(const struct net_device *dev);
379 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
380 unsigned int *idx);
381 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
382 unsigned short header_size,
383 unsigned short data_size_max,
384 unsigned short data_size_align,
385 unsigned int *mtu_idxp);
386 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
387 struct tp_tcp_stats *v6);
388 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
389 const unsigned int *pgsz_order);
390 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
391 unsigned int skb_len, unsigned int pull_len);
392 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size);
393 int cxgb4_flush_eq_cache(struct net_device *dev);
394 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte);
395 u64 cxgb4_read_sge_timestamp(struct net_device *dev);
396
397 enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS };
398 int cxgb4_bar2_sge_qregs(struct net_device *dev,
399 unsigned int qid,
400 enum cxgb4_bar2_qtype qtype,
401 int user,
402 u64 *pbar2_qoffset,
403 unsigned int *pbar2_qid);
404
405 #endif /* !__CXGB4_ULD_H */
406