1 /*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10 #include <linux/pci_regs.h>
11 #include <linux/pci_ids.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17 #include <linux/pci.h>
18 #include <linux/of.h>
19 #include <linux/delay.h>
20 #include <asm/opal.h>
21 #include <asm/msi_bitmap.h>
22 #include <asm/pnv-pci.h>
23 #include <asm/io.h>
24 #include <asm/reg.h>
25
26 #include "cxl.h"
27 #include <misc/cxl.h>
28
29
30 #define CXL_PCI_VSEC_ID 0x1280
31 #define CXL_VSEC_MIN_SIZE 0x80
32
33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43 #define CXL_STATUS_SECOND_PORT 0x80
44 #define CXL_STATUS_MSI_X_FULL 0x40
45 #define CXL_STATUS_MSI_X_SINGLE 0x20
46 #define CXL_STATUS_FLASH_RW 0x08
47 #define CXL_STATUS_FLASH_RO 0x04
48 #define CXL_STATUS_LOADABLE_AFU 0x02
49 #define CXL_STATUS_LOADABLE_PSL 0x01
50 /* If we see these features we won't try to use the card */
51 #define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
60 #define CXL_VSEC_PROTOCOL_MASK 0xe0
61 #define CXL_VSEC_PROTOCOL_1024TB 0x80
62 #define CXL_VSEC_PROTOCOL_512TB 0x40
63 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
65
66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0xc, dest)
68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xe, dest)
70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71 pci_read_config_byte(dev, vsec + 0xf, dest)
72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73 pci_read_config_word(dev, vsec + 0x10, dest)
74
75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76 pci_read_config_byte(dev, vsec + 0x13, dest)
77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78 pci_write_config_byte(dev, vsec + 0x13, val)
79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
82
83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x20, dest)
85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x24, dest)
87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x28, dest)
89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90 pci_read_config_dword(dev, vsec + 0x2c, dest)
91
92
93 /* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
95 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
96 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
97 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
98 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
99
100 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
101 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
102 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
103 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
104 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
105 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
107 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
108 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
109 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
110 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
112 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
113 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
114 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
115 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
116 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
117 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
118 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
119 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
120
121 static const struct pci_device_id cxl_pci_tbl[] = {
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
126 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
127 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
128 { PCI_DEVICE_CLASS(0x120000, ~0), },
129
130 { }
131 };
132 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
133
134
135 /*
136 * Mostly using these wrappers to avoid confusion:
137 * priv 1 is BAR2, while priv 2 is BAR0
138 */
p1_base(struct pci_dev * dev)139 static inline resource_size_t p1_base(struct pci_dev *dev)
140 {
141 return pci_resource_start(dev, 2);
142 }
143
p1_size(struct pci_dev * dev)144 static inline resource_size_t p1_size(struct pci_dev *dev)
145 {
146 return pci_resource_len(dev, 2);
147 }
148
p2_base(struct pci_dev * dev)149 static inline resource_size_t p2_base(struct pci_dev *dev)
150 {
151 return pci_resource_start(dev, 0);
152 }
153
p2_size(struct pci_dev * dev)154 static inline resource_size_t p2_size(struct pci_dev *dev)
155 {
156 return pci_resource_len(dev, 0);
157 }
158
find_cxl_vsec(struct pci_dev * dev)159 static int find_cxl_vsec(struct pci_dev *dev)
160 {
161 int vsec = 0;
162 u16 val;
163
164 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
165 pci_read_config_word(dev, vsec + 0x4, &val);
166 if (val == CXL_PCI_VSEC_ID)
167 return vsec;
168 }
169 return 0;
170
171 }
172
dump_cxl_config_space(struct pci_dev * dev)173 static void dump_cxl_config_space(struct pci_dev *dev)
174 {
175 int vsec;
176 u32 val;
177
178 dev_info(&dev->dev, "dump_cxl_config_space\n");
179
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
181 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
183 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
185 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
187 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
189 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
190 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
191 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
192
193 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
194 p1_base(dev), p1_size(dev));
195 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
196 p2_base(dev), p2_size(dev));
197 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
198 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
199
200 if (!(vsec = find_cxl_vsec(dev)))
201 return;
202
203 #define show_reg(name, what) \
204 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
205
206 pci_read_config_dword(dev, vsec + 0x0, &val);
207 show_reg("Cap ID", (val >> 0) & 0xffff);
208 show_reg("Cap Ver", (val >> 16) & 0xf);
209 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
210 pci_read_config_dword(dev, vsec + 0x4, &val);
211 show_reg("VSEC ID", (val >> 0) & 0xffff);
212 show_reg("VSEC Rev", (val >> 16) & 0xf);
213 show_reg("VSEC Length", (val >> 20) & 0xfff);
214 pci_read_config_dword(dev, vsec + 0x8, &val);
215 show_reg("Num AFUs", (val >> 0) & 0xff);
216 show_reg("Status", (val >> 8) & 0xff);
217 show_reg("Mode Control", (val >> 16) & 0xff);
218 show_reg("Reserved", (val >> 24) & 0xff);
219 pci_read_config_dword(dev, vsec + 0xc, &val);
220 show_reg("PSL Rev", (val >> 0) & 0xffff);
221 show_reg("CAIA Ver", (val >> 16) & 0xffff);
222 pci_read_config_dword(dev, vsec + 0x10, &val);
223 show_reg("Base Image Rev", (val >> 0) & 0xffff);
224 show_reg("Reserved", (val >> 16) & 0x0fff);
225 show_reg("Image Control", (val >> 28) & 0x3);
226 show_reg("Reserved", (val >> 30) & 0x1);
227 show_reg("Image Loaded", (val >> 31) & 0x1);
228
229 pci_read_config_dword(dev, vsec + 0x14, &val);
230 show_reg("Reserved", val);
231 pci_read_config_dword(dev, vsec + 0x18, &val);
232 show_reg("Reserved", val);
233 pci_read_config_dword(dev, vsec + 0x1c, &val);
234 show_reg("Reserved", val);
235
236 pci_read_config_dword(dev, vsec + 0x20, &val);
237 show_reg("AFU Descriptor Offset", val);
238 pci_read_config_dword(dev, vsec + 0x24, &val);
239 show_reg("AFU Descriptor Size", val);
240 pci_read_config_dword(dev, vsec + 0x28, &val);
241 show_reg("Problem State Offset", val);
242 pci_read_config_dword(dev, vsec + 0x2c, &val);
243 show_reg("Problem State Size", val);
244
245 pci_read_config_dword(dev, vsec + 0x30, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x34, &val);
248 show_reg("Reserved", val);
249 pci_read_config_dword(dev, vsec + 0x38, &val);
250 show_reg("Reserved", val);
251 pci_read_config_dword(dev, vsec + 0x3c, &val);
252 show_reg("Reserved", val);
253
254 pci_read_config_dword(dev, vsec + 0x40, &val);
255 show_reg("PSL Programming Port", val);
256 pci_read_config_dword(dev, vsec + 0x44, &val);
257 show_reg("PSL Programming Control", val);
258
259 pci_read_config_dword(dev, vsec + 0x48, &val);
260 show_reg("Reserved", val);
261 pci_read_config_dword(dev, vsec + 0x4c, &val);
262 show_reg("Reserved", val);
263
264 pci_read_config_dword(dev, vsec + 0x50, &val);
265 show_reg("Flash Address Register", val);
266 pci_read_config_dword(dev, vsec + 0x54, &val);
267 show_reg("Flash Size Register", val);
268 pci_read_config_dword(dev, vsec + 0x58, &val);
269 show_reg("Flash Status/Control Register", val);
270 pci_read_config_dword(dev, vsec + 0x58, &val);
271 show_reg("Flash Data Port", val);
272
273 #undef show_reg
274 }
275
dump_afu_descriptor(struct cxl_afu * afu)276 static void dump_afu_descriptor(struct cxl_afu *afu)
277 {
278 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
279 int i;
280
281 #define show_reg(name, what) \
282 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
283
284 val = AFUD_READ_INFO(afu);
285 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
286 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
287 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
288 show_reg("req_prog_mode", val & 0xffffULL);
289 afu_cr_num = AFUD_NUM_CRS(val);
290
291 val = AFUD_READ(afu, 0x8);
292 show_reg("Reserved", val);
293 val = AFUD_READ(afu, 0x10);
294 show_reg("Reserved", val);
295 val = AFUD_READ(afu, 0x18);
296 show_reg("Reserved", val);
297
298 val = AFUD_READ_CR(afu);
299 show_reg("Reserved", (val >> (63-7)) & 0xff);
300 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
301 afu_cr_len = AFUD_CR_LEN(val) * 256;
302
303 val = AFUD_READ_CR_OFF(afu);
304 afu_cr_off = val;
305 show_reg("AFU_CR_offset", val);
306
307 val = AFUD_READ_PPPSA(afu);
308 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
309 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
310
311 val = AFUD_READ_PPPSA_OFF(afu);
312 show_reg("PerProcessPSA_offset", val);
313
314 val = AFUD_READ_EB(afu);
315 show_reg("Reserved", (val >> (63-7)) & 0xff);
316 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
317
318 val = AFUD_READ_EB_OFF(afu);
319 show_reg("AFU_EB_offset", val);
320
321 for (i = 0; i < afu_cr_num; i++) {
322 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
323 show_reg("CR Vendor", val & 0xffff);
324 show_reg("CR Device", (val >> 16) & 0xffff);
325 }
326 #undef show_reg
327 }
328
329 #define P8_CAPP_UNIT0_ID 0xBA
330 #define P8_CAPP_UNIT1_ID 0XBE
331 #define P9_CAPP_UNIT0_ID 0xC0
332 #define P9_CAPP_UNIT1_ID 0xE0
333
get_phb_index(struct device_node * np,u32 * phb_index)334 static int get_phb_index(struct device_node *np, u32 *phb_index)
335 {
336 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
337 return -ENODEV;
338 return 0;
339 }
340
get_capp_unit_id(struct device_node * np,u32 phb_index)341 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
342 {
343 /*
344 * POWER 8:
345 * - For chips other than POWER8NVL, we only have CAPP 0,
346 * irrespective of which PHB is used.
347 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
348 * CAPP 1 is attached to PHB1.
349 */
350 if (cxl_is_power8()) {
351 if (!pvr_version_is(PVR_POWER8NVL))
352 return P8_CAPP_UNIT0_ID;
353
354 if (phb_index == 0)
355 return P8_CAPP_UNIT0_ID;
356
357 if (phb_index == 1)
358 return P8_CAPP_UNIT1_ID;
359 }
360
361 /*
362 * POWER 9:
363 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
364 * PEC1 (PHB1 - PHB2). No capi mode
365 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
366 */
367 if (cxl_is_power9()) {
368 if (phb_index == 0)
369 return P9_CAPP_UNIT0_ID;
370
371 if (phb_index == 3)
372 return P9_CAPP_UNIT1_ID;
373 }
374
375 return 0;
376 }
377
cxl_calc_capp_routing(struct pci_dev * dev,u64 * chipid,u32 * phb_index,u64 * capp_unit_id)378 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
379 u32 *phb_index, u64 *capp_unit_id)
380 {
381 int rc;
382 struct device_node *np;
383 const __be32 *prop;
384
385 if (!(np = pnv_pci_get_phb_node(dev)))
386 return -ENODEV;
387
388 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
389 np = of_get_next_parent(np);
390 if (!np)
391 return -ENODEV;
392
393 *chipid = be32_to_cpup(prop);
394
395 rc = get_phb_index(np, phb_index);
396 if (rc) {
397 pr_err("cxl: invalid phb index\n");
398 return rc;
399 }
400
401 *capp_unit_id = get_capp_unit_id(np, *phb_index);
402 of_node_put(np);
403 if (!*capp_unit_id) {
404 pr_err("cxl: invalid capp unit id\n");
405 return -ENODEV;
406 }
407
408 return 0;
409 }
410
cxl_get_xsl9_dsnctl(u64 capp_unit_id,u64 * reg)411 int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
412 {
413 u64 xsl_dsnctl;
414
415 /*
416 * CAPI Identifier bits [0:7]
417 * bit 61:60 MSI bits --> 0
418 * bit 59 TVT selector --> 0
419 */
420
421 /*
422 * Tell XSL where to route data to.
423 * The field chipid should match the PHB CAPI_CMPM register
424 */
425 xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
426 xsl_dsnctl |= (capp_unit_id << (63-15));
427
428 /* nMMU_ID Defaults to: b’000001001’*/
429 xsl_dsnctl |= ((u64)0x09 << (63-28));
430
431 if (!(cxl_is_power9_dd1())) {
432 /*
433 * Used to identify CAPI packets which should be sorted into
434 * the Non-Blocking queues by the PHB. This field should match
435 * the PHB PBL_NBW_CMPM register
436 * nbwind=0x03, bits [57:58], must include capi indicator.
437 * Not supported on P9 DD1.
438 */
439 xsl_dsnctl |= ((u64)0x03 << (63-47));
440
441 /*
442 * Upper 16b address bits of ASB_Notify messages sent to the
443 * system. Need to match the PHB’s ASN Compare/Mask Register.
444 * Not supported on P9 DD1.
445 */
446 xsl_dsnctl |= ((u64)0x04 << (63-55));
447 }
448
449 *reg = xsl_dsnctl;
450 return 0;
451 }
452
init_implementation_adapter_regs_psl9(struct cxl * adapter,struct pci_dev * dev)453 static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
454 struct pci_dev *dev)
455 {
456 u64 xsl_dsnctl, psl_fircntl;
457 u64 chipid;
458 u32 phb_index;
459 u64 capp_unit_id;
460 u64 psl_debug;
461 int rc;
462
463 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
464 if (rc)
465 return rc;
466
467 rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl);
468 if (rc)
469 return rc;
470
471 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
472
473 /* Set fir_cntl to recommended value for production env */
474 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
475 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
476 psl_fircntl |= 0x1ULL; /* ce_thresh */
477 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
478
479 /* vccredits=0x1 pcklat=0x4 */
480 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
481
482 /*
483 * For debugging with trace arrays.
484 * Configure RX trace 0 segmented mode.
485 * Configure CT trace 0 segmented mode.
486 * Configure LA0 trace 0 segmented mode.
487 * Configure LA1 trace 0 segmented mode.
488 */
489 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
490 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
491 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
492 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
493
494 /*
495 * A response to an ASB_Notify request is returned by the
496 * system as an MMIO write to the address defined in
497 * the PSL_TNR_ADDR register
498 */
499 /* PSL_TNR_ADDR */
500
501 /* NORST */
502 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
503
504 /* allocate the apc machines */
505 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
506
507 /* Disable vc dd1 fix */
508 if (cxl_is_power9_dd1())
509 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
510
511 /*
512 * Check if PSL has data-cache. We need to flush adapter datacache
513 * when as its about to be removed.
514 */
515 psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
516 if (psl_debug & CXL_PSL_DEBUG_CDC) {
517 dev_dbg(&dev->dev, "No data-cache present\n");
518 adapter->native->no_data_cache = true;
519 }
520
521 return 0;
522 }
523
init_implementation_adapter_regs_psl8(struct cxl * adapter,struct pci_dev * dev)524 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
525 {
526 u64 psl_dsnctl, psl_fircntl;
527 u64 chipid;
528 u32 phb_index;
529 u64 capp_unit_id;
530 int rc;
531
532 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
533 if (rc)
534 return rc;
535
536 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
537 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
538 /* Tell PSL where to route data to */
539 psl_dsnctl |= (chipid << (63-5));
540 psl_dsnctl |= (capp_unit_id << (63-13));
541
542 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
543 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
544 /* snoop write mask */
545 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
546 /* set fir_cntl to recommended value for production env */
547 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
548 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
549 psl_fircntl |= 0x1ULL; /* ce_thresh */
550 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
551 /* for debugging with trace arrays */
552 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
553
554 return 0;
555 }
556
init_implementation_adapter_regs_xsl(struct cxl * adapter,struct pci_dev * dev)557 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
558 {
559 u64 xsl_dsnctl;
560 u64 chipid;
561 u32 phb_index;
562 u64 capp_unit_id;
563 int rc;
564
565 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
566 if (rc)
567 return rc;
568
569 /* Tell XSL where to route data to */
570 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
571 xsl_dsnctl |= (capp_unit_id << (63-13));
572 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
573
574 return 0;
575 }
576
577 /* PSL & XSL */
578 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
579 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
580 /* For the PSL this is a multiple for 0 < n <= 7: */
581 #define PSL_2048_250MHZ_CYCLES 1
582
write_timebase_ctrl_psl9(struct cxl * adapter)583 static void write_timebase_ctrl_psl9(struct cxl *adapter)
584 {
585 cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
586 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
587 }
588
write_timebase_ctrl_psl8(struct cxl * adapter)589 static void write_timebase_ctrl_psl8(struct cxl *adapter)
590 {
591 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
592 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
593 }
594
595 /* XSL */
596 #define TBSYNC_ENA (1ULL << 63)
597 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
598 #define XSL_2000_CLOCKS 1
599 #define XSL_4000_CLOCKS 2
600 #define XSL_8000_CLOCKS 3
601
write_timebase_ctrl_xsl(struct cxl * adapter)602 static void write_timebase_ctrl_xsl(struct cxl *adapter)
603 {
604 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
605 TBSYNC_ENA |
606 TBSYNC_CAL(3) |
607 TBSYNC_CNT(XSL_4000_CLOCKS));
608 }
609
timebase_read_psl9(struct cxl * adapter)610 static u64 timebase_read_psl9(struct cxl *adapter)
611 {
612 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
613 }
614
timebase_read_psl8(struct cxl * adapter)615 static u64 timebase_read_psl8(struct cxl *adapter)
616 {
617 return cxl_p1_read(adapter, CXL_PSL_Timebase);
618 }
619
timebase_read_xsl(struct cxl * adapter)620 static u64 timebase_read_xsl(struct cxl *adapter)
621 {
622 return cxl_p1_read(adapter, CXL_XSL_Timebase);
623 }
624
cxl_setup_psl_timebase(struct cxl * adapter,struct pci_dev * dev)625 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
626 {
627 u64 psl_tb;
628 int delta;
629 unsigned int retry = 0;
630 struct device_node *np;
631
632 adapter->psl_timebase_synced = false;
633
634 if (!(np = pnv_pci_get_phb_node(dev)))
635 return;
636
637 /* Do not fail when CAPP timebase sync is not supported by OPAL */
638 of_node_get(np);
639 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
640 of_node_put(np);
641 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
642 return;
643 }
644 of_node_put(np);
645
646 /*
647 * Setup PSL Timebase Control and Status register
648 * with the recommended Timebase Sync Count value
649 */
650 adapter->native->sl_ops->write_timebase_ctrl(adapter);
651
652 /* Enable PSL Timebase */
653 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
654 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
655
656 /* Wait until CORE TB and PSL TB difference <= 16usecs */
657 do {
658 msleep(1);
659 if (retry++ > 5) {
660 dev_info(&dev->dev, "PSL timebase can't synchronize\n");
661 return;
662 }
663 psl_tb = adapter->native->sl_ops->timebase_read(adapter);
664 delta = mftb() - psl_tb;
665 if (delta < 0)
666 delta = -delta;
667 } while (tb_to_ns(delta) > 16000);
668
669 adapter->psl_timebase_synced = true;
670 return;
671 }
672
init_implementation_afu_regs_psl9(struct cxl_afu * afu)673 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
674 {
675 return 0;
676 }
677
init_implementation_afu_regs_psl8(struct cxl_afu * afu)678 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
679 {
680 /* read/write masks for this slice */
681 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
682 /* APC read/write masks for this slice */
683 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
684 /* for debugging with trace arrays */
685 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
686 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
687
688 return 0;
689 }
690
cxl_pci_setup_irq(struct cxl * adapter,unsigned int hwirq,unsigned int virq)691 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
692 unsigned int virq)
693 {
694 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
695
696 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
697 }
698
cxl_update_image_control(struct cxl * adapter)699 int cxl_update_image_control(struct cxl *adapter)
700 {
701 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
702 int rc;
703 int vsec;
704 u8 image_state;
705
706 if (!(vsec = find_cxl_vsec(dev))) {
707 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
708 return -ENODEV;
709 }
710
711 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
712 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
713 return rc;
714 }
715
716 if (adapter->perst_loads_image)
717 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
718 else
719 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
720
721 if (adapter->perst_select_user)
722 image_state |= CXL_VSEC_PERST_SELECT_USER;
723 else
724 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
725
726 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
727 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
728 return rc;
729 }
730
731 return 0;
732 }
733
cxl_pci_alloc_one_irq(struct cxl * adapter)734 int cxl_pci_alloc_one_irq(struct cxl *adapter)
735 {
736 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
737
738 return pnv_cxl_alloc_hwirqs(dev, 1);
739 }
740
cxl_pci_release_one_irq(struct cxl * adapter,int hwirq)741 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
742 {
743 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
744
745 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
746 }
747
cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges * irqs,struct cxl * adapter,unsigned int num)748 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
749 struct cxl *adapter, unsigned int num)
750 {
751 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
752
753 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
754 }
755
cxl_pci_release_irq_ranges(struct cxl_irq_ranges * irqs,struct cxl * adapter)756 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
757 struct cxl *adapter)
758 {
759 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
760
761 pnv_cxl_release_hwirq_ranges(irqs, dev);
762 }
763
setup_cxl_bars(struct pci_dev * dev)764 static int setup_cxl_bars(struct pci_dev *dev)
765 {
766 /* Safety check in case we get backported to < 3.17 without M64 */
767 if ((p1_base(dev) < 0x100000000ULL) ||
768 (p2_base(dev) < 0x100000000ULL)) {
769 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
770 return -ENODEV;
771 }
772
773 /*
774 * BAR 4/5 has a special meaning for CXL and must be programmed with a
775 * special value corresponding to the CXL protocol address range.
776 * For POWER 8/9 that means bits 48:49 must be set to 10
777 */
778 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
779 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
780
781 return 0;
782 }
783
784 #ifdef CONFIG_CXL_BIMODAL
785
786 struct cxl_switch_work {
787 struct pci_dev *dev;
788 struct work_struct work;
789 int vsec;
790 int mode;
791 };
792
switch_card_to_cxl(struct work_struct * work)793 static void switch_card_to_cxl(struct work_struct *work)
794 {
795 struct cxl_switch_work *switch_work =
796 container_of(work, struct cxl_switch_work, work);
797 struct pci_dev *dev = switch_work->dev;
798 struct pci_bus *bus = dev->bus;
799 struct pci_controller *hose = pci_bus_to_host(bus);
800 struct pci_dev *bridge;
801 struct pnv_php_slot *php_slot;
802 unsigned int devfn;
803 u8 val;
804 int rc;
805
806 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
807 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
808 bus_list);
809 if (!bridge) {
810 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
811 goto err_dev_put;
812 }
813
814 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
815 if (!php_slot) {
816 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
817 "information. You may need to upgrade "
818 "skiboot. Aborting.\n");
819 goto err_dev_put;
820 }
821
822 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
823 if (rc) {
824 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
825 goto err_dev_put;
826 }
827 devfn = dev->devfn;
828
829 /* Release the reference obtained in cxl_check_and_switch_mode() */
830 pci_dev_put(dev);
831
832 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
833 pci_lock_rescan_remove();
834 pci_hp_remove_devices(bridge->subordinate);
835 pci_unlock_rescan_remove();
836
837 /* Switch the CXL protocol on the card */
838 if (switch_work->mode == CXL_BIMODE_CXL) {
839 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
840 val &= ~CXL_VSEC_PROTOCOL_MASK;
841 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
842 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
843 if (rc) {
844 dev_err(&bus->dev, "cxl: Failed to enable kernel API"
845 " on real PHB, aborting\n");
846 goto err_free_work;
847 }
848 } else {
849 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
850 goto err_free_work;
851 }
852
853 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
854 if (rc) {
855 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
856 goto err_free_work;
857 }
858
859 /*
860 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
861 * we must wait 100ms after this mode switch before touching PCIe config
862 * space.
863 */
864 msleep(100);
865
866 /*
867 * Hot reset to cause the card to come back in cxl mode. A
868 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
869 * in skiboot, so we use a hot reset instead.
870 *
871 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
872 * guaranteed to sit directly under the root port, and setting the reset
873 * state on a device directly under the root port is equivalent to doing
874 * it on the root port iself.
875 */
876 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
877 pci_set_pcie_reset_state(bridge, pcie_hot_reset);
878 pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
879
880 dev_dbg(&bus->dev, "cxl: Offlining slot\n");
881 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
882 if (rc) {
883 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
884 goto err_free_work;
885 }
886
887 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
888 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
889 if (rc) {
890 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
891 goto err_free_work;
892 }
893
894 pci_lock_rescan_remove();
895 pci_hp_add_devices(bridge->subordinate);
896 pci_unlock_rescan_remove();
897
898 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
899 kfree(switch_work);
900 return;
901
902 err_dev_put:
903 /* Release the reference obtained in cxl_check_and_switch_mode() */
904 pci_dev_put(dev);
905 err_free_work:
906 kfree(switch_work);
907 }
908
cxl_check_and_switch_mode(struct pci_dev * dev,int mode,int vsec)909 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
910 {
911 struct cxl_switch_work *work;
912 u8 val;
913 int rc;
914
915 if (!cpu_has_feature(CPU_FTR_HVMODE))
916 return -ENODEV;
917
918 if (!vsec) {
919 vsec = find_cxl_vsec(dev);
920 if (!vsec) {
921 dev_info(&dev->dev, "CXL VSEC not found\n");
922 return -ENODEV;
923 }
924 }
925
926 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
927 if (rc) {
928 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
929 return rc;
930 }
931
932 if (mode == CXL_BIMODE_PCI) {
933 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
934 dev_info(&dev->dev, "Card is already in PCI mode\n");
935 return 0;
936 }
937 /*
938 * TODO: Before it's safe to switch the card back to PCI mode
939 * we need to disable the CAPP and make sure any cachelines the
940 * card holds have been flushed out. Needs skiboot support.
941 */
942 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
943 return -EIO;
944 }
945
946 if (val & CXL_VSEC_PROTOCOL_ENABLE) {
947 dev_info(&dev->dev, "Card is already in CXL mode\n");
948 return 0;
949 }
950
951 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
952 "to switch to CXL mode\n");
953
954 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
955 if (!work)
956 return -ENOMEM;
957
958 pci_dev_get(dev);
959 work->dev = dev;
960 work->vsec = vsec;
961 work->mode = mode;
962 INIT_WORK(&work->work, switch_card_to_cxl);
963
964 schedule_work(&work->work);
965
966 /*
967 * We return a failure now to abort the driver init. Once the
968 * link has been cycled and the card is in cxl mode we will
969 * come back (possibly using the generic cxl driver), but
970 * return success as the card should then be in cxl mode.
971 *
972 * TODO: What if the card comes back in PCI mode even after
973 * the switch? Don't want to spin endlessly.
974 */
975 return -EBUSY;
976 }
977 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
978
979 #endif /* CONFIG_CXL_BIMODAL */
980
setup_cxl_protocol_area(struct pci_dev * dev)981 static int setup_cxl_protocol_area(struct pci_dev *dev)
982 {
983 u8 val;
984 int rc;
985 int vsec = find_cxl_vsec(dev);
986
987 if (!vsec) {
988 dev_info(&dev->dev, "CXL VSEC not found\n");
989 return -ENODEV;
990 }
991
992 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
993 if (rc) {
994 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
995 return rc;
996 }
997
998 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
999 dev_err(&dev->dev, "Card not in CAPI mode!\n");
1000 return -EIO;
1001 }
1002
1003 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
1004 val &= ~CXL_VSEC_PROTOCOL_MASK;
1005 val |= CXL_VSEC_PROTOCOL_256TB;
1006 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
1007 if (rc) {
1008 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
1009 return rc;
1010 }
1011 }
1012
1013 return 0;
1014 }
1015
pci_map_slice_regs(struct cxl_afu * afu,struct cxl * adapter,struct pci_dev * dev)1016 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1017 {
1018 u64 p1n_base, p2n_base, afu_desc;
1019 const u64 p1n_size = 0x100;
1020 const u64 p2n_size = 0x1000;
1021
1022 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
1023 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
1024 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
1025 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1026
1027 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
1028 goto err;
1029 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1030 goto err1;
1031 if (afu_desc) {
1032 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
1033 goto err2;
1034 }
1035
1036 return 0;
1037 err2:
1038 iounmap(afu->p2n_mmio);
1039 err1:
1040 iounmap(afu->native->p1n_mmio);
1041 err:
1042 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1043 return -ENOMEM;
1044 }
1045
pci_unmap_slice_regs(struct cxl_afu * afu)1046 static void pci_unmap_slice_regs(struct cxl_afu *afu)
1047 {
1048 if (afu->p2n_mmio) {
1049 iounmap(afu->p2n_mmio);
1050 afu->p2n_mmio = NULL;
1051 }
1052 if (afu->native->p1n_mmio) {
1053 iounmap(afu->native->p1n_mmio);
1054 afu->native->p1n_mmio = NULL;
1055 }
1056 if (afu->native->afu_desc_mmio) {
1057 iounmap(afu->native->afu_desc_mmio);
1058 afu->native->afu_desc_mmio = NULL;
1059 }
1060 }
1061
cxl_pci_release_afu(struct device * dev)1062 void cxl_pci_release_afu(struct device *dev)
1063 {
1064 struct cxl_afu *afu = to_cxl_afu(dev);
1065
1066 pr_devel("%s\n", __func__);
1067
1068 idr_destroy(&afu->contexts_idr);
1069 cxl_release_spa(afu);
1070
1071 kfree(afu->native);
1072 kfree(afu);
1073 }
1074
1075 /* Expects AFU struct to have recently been zeroed out */
cxl_read_afu_descriptor(struct cxl_afu * afu)1076 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1077 {
1078 u64 val;
1079
1080 val = AFUD_READ_INFO(afu);
1081 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1082 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
1083 afu->crs_num = AFUD_NUM_CRS(val);
1084
1085 if (AFUD_AFU_DIRECTED(val))
1086 afu->modes_supported |= CXL_MODE_DIRECTED;
1087 if (AFUD_DEDICATED_PROCESS(val))
1088 afu->modes_supported |= CXL_MODE_DEDICATED;
1089 if (AFUD_TIME_SLICED(val))
1090 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1091
1092 val = AFUD_READ_PPPSA(afu);
1093 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1094 afu->psa = AFUD_PPPSA_PSA(val);
1095 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
1096 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
1097
1098 val = AFUD_READ_CR(afu);
1099 afu->crs_len = AFUD_CR_LEN(val) * 256;
1100 afu->crs_offset = AFUD_READ_CR_OFF(afu);
1101
1102
1103 /* eb_len is in multiple of 4K */
1104 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1105 afu->eb_offset = AFUD_READ_EB_OFF(afu);
1106
1107 /* eb_off is 4K aligned so lower 12 bits are always zero */
1108 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1109 dev_warn(&afu->dev,
1110 "Invalid AFU error buffer offset %Lx\n",
1111 afu->eb_offset);
1112 dev_info(&afu->dev,
1113 "Ignoring AFU error buffer in the descriptor\n");
1114 /* indicate that no afu buffer exists */
1115 afu->eb_len = 0;
1116 }
1117
1118 return 0;
1119 }
1120
cxl_afu_descriptor_looks_ok(struct cxl_afu * afu)1121 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1122 {
1123 int i, rc;
1124 u32 val;
1125
1126 if (afu->psa && afu->adapter->ps_size <
1127 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
1128 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1129 return -ENODEV;
1130 }
1131
1132 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
1133 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
1134
1135 for (i = 0; i < afu->crs_num; i++) {
1136 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1137 if (rc || val == 0) {
1138 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1139 return -EINVAL;
1140 }
1141 }
1142
1143 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1144 /*
1145 * We could also check this for the dedicated process model
1146 * since the architecture indicates it should be set to 1, but
1147 * in that case we ignore the value and I'd rather not risk
1148 * breaking any existing dedicated process AFUs that left it as
1149 * 0 (not that I'm aware of any). It is clearly an error for an
1150 * AFU directed AFU to set this to 0, and would have previously
1151 * triggered a bug resulting in the maximum not being enforced
1152 * at all since idr_alloc treats 0 as no maximum.
1153 */
1154 dev_err(&afu->dev, "AFU does not support any processes\n");
1155 return -EINVAL;
1156 }
1157
1158 return 0;
1159 }
1160
sanitise_afu_regs_psl9(struct cxl_afu * afu)1161 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1162 {
1163 u64 reg;
1164
1165 /*
1166 * Clear out any regs that contain either an IVTE or address or may be
1167 * waiting on an acknowledgment to try to be a bit safer as we bring
1168 * it online
1169 */
1170 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1171 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1172 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1173 if (cxl_ops->afu_reset(afu))
1174 return -EIO;
1175 if (cxl_afu_disable(afu))
1176 return -EIO;
1177 if (cxl_psl_purge(afu))
1178 return -EIO;
1179 }
1180 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1181 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1182 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1183 if (reg) {
1184 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1185 if (reg & CXL_PSL9_DSISR_An_TF)
1186 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1187 else
1188 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1189 }
1190 if (afu->adapter->native->sl_ops->register_serr_irq) {
1191 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1192 if (reg) {
1193 if (reg & ~0x000000007fffffff)
1194 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1195 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1196 }
1197 }
1198 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1199 if (reg) {
1200 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1201 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1202 }
1203
1204 return 0;
1205 }
1206
sanitise_afu_regs_psl8(struct cxl_afu * afu)1207 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
1208 {
1209 u64 reg;
1210
1211 /*
1212 * Clear out any regs that contain either an IVTE or address or may be
1213 * waiting on an acknowledgement to try to be a bit safer as we bring
1214 * it online
1215 */
1216 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1217 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1218 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1219 if (cxl_ops->afu_reset(afu))
1220 return -EIO;
1221 if (cxl_afu_disable(afu))
1222 return -EIO;
1223 if (cxl_psl_purge(afu))
1224 return -EIO;
1225 }
1226 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1227 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1228 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1229 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1230 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1231 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1232 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1233 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1234 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1235 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1236 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1237 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1238 if (reg) {
1239 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1240 if (reg & CXL_PSL_DSISR_TRANS)
1241 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1242 else
1243 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1244 }
1245 if (afu->adapter->native->sl_ops->register_serr_irq) {
1246 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1247 if (reg) {
1248 if (reg & ~0xffff)
1249 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1250 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1251 }
1252 }
1253 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1254 if (reg) {
1255 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1256 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1257 }
1258
1259 return 0;
1260 }
1261
1262 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1263 /*
1264 * afu_eb_read:
1265 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1266 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1267 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1268 */
cxl_pci_afu_read_err_buffer(struct cxl_afu * afu,char * buf,loff_t off,size_t count)1269 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1270 loff_t off, size_t count)
1271 {
1272 loff_t aligned_start, aligned_end;
1273 size_t aligned_length;
1274 void *tbuf;
1275 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1276
1277 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1278 return 0;
1279
1280 /* calculate aligned read window */
1281 count = min((size_t)(afu->eb_len - off), count);
1282 aligned_start = round_down(off, 8);
1283 aligned_end = round_up(off + count, 8);
1284 aligned_length = aligned_end - aligned_start;
1285
1286 /* max we can copy in one read is PAGE_SIZE */
1287 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1288 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1289 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1290 }
1291
1292 /* use bounce buffer for copy */
1293 tbuf = (void *)__get_free_page(GFP_KERNEL);
1294 if (!tbuf)
1295 return -ENOMEM;
1296
1297 /* perform aligned read from the mmio region */
1298 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1299 memcpy(buf, tbuf + (off & 0x7), count);
1300
1301 free_page((unsigned long)tbuf);
1302
1303 return count;
1304 }
1305
pci_configure_afu(struct cxl_afu * afu,struct cxl * adapter,struct pci_dev * dev)1306 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1307 {
1308 int rc;
1309
1310 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1311 return rc;
1312
1313 if (adapter->native->sl_ops->sanitise_afu_regs) {
1314 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1315 if (rc)
1316 goto err1;
1317 }
1318
1319 /* We need to reset the AFU before we can read the AFU descriptor */
1320 if ((rc = cxl_ops->afu_reset(afu)))
1321 goto err1;
1322
1323 if (cxl_verbose)
1324 dump_afu_descriptor(afu);
1325
1326 if ((rc = cxl_read_afu_descriptor(afu)))
1327 goto err1;
1328
1329 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1330 goto err1;
1331
1332 if (adapter->native->sl_ops->afu_regs_init)
1333 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1334 goto err1;
1335
1336 if (adapter->native->sl_ops->register_serr_irq)
1337 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1338 goto err1;
1339
1340 if ((rc = cxl_native_register_psl_irq(afu)))
1341 goto err2;
1342
1343 atomic_set(&afu->configured_state, 0);
1344 return 0;
1345
1346 err2:
1347 if (adapter->native->sl_ops->release_serr_irq)
1348 adapter->native->sl_ops->release_serr_irq(afu);
1349 err1:
1350 pci_unmap_slice_regs(afu);
1351 return rc;
1352 }
1353
pci_deconfigure_afu(struct cxl_afu * afu)1354 static void pci_deconfigure_afu(struct cxl_afu *afu)
1355 {
1356 /*
1357 * It's okay to deconfigure when AFU is already locked, otherwise wait
1358 * until there are no readers
1359 */
1360 if (atomic_read(&afu->configured_state) != -1) {
1361 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1362 schedule();
1363 }
1364 cxl_native_release_psl_irq(afu);
1365 if (afu->adapter->native->sl_ops->release_serr_irq)
1366 afu->adapter->native->sl_ops->release_serr_irq(afu);
1367 pci_unmap_slice_regs(afu);
1368 }
1369
pci_init_afu(struct cxl * adapter,int slice,struct pci_dev * dev)1370 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1371 {
1372 struct cxl_afu *afu;
1373 int rc = -ENOMEM;
1374
1375 afu = cxl_alloc_afu(adapter, slice);
1376 if (!afu)
1377 return -ENOMEM;
1378
1379 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1380 if (!afu->native)
1381 goto err_free_afu;
1382
1383 mutex_init(&afu->native->spa_mutex);
1384
1385 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1386 if (rc)
1387 goto err_free_native;
1388
1389 rc = pci_configure_afu(afu, adapter, dev);
1390 if (rc)
1391 goto err_free_native;
1392
1393 /* Don't care if this fails */
1394 cxl_debugfs_afu_add(afu);
1395
1396 /*
1397 * After we call this function we must not free the afu directly, even
1398 * if it returns an error!
1399 */
1400 if ((rc = cxl_register_afu(afu)))
1401 goto err_put1;
1402
1403 if ((rc = cxl_sysfs_afu_add(afu)))
1404 goto err_put1;
1405
1406 adapter->afu[afu->slice] = afu;
1407
1408 if ((rc = cxl_pci_vphb_add(afu)))
1409 dev_info(&afu->dev, "Can't register vPHB\n");
1410
1411 return 0;
1412
1413 err_put1:
1414 pci_deconfigure_afu(afu);
1415 cxl_debugfs_afu_remove(afu);
1416 device_unregister(&afu->dev);
1417 return rc;
1418
1419 err_free_native:
1420 kfree(afu->native);
1421 err_free_afu:
1422 kfree(afu);
1423 return rc;
1424
1425 }
1426
cxl_pci_remove_afu(struct cxl_afu * afu)1427 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1428 {
1429 pr_devel("%s\n", __func__);
1430
1431 if (!afu)
1432 return;
1433
1434 cxl_pci_vphb_remove(afu);
1435 cxl_sysfs_afu_remove(afu);
1436 cxl_debugfs_afu_remove(afu);
1437
1438 spin_lock(&afu->adapter->afu_list_lock);
1439 afu->adapter->afu[afu->slice] = NULL;
1440 spin_unlock(&afu->adapter->afu_list_lock);
1441
1442 cxl_context_detach_all(afu);
1443 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1444
1445 pci_deconfigure_afu(afu);
1446 device_unregister(&afu->dev);
1447 }
1448
cxl_pci_reset(struct cxl * adapter)1449 int cxl_pci_reset(struct cxl *adapter)
1450 {
1451 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1452 int rc;
1453
1454 if (adapter->perst_same_image) {
1455 dev_warn(&dev->dev,
1456 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1457 return -EINVAL;
1458 }
1459
1460 dev_info(&dev->dev, "CXL reset\n");
1461
1462 /*
1463 * The adapter is about to be reset, so ignore errors.
1464 */
1465 cxl_data_cache_flush(adapter);
1466
1467 /* pcie_warm_reset requests a fundamental pci reset which includes a
1468 * PERST assert/deassert. PERST triggers a loading of the image
1469 * if "user" or "factory" is selected in sysfs */
1470 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1471 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1472 return rc;
1473 }
1474
1475 return rc;
1476 }
1477
cxl_map_adapter_regs(struct cxl * adapter,struct pci_dev * dev)1478 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1479 {
1480 if (pci_request_region(dev, 2, "priv 2 regs"))
1481 goto err1;
1482 if (pci_request_region(dev, 0, "priv 1 regs"))
1483 goto err2;
1484
1485 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1486 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1487
1488 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1489 goto err3;
1490
1491 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1492 goto err4;
1493
1494 return 0;
1495
1496 err4:
1497 iounmap(adapter->native->p1_mmio);
1498 adapter->native->p1_mmio = NULL;
1499 err3:
1500 pci_release_region(dev, 0);
1501 err2:
1502 pci_release_region(dev, 2);
1503 err1:
1504 return -ENOMEM;
1505 }
1506
cxl_unmap_adapter_regs(struct cxl * adapter)1507 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1508 {
1509 if (adapter->native->p1_mmio) {
1510 iounmap(adapter->native->p1_mmio);
1511 adapter->native->p1_mmio = NULL;
1512 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1513 }
1514 if (adapter->native->p2_mmio) {
1515 iounmap(adapter->native->p2_mmio);
1516 adapter->native->p2_mmio = NULL;
1517 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1518 }
1519 }
1520
cxl_read_vsec(struct cxl * adapter,struct pci_dev * dev)1521 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1522 {
1523 int vsec;
1524 u32 afu_desc_off, afu_desc_size;
1525 u32 ps_off, ps_size;
1526 u16 vseclen;
1527 u8 image_state;
1528
1529 if (!(vsec = find_cxl_vsec(dev))) {
1530 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1531 return -ENODEV;
1532 }
1533
1534 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1535 if (vseclen < CXL_VSEC_MIN_SIZE) {
1536 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1537 return -EINVAL;
1538 }
1539
1540 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1541 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1542 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1543 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1544 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1545 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1546 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1547 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1548 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1549
1550 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1551 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1552 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1553 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1554 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1555
1556 /* Convert everything to bytes, because there is NO WAY I'd look at the
1557 * code a month later and forget what units these are in ;-) */
1558 adapter->native->ps_off = ps_off * 64 * 1024;
1559 adapter->ps_size = ps_size * 64 * 1024;
1560 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1561 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1562
1563 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1564 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1565
1566 return 0;
1567 }
1568
1569 /*
1570 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1571 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1572 * reported. Mask this error in the Uncorrectable Error Mask Register.
1573 *
1574 * The upper nibble of the PSL revision is used to distinguish between
1575 * different cards. The affected ones have it set to 0.
1576 */
cxl_fixup_malformed_tlp(struct cxl * adapter,struct pci_dev * dev)1577 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1578 {
1579 int aer;
1580 u32 data;
1581
1582 if (adapter->psl_rev & 0xf000)
1583 return;
1584 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1585 return;
1586 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1587 if (data & PCI_ERR_UNC_MALF_TLP)
1588 if (data & PCI_ERR_UNC_INTN)
1589 return;
1590 data |= PCI_ERR_UNC_MALF_TLP;
1591 data |= PCI_ERR_UNC_INTN;
1592 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1593 }
1594
cxl_compatible_caia_version(struct cxl * adapter)1595 static bool cxl_compatible_caia_version(struct cxl *adapter)
1596 {
1597 if (cxl_is_power8() && (adapter->caia_major == 1))
1598 return true;
1599
1600 if (cxl_is_power9() && (adapter->caia_major == 2))
1601 return true;
1602
1603 return false;
1604 }
1605
cxl_vsec_looks_ok(struct cxl * adapter,struct pci_dev * dev)1606 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1607 {
1608 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1609 return -EBUSY;
1610
1611 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1612 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1613 return -EINVAL;
1614 }
1615
1616 if (!cxl_compatible_caia_version(adapter)) {
1617 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1618 adapter->caia_major);
1619 return -ENODEV;
1620 }
1621
1622 if (!adapter->slices) {
1623 /* Once we support dynamic reprogramming we can use the card if
1624 * it supports loadable AFUs */
1625 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1626 return -EINVAL;
1627 }
1628
1629 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1630 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1631 return -EINVAL;
1632 }
1633
1634 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1635 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1636 "available in BAR2: 0x%llx > 0x%llx\n",
1637 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1638 return -EINVAL;
1639 }
1640
1641 return 0;
1642 }
1643
cxl_pci_read_adapter_vpd(struct cxl * adapter,void * buf,size_t len)1644 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1645 {
1646 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1647 }
1648
cxl_release_adapter(struct device * dev)1649 static void cxl_release_adapter(struct device *dev)
1650 {
1651 struct cxl *adapter = to_cxl_adapter(dev);
1652
1653 pr_devel("cxl_release_adapter\n");
1654
1655 cxl_remove_adapter_nr(adapter);
1656
1657 kfree(adapter->native);
1658 kfree(adapter);
1659 }
1660
1661 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1662
sanitise_adapter_regs(struct cxl * adapter)1663 static int sanitise_adapter_regs(struct cxl *adapter)
1664 {
1665 int rc = 0;
1666
1667 /* Clear PSL tberror bit by writing 1 to it */
1668 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1669
1670 if (adapter->native->sl_ops->invalidate_all) {
1671 /* do not invalidate ERAT entries when not reloading on PERST */
1672 if (cxl_is_power9() && (adapter->perst_loads_image))
1673 return 0;
1674 rc = adapter->native->sl_ops->invalidate_all(adapter);
1675 }
1676
1677 return rc;
1678 }
1679
1680 /* This should contain *only* operations that can safely be done in
1681 * both creation and recovery.
1682 */
cxl_configure_adapter(struct cxl * adapter,struct pci_dev * dev)1683 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1684 {
1685 int rc;
1686
1687 adapter->dev.parent = &dev->dev;
1688 adapter->dev.release = cxl_release_adapter;
1689 pci_set_drvdata(dev, adapter);
1690
1691 rc = pci_enable_device(dev);
1692 if (rc) {
1693 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1694 return rc;
1695 }
1696
1697 if ((rc = cxl_read_vsec(adapter, dev)))
1698 return rc;
1699
1700 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1701 return rc;
1702
1703 cxl_fixup_malformed_tlp(adapter, dev);
1704
1705 if ((rc = setup_cxl_bars(dev)))
1706 return rc;
1707
1708 if ((rc = setup_cxl_protocol_area(dev)))
1709 return rc;
1710
1711 if ((rc = cxl_update_image_control(adapter)))
1712 return rc;
1713
1714 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1715 return rc;
1716
1717 if ((rc = sanitise_adapter_regs(adapter)))
1718 goto err;
1719
1720 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1721 goto err;
1722
1723 /* Required for devices using CAPP DMA mode, harmless for others */
1724 pci_set_master(dev);
1725
1726 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1727 goto err;
1728
1729 /* If recovery happened, the last step is to turn on snooping.
1730 * In the non-recovery case this has no effect */
1731 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1732 goto err;
1733
1734 /* Ignore error, adapter init is not dependant on timebase sync */
1735 cxl_setup_psl_timebase(adapter, dev);
1736
1737 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1738 goto err;
1739
1740 return 0;
1741
1742 err:
1743 cxl_unmap_adapter_regs(adapter);
1744 return rc;
1745
1746 }
1747
cxl_deconfigure_adapter(struct cxl * adapter)1748 static void cxl_deconfigure_adapter(struct cxl *adapter)
1749 {
1750 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1751
1752 cxl_native_release_psl_err_irq(adapter);
1753 cxl_unmap_adapter_regs(adapter);
1754
1755 pci_disable_device(pdev);
1756 }
1757
1758 static const struct cxl_service_layer_ops psl9_ops = {
1759 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1760 .invalidate_all = cxl_invalidate_all_psl9,
1761 .afu_regs_init = init_implementation_afu_regs_psl9,
1762 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1763 .register_serr_irq = cxl_native_register_serr_irq,
1764 .release_serr_irq = cxl_native_release_serr_irq,
1765 .handle_interrupt = cxl_irq_psl9,
1766 .fail_irq = cxl_fail_irq_psl,
1767 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1768 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1769 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1770 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1771 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1772 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1773 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1774 .debugfs_stop_trace = cxl_stop_trace_psl9,
1775 .write_timebase_ctrl = write_timebase_ctrl_psl9,
1776 .timebase_read = timebase_read_psl9,
1777 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1778 .needs_reset_before_disable = true,
1779 };
1780
1781 static const struct cxl_service_layer_ops psl8_ops = {
1782 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1783 .invalidate_all = cxl_invalidate_all_psl8,
1784 .afu_regs_init = init_implementation_afu_regs_psl8,
1785 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1786 .register_serr_irq = cxl_native_register_serr_irq,
1787 .release_serr_irq = cxl_native_release_serr_irq,
1788 .handle_interrupt = cxl_irq_psl8,
1789 .fail_irq = cxl_fail_irq_psl,
1790 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1791 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1792 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1793 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1794 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1795 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1796 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1797 .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1798 .debugfs_stop_trace = cxl_stop_trace_psl8,
1799 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1800 .timebase_read = timebase_read_psl8,
1801 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1802 .needs_reset_before_disable = true,
1803 };
1804
1805 static const struct cxl_service_layer_ops xsl_ops = {
1806 .adapter_regs_init = init_implementation_adapter_regs_xsl,
1807 .invalidate_all = cxl_invalidate_all_psl8,
1808 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1809 .handle_interrupt = cxl_irq_psl8,
1810 .fail_irq = cxl_fail_irq_psl,
1811 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1812 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1813 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1814 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1815 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
1816 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1817 .timebase_read = timebase_read_xsl,
1818 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1819 };
1820
set_sl_ops(struct cxl * adapter,struct pci_dev * dev)1821 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1822 {
1823 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1824 /* Mellanox CX-4 */
1825 dev_info(&dev->dev, "Device uses an XSL\n");
1826 adapter->native->sl_ops = &xsl_ops;
1827 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1828 } else {
1829 if (cxl_is_power8()) {
1830 dev_info(&dev->dev, "Device uses a PSL8\n");
1831 adapter->native->sl_ops = &psl8_ops;
1832 } else {
1833 dev_info(&dev->dev, "Device uses a PSL9\n");
1834 adapter->native->sl_ops = &psl9_ops;
1835 }
1836 }
1837 }
1838
1839
cxl_pci_init_adapter(struct pci_dev * dev)1840 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1841 {
1842 struct cxl *adapter;
1843 int rc;
1844
1845 adapter = cxl_alloc_adapter();
1846 if (!adapter)
1847 return ERR_PTR(-ENOMEM);
1848
1849 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1850 if (!adapter->native) {
1851 rc = -ENOMEM;
1852 goto err_release;
1853 }
1854
1855 set_sl_ops(adapter, dev);
1856
1857 /* Set defaults for parameters which need to persist over
1858 * configure/reconfigure
1859 */
1860 adapter->perst_loads_image = true;
1861 adapter->perst_same_image = false;
1862
1863 rc = cxl_configure_adapter(adapter, dev);
1864 if (rc) {
1865 pci_disable_device(dev);
1866 goto err_release;
1867 }
1868
1869 /* Don't care if this one fails: */
1870 cxl_debugfs_adapter_add(adapter);
1871
1872 /*
1873 * After we call this function we must not free the adapter directly,
1874 * even if it returns an error!
1875 */
1876 if ((rc = cxl_register_adapter(adapter)))
1877 goto err_put1;
1878
1879 if ((rc = cxl_sysfs_adapter_add(adapter)))
1880 goto err_put1;
1881
1882 /* Release the context lock as adapter is configured */
1883 cxl_adapter_context_unlock(adapter);
1884
1885 return adapter;
1886
1887 err_put1:
1888 /* This should mirror cxl_remove_adapter, except without the
1889 * sysfs parts
1890 */
1891 cxl_debugfs_adapter_remove(adapter);
1892 cxl_deconfigure_adapter(adapter);
1893 device_unregister(&adapter->dev);
1894 return ERR_PTR(rc);
1895
1896 err_release:
1897 cxl_release_adapter(&adapter->dev);
1898 return ERR_PTR(rc);
1899 }
1900
cxl_pci_remove_adapter(struct cxl * adapter)1901 static void cxl_pci_remove_adapter(struct cxl *adapter)
1902 {
1903 pr_devel("cxl_remove_adapter\n");
1904
1905 cxl_sysfs_adapter_remove(adapter);
1906 cxl_debugfs_adapter_remove(adapter);
1907
1908 /*
1909 * Flush adapter datacache as its about to be removed.
1910 */
1911 cxl_data_cache_flush(adapter);
1912
1913 cxl_deconfigure_adapter(adapter);
1914
1915 device_unregister(&adapter->dev);
1916 }
1917
1918 #define CXL_MAX_PCIEX_PARENT 2
1919
cxl_slot_is_switched(struct pci_dev * dev)1920 int cxl_slot_is_switched(struct pci_dev *dev)
1921 {
1922 struct device_node *np;
1923 int depth = 0;
1924 const __be32 *prop;
1925
1926 if (!(np = pci_device_to_OF_node(dev))) {
1927 pr_err("cxl: np = NULL\n");
1928 return -ENODEV;
1929 }
1930 of_node_get(np);
1931 while (np) {
1932 np = of_get_next_parent(np);
1933 prop = of_get_property(np, "device_type", NULL);
1934 if (!prop || strcmp((char *)prop, "pciex"))
1935 break;
1936 depth++;
1937 }
1938 of_node_put(np);
1939 return (depth > CXL_MAX_PCIEX_PARENT);
1940 }
1941
cxl_slot_is_supported(struct pci_dev * dev,int flags)1942 bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1943 {
1944 if (!cpu_has_feature(CPU_FTR_HVMODE))
1945 return false;
1946
1947 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1948 /*
1949 * CAPP DMA mode is technically supported on regular P8, but
1950 * will EEH if the card attempts to access memory < 4GB, which
1951 * we cannot realistically avoid. We might be able to work
1952 * around the issue, but until then return unsupported:
1953 */
1954 return false;
1955 }
1956
1957 if (cxl_slot_is_switched(dev))
1958 return false;
1959
1960 /*
1961 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1962 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1963 * served basis, which is racy to check from here. If we need to
1964 * support this in future we might need to consider having this
1965 * function effectively reserve it ahead of time.
1966 *
1967 * Currently, the only user of this API is the Mellanox CX4, which is
1968 * only supported on P8NVL due to the above mentioned limitation of
1969 * CAPP DMA mode and therefore does not need to worry about this. If the
1970 * issue with CAPP DMA mode is later worked around on P8 we might need
1971 * to revisit this.
1972 */
1973
1974 return true;
1975 }
1976 EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
1977
1978
cxl_probe(struct pci_dev * dev,const struct pci_device_id * id)1979 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1980 {
1981 struct cxl *adapter;
1982 int slice;
1983 int rc;
1984
1985 if (cxl_pci_is_vphb_device(dev)) {
1986 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1987 return -ENODEV;
1988 }
1989
1990 if (cxl_slot_is_switched(dev)) {
1991 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1992 return -ENODEV;
1993 }
1994
1995 if (cxl_is_power9() && !radix_enabled()) {
1996 dev_info(&dev->dev, "Only Radix mode supported\n");
1997 return -ENODEV;
1998 }
1999
2000 if (cxl_verbose)
2001 dump_cxl_config_space(dev);
2002
2003 adapter = cxl_pci_init_adapter(dev);
2004 if (IS_ERR(adapter)) {
2005 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
2006 return PTR_ERR(adapter);
2007 }
2008
2009 for (slice = 0; slice < adapter->slices; slice++) {
2010 if ((rc = pci_init_afu(adapter, slice, dev))) {
2011 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
2012 continue;
2013 }
2014
2015 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
2016 if (rc)
2017 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
2018 }
2019
2020 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2021 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2022
2023 return 0;
2024 }
2025
cxl_remove(struct pci_dev * dev)2026 static void cxl_remove(struct pci_dev *dev)
2027 {
2028 struct cxl *adapter = pci_get_drvdata(dev);
2029 struct cxl_afu *afu;
2030 int i;
2031
2032 /*
2033 * Lock to prevent someone grabbing a ref through the adapter list as
2034 * we are removing it
2035 */
2036 for (i = 0; i < adapter->slices; i++) {
2037 afu = adapter->afu[i];
2038 cxl_pci_remove_afu(afu);
2039 }
2040 cxl_pci_remove_adapter(adapter);
2041 }
2042
cxl_vphb_error_detected(struct cxl_afu * afu,pci_channel_state_t state)2043 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2044 pci_channel_state_t state)
2045 {
2046 struct pci_dev *afu_dev;
2047 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2048 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2049
2050 /* There should only be one entry, but go through the list
2051 * anyway
2052 */
2053 if (afu == NULL || afu->phb == NULL)
2054 return result;
2055
2056 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2057 if (!afu_dev->driver)
2058 continue;
2059
2060 afu_dev->error_state = state;
2061
2062 if (afu_dev->driver->err_handler)
2063 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2064 state);
2065 /* Disconnect trumps all, NONE trumps NEED_RESET */
2066 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2067 result = PCI_ERS_RESULT_DISCONNECT;
2068 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2069 (result == PCI_ERS_RESULT_NEED_RESET))
2070 result = PCI_ERS_RESULT_NONE;
2071 }
2072 return result;
2073 }
2074
cxl_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)2075 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2076 pci_channel_state_t state)
2077 {
2078 struct cxl *adapter = pci_get_drvdata(pdev);
2079 struct cxl_afu *afu;
2080 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2081 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2082 int i;
2083
2084 /* At this point, we could still have an interrupt pending.
2085 * Let's try to get them out of the way before they do
2086 * anything we don't like.
2087 */
2088 schedule();
2089
2090 /* If we're permanently dead, give up. */
2091 if (state == pci_channel_io_perm_failure) {
2092 spin_lock(&adapter->afu_list_lock);
2093 for (i = 0; i < adapter->slices; i++) {
2094 afu = adapter->afu[i];
2095 /*
2096 * Tell the AFU drivers; but we don't care what they
2097 * say, we're going away.
2098 */
2099 cxl_vphb_error_detected(afu, state);
2100 }
2101 spin_unlock(&adapter->afu_list_lock);
2102 return PCI_ERS_RESULT_DISCONNECT;
2103 }
2104
2105 /* Are we reflashing?
2106 *
2107 * If we reflash, we could come back as something entirely
2108 * different, including a non-CAPI card. As such, by default
2109 * we don't participate in the process. We'll be unbound and
2110 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2111 * us!)
2112 *
2113 * However, this isn't the entire story: for reliablity
2114 * reasons, we usually want to reflash the FPGA on PERST in
2115 * order to get back to a more reliable known-good state.
2116 *
2117 * This causes us a bit of a problem: if we reflash we can't
2118 * trust that we'll come back the same - we could have a new
2119 * image and been PERSTed in order to load that
2120 * image. However, most of the time we actually *will* come
2121 * back the same - for example a regular EEH event.
2122 *
2123 * Therefore, we allow the user to assert that the image is
2124 * indeed the same and that we should continue on into EEH
2125 * anyway.
2126 */
2127 if (adapter->perst_loads_image && !adapter->perst_same_image) {
2128 /* TODO take the PHB out of CXL mode */
2129 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2130 return PCI_ERS_RESULT_NONE;
2131 }
2132
2133 /*
2134 * At this point, we want to try to recover. We'll always
2135 * need a complete slot reset: we don't trust any other reset.
2136 *
2137 * Now, we go through each AFU:
2138 * - We send the driver, if bound, an error_detected callback.
2139 * We expect it to clean up, but it can also tell us to give
2140 * up and permanently detach the card. To simplify things, if
2141 * any bound AFU driver doesn't support EEH, we give up on EEH.
2142 *
2143 * - We detach all contexts associated with the AFU. This
2144 * does not free them, but puts them into a CLOSED state
2145 * which causes any the associated files to return useful
2146 * errors to userland. It also unmaps, but does not free,
2147 * any IRQs.
2148 *
2149 * - We clean up our side: releasing and unmapping resources we hold
2150 * so we can wire them up again when the hardware comes back up.
2151 *
2152 * Driver authors should note:
2153 *
2154 * - Any contexts you create in your kernel driver (except
2155 * those associated with anonymous file descriptors) are
2156 * your responsibility to free and recreate. Likewise with
2157 * any attached resources.
2158 *
2159 * - We will take responsibility for re-initialising the
2160 * device context (the one set up for you in
2161 * cxl_pci_enable_device_hook and accessed through
2162 * cxl_get_context). If you've attached IRQs or other
2163 * resources to it, they remains yours to free.
2164 *
2165 * You can call the same functions to release resources as you
2166 * normally would: we make sure that these functions continue
2167 * to work when the hardware is down.
2168 *
2169 * Two examples:
2170 *
2171 * 1) If you normally free all your resources at the end of
2172 * each request, or if you use anonymous FDs, your
2173 * error_detected callback can simply set a flag to tell
2174 * your driver not to start any new calls. You can then
2175 * clear the flag in the resume callback.
2176 *
2177 * 2) If you normally allocate your resources on startup:
2178 * * Set a flag in error_detected as above.
2179 * * Let CXL detach your contexts.
2180 * * In slot_reset, free the old resources and allocate new ones.
2181 * * In resume, clear the flag to allow things to start.
2182 */
2183
2184 /* Make sure no one else changes the afu list */
2185 spin_lock(&adapter->afu_list_lock);
2186
2187 for (i = 0; i < adapter->slices; i++) {
2188 afu = adapter->afu[i];
2189
2190 if (afu == NULL)
2191 continue;
2192
2193 afu_result = cxl_vphb_error_detected(afu, state);
2194 cxl_context_detach_all(afu);
2195 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2196 pci_deconfigure_afu(afu);
2197
2198 /* Disconnect trumps all, NONE trumps NEED_RESET */
2199 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2200 result = PCI_ERS_RESULT_DISCONNECT;
2201 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2202 (result == PCI_ERS_RESULT_NEED_RESET))
2203 result = PCI_ERS_RESULT_NONE;
2204 }
2205 spin_unlock(&adapter->afu_list_lock);
2206
2207 /* should take the context lock here */
2208 if (cxl_adapter_context_lock(adapter) != 0)
2209 dev_warn(&adapter->dev,
2210 "Couldn't take context lock with %d active-contexts\n",
2211 atomic_read(&adapter->contexts_num));
2212
2213 cxl_deconfigure_adapter(adapter);
2214
2215 return result;
2216 }
2217
cxl_pci_slot_reset(struct pci_dev * pdev)2218 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2219 {
2220 struct cxl *adapter = pci_get_drvdata(pdev);
2221 struct cxl_afu *afu;
2222 struct cxl_context *ctx;
2223 struct pci_dev *afu_dev;
2224 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2225 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2226 int i;
2227
2228 if (cxl_configure_adapter(adapter, pdev))
2229 goto err;
2230
2231 /*
2232 * Unlock context activation for the adapter. Ideally this should be
2233 * done in cxl_pci_resume but cxlflash module tries to activate the
2234 * master context as part of slot_reset callback.
2235 */
2236 cxl_adapter_context_unlock(adapter);
2237
2238 spin_lock(&adapter->afu_list_lock);
2239 for (i = 0; i < adapter->slices; i++) {
2240 afu = adapter->afu[i];
2241
2242 if (afu == NULL)
2243 continue;
2244
2245 if (pci_configure_afu(afu, adapter, pdev))
2246 goto err_unlock;
2247
2248 if (cxl_afu_select_best_mode(afu))
2249 goto err_unlock;
2250
2251 if (afu->phb == NULL)
2252 continue;
2253
2254 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2255 /* Reset the device context.
2256 * TODO: make this less disruptive
2257 */
2258 ctx = cxl_get_context(afu_dev);
2259
2260 if (ctx && cxl_release_context(ctx))
2261 goto err_unlock;
2262
2263 ctx = cxl_dev_context_init(afu_dev);
2264 if (IS_ERR(ctx))
2265 goto err_unlock;
2266
2267 afu_dev->dev.archdata.cxl_ctx = ctx;
2268
2269 if (cxl_ops->afu_check_and_enable(afu))
2270 goto err_unlock;
2271
2272 afu_dev->error_state = pci_channel_io_normal;
2273
2274 /* If there's a driver attached, allow it to
2275 * chime in on recovery. Drivers should check
2276 * if everything has come back OK, but
2277 * shouldn't start new work until we call
2278 * their resume function.
2279 */
2280 if (!afu_dev->driver)
2281 continue;
2282
2283 if (afu_dev->driver->err_handler &&
2284 afu_dev->driver->err_handler->slot_reset)
2285 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2286
2287 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2288 result = PCI_ERS_RESULT_DISCONNECT;
2289 }
2290 }
2291
2292 spin_unlock(&adapter->afu_list_lock);
2293 return result;
2294
2295 err_unlock:
2296 spin_unlock(&adapter->afu_list_lock);
2297
2298 err:
2299 /* All the bits that happen in both error_detected and cxl_remove
2300 * should be idempotent, so we don't need to worry about leaving a mix
2301 * of unconfigured and reconfigured resources.
2302 */
2303 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2304 return PCI_ERS_RESULT_DISCONNECT;
2305 }
2306
cxl_pci_resume(struct pci_dev * pdev)2307 static void cxl_pci_resume(struct pci_dev *pdev)
2308 {
2309 struct cxl *adapter = pci_get_drvdata(pdev);
2310 struct cxl_afu *afu;
2311 struct pci_dev *afu_dev;
2312 int i;
2313
2314 /* Everything is back now. Drivers should restart work now.
2315 * This is not the place to be checking if everything came back up
2316 * properly, because there's no return value: do that in slot_reset.
2317 */
2318 spin_lock(&adapter->afu_list_lock);
2319 for (i = 0; i < adapter->slices; i++) {
2320 afu = adapter->afu[i];
2321
2322 if (afu == NULL || afu->phb == NULL)
2323 continue;
2324
2325 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2326 if (afu_dev->driver && afu_dev->driver->err_handler &&
2327 afu_dev->driver->err_handler->resume)
2328 afu_dev->driver->err_handler->resume(afu_dev);
2329 }
2330 }
2331 spin_unlock(&adapter->afu_list_lock);
2332 }
2333
2334 static const struct pci_error_handlers cxl_err_handler = {
2335 .error_detected = cxl_pci_error_detected,
2336 .slot_reset = cxl_pci_slot_reset,
2337 .resume = cxl_pci_resume,
2338 };
2339
2340 struct pci_driver cxl_pci_driver = {
2341 .name = "cxl-pci",
2342 .id_table = cxl_pci_tbl,
2343 .probe = cxl_probe,
2344 .remove = cxl_remove,
2345 .shutdown = cxl_remove,
2346 .err_handler = &cxl_err_handler,
2347 };
2348