1 /*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/include/asm/kvm_host.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef __ARM64_KVM_HOST_H__
23 #define __ARM64_KVM_HOST_H__
24
25 #include <linux/types.h>
26 #include <linux/kvm_types.h>
27 #include <asm/cpufeature.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30 #include <asm/kvm_mmio.h>
31
32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
33
34 #define KVM_USER_MEM_SLOTS 512
35 #define KVM_HALT_POLL_NS_DEFAULT 500000
36
37 #include <kvm/arm_vgic.h>
38 #include <kvm/arm_arch_timer.h>
39 #include <kvm/arm_pmu.h>
40
41 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
42
43 #define KVM_VCPU_MAX_FEATURES 4
44
45 #define KVM_REQ_SLEEP \
46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
48
49 int __attribute_const__ kvm_target_cpu(void);
50 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
51 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
52 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
53
54 struct kvm_arch {
55 /* The VMID generation used for the virt. memory system */
56 u64 vmid_gen;
57 u32 vmid;
58
59 /* 1-level 2nd stage table and lock */
60 spinlock_t pgd_lock;
61 pgd_t *pgd;
62
63 /* VTTBR value associated with above pgd and vmid */
64 u64 vttbr;
65
66 /* The last vcpu id that ran on each physical CPU */
67 int __percpu *last_vcpu_ran;
68
69 /* The maximum number of vCPUs depends on the used GIC model */
70 int max_vcpus;
71
72 /* Interrupt controller */
73 struct vgic_dist vgic;
74
75 /* Mandated version of PSCI */
76 u32 psci_version;
77 };
78
79 #define KVM_NR_MEM_OBJS 40
80
81 /*
82 * We don't want allocation failures within the mmu code, so we preallocate
83 * enough memory for a single page fault in a cache.
84 */
85 struct kvm_mmu_memory_cache {
86 int nobjs;
87 void *objects[KVM_NR_MEM_OBJS];
88 };
89
90 struct kvm_vcpu_fault_info {
91 u32 esr_el2; /* Hyp Syndrom Register */
92 u64 far_el2; /* Hyp Fault Address Register */
93 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
94 };
95
96 /*
97 * 0 is reserved as an invalid value.
98 * Order should be kept in sync with the save/restore code.
99 */
100 enum vcpu_sysreg {
101 __INVALID_SYSREG__,
102 MPIDR_EL1, /* MultiProcessor Affinity Register */
103 CSSELR_EL1, /* Cache Size Selection Register */
104 SCTLR_EL1, /* System Control Register */
105 ACTLR_EL1, /* Auxiliary Control Register */
106 CPACR_EL1, /* Coprocessor Access Control */
107 TTBR0_EL1, /* Translation Table Base Register 0 */
108 TTBR1_EL1, /* Translation Table Base Register 1 */
109 TCR_EL1, /* Translation Control Register */
110 ESR_EL1, /* Exception Syndrome Register */
111 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
112 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
113 FAR_EL1, /* Fault Address Register */
114 MAIR_EL1, /* Memory Attribute Indirection Register */
115 VBAR_EL1, /* Vector Base Address Register */
116 CONTEXTIDR_EL1, /* Context ID Register */
117 TPIDR_EL0, /* Thread ID, User R/W */
118 TPIDRRO_EL0, /* Thread ID, User R/O */
119 TPIDR_EL1, /* Thread ID, Privileged */
120 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
121 CNTKCTL_EL1, /* Timer Control Register (EL1) */
122 PAR_EL1, /* Physical Address Register */
123 MDSCR_EL1, /* Monitor Debug System Control Register */
124 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
125
126 /* Performance Monitors Registers */
127 PMCR_EL0, /* Control Register */
128 PMSELR_EL0, /* Event Counter Selection Register */
129 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
130 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
131 PMCCNTR_EL0, /* Cycle Counter Register */
132 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
133 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
134 PMCCFILTR_EL0, /* Cycle Count Filter Register */
135 PMCNTENSET_EL0, /* Count Enable Set Register */
136 PMINTENSET_EL1, /* Interrupt Enable Set Register */
137 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
138 PMSWINC_EL0, /* Software Increment Register */
139 PMUSERENR_EL0, /* User Enable Register */
140
141 /* 32bit specific registers. Keep them at the end of the range */
142 DACR32_EL2, /* Domain Access Control Register */
143 IFSR32_EL2, /* Instruction Fault Status Register */
144 FPEXC32_EL2, /* Floating-Point Exception Control Register */
145 DBGVCR32_EL2, /* Debug Vector Catch Register */
146
147 NR_SYS_REGS /* Nothing after this line! */
148 };
149
150 /* 32bit mapping */
151 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
152 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
153 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
154 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
155 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
156 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
157 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
158 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
159 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
160 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
161 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
162 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
163 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
164 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
165 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
166 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
167 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
168 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
169 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
170 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
171 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
172 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
173 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
174 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
175 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
176 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
177 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
178 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
179 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
180
181 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
182 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
183 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
184 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
185 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
186 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
187 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
188
189 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
190
191 struct kvm_cpu_context {
192 struct kvm_regs gp_regs;
193 union {
194 u64 sys_regs[NR_SYS_REGS];
195 u32 copro[NR_COPRO_REGS];
196 };
197
198 struct kvm_vcpu *__hyp_running_vcpu;
199 };
200
201 typedef struct kvm_cpu_context kvm_cpu_context_t;
202
203 struct kvm_vcpu_arch {
204 struct kvm_cpu_context ctxt;
205
206 /* HYP configuration */
207 u64 hcr_el2;
208 u32 mdcr_el2;
209
210 /* Exception Information */
211 struct kvm_vcpu_fault_info fault;
212
213 /* State of various workarounds, see kvm_asm.h for bit assignment */
214 u64 workaround_flags;
215
216 /* Guest debug state */
217 u64 debug_flags;
218
219 /*
220 * We maintain more than a single set of debug registers to support
221 * debugging the guest from the host and to maintain separate host and
222 * guest state during world switches. vcpu_debug_state are the debug
223 * registers of the vcpu as the guest sees them. host_debug_state are
224 * the host registers which are saved and restored during
225 * world switches. external_debug_state contains the debug
226 * values we want to debug the guest. This is set via the
227 * KVM_SET_GUEST_DEBUG ioctl.
228 *
229 * debug_ptr points to the set of debug registers that should be loaded
230 * onto the hardware when running the guest.
231 */
232 struct kvm_guest_debug_arch *debug_ptr;
233 struct kvm_guest_debug_arch vcpu_debug_state;
234 struct kvm_guest_debug_arch external_debug_state;
235
236 /* Pointer to host CPU context */
237 kvm_cpu_context_t *host_cpu_context;
238 struct {
239 /* {Break,watch}point registers */
240 struct kvm_guest_debug_arch regs;
241 /* Statistical profiling extension */
242 u64 pmscr_el1;
243 } host_debug_state;
244
245 /* VGIC state */
246 struct vgic_cpu vgic_cpu;
247 struct arch_timer_cpu timer_cpu;
248 struct kvm_pmu pmu;
249
250 /*
251 * Anything that is not used directly from assembly code goes
252 * here.
253 */
254
255 /*
256 * Guest registers we preserve during guest debugging.
257 *
258 * These shadow registers are updated by the kvm_handle_sys_reg
259 * trap handler if the guest accesses or updates them while we
260 * are using guest debug.
261 */
262 struct {
263 u32 mdscr_el1;
264 } guest_debug_preserved;
265
266 /* vcpu power-off state */
267 bool power_off;
268
269 /* Don't run the guest (internal implementation need) */
270 bool pause;
271
272 /* IO related fields */
273 struct kvm_decode mmio_decode;
274
275 /* Interrupt related fields */
276 u64 irq_lines; /* IRQ and FIQ levels */
277
278 /* Cache some mmu pages needed inside spinlock regions */
279 struct kvm_mmu_memory_cache mmu_page_cache;
280
281 /* Target CPU and feature flags */
282 int target;
283 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
284
285 /* Detect first run of a vcpu */
286 bool has_run_once;
287 };
288
289 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
290 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
291 /*
292 * CP14 and CP15 live in the same array, as they are backed by the
293 * same system registers.
294 */
295 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
296 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
297
298 #ifdef CONFIG_CPU_BIG_ENDIAN
299 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
300 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
301 #else
302 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
303 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
304 #endif
305
306 struct kvm_vm_stat {
307 ulong remote_tlb_flush;
308 };
309
310 struct kvm_vcpu_stat {
311 u64 halt_successful_poll;
312 u64 halt_attempted_poll;
313 u64 halt_poll_invalid;
314 u64 halt_wakeup;
315 u64 hvc_exit_stat;
316 u64 wfe_exit_stat;
317 u64 wfi_exit_stat;
318 u64 mmio_exit_user;
319 u64 mmio_exit_kernel;
320 u64 exits;
321 };
322
323 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
324 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
325 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
326 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
327 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
328
329 #define KVM_ARCH_WANT_MMU_NOTIFIER
330 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
331 int kvm_unmap_hva_range(struct kvm *kvm,
332 unsigned long start, unsigned long end);
333 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
334 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
335 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
336
337 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
338 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
339 void kvm_arm_halt_guest(struct kvm *kvm);
340 void kvm_arm_resume_guest(struct kvm *kvm);
341
342 u64 __kvm_call_hyp(void *hypfn, ...);
343 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
344
345 void force_vm_exit(const cpumask_t *mask);
346 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
347
348 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
349 int exception_index);
350
351 int kvm_perf_init(void);
352 int kvm_perf_teardown(void);
353
354 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
355
356 void __kvm_set_tpidr_el2(u64 tpidr_el2);
357 DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
358
359 void __kvm_enable_ssbs(void);
360
__cpu_init_hyp_mode(phys_addr_t pgd_ptr,unsigned long hyp_stack_ptr,unsigned long vector_ptr)361 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
362 unsigned long hyp_stack_ptr,
363 unsigned long vector_ptr)
364 {
365 u64 tpidr_el2;
366
367 /*
368 * Call initialization code, and switch to the full blown HYP code.
369 * If the cpucaps haven't been finalized yet, something has gone very
370 * wrong, and hyp will crash and burn when it uses any
371 * cpus_have_const_cap() wrapper.
372 */
373 BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
374 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
375
376 /*
377 * Calculate the raw per-cpu offset without a translation from the
378 * kernel's mapping to the linear mapping, and store it in tpidr_el2
379 * so that we can use adr_l to access per-cpu variables in EL2.
380 */
381 tpidr_el2 = (u64)this_cpu_ptr(&kvm_host_cpu_state)
382 - (u64)kvm_ksym_ref(kvm_host_cpu_state);
383
384 kvm_call_hyp(__kvm_set_tpidr_el2, tpidr_el2);
385
386 /*
387 * Disabling SSBD on a non-VHE system requires us to enable SSBS
388 * at EL2.
389 */
390 if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
391 arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
392 kvm_call_hyp(__kvm_enable_ssbs);
393 }
394 }
395
kvm_arch_hardware_unsetup(void)396 static inline void kvm_arch_hardware_unsetup(void) {}
kvm_arch_sync_events(struct kvm * kvm)397 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_vcpu_uninit(struct kvm_vcpu * vcpu)398 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)399 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
kvm_arch_vcpu_block_finish(struct kvm_vcpu * vcpu)400 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
401
402 void kvm_arm_init_debug(void);
403 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
404 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
405 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
406 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
407 struct kvm_device_attr *attr);
408 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
409 struct kvm_device_attr *attr);
410 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
411 struct kvm_device_attr *attr);
412
__cpu_init_stage2(void)413 static inline void __cpu_init_stage2(void)
414 {
415 u32 parange = kvm_call_hyp(__init_stage2_translation);
416
417 WARN_ONCE(parange < 40,
418 "PARange is %d bits, unsupported configuration!", parange);
419 }
420
kvm_arm_harden_branch_predictor(void)421 static inline bool kvm_arm_harden_branch_predictor(void)
422 {
423 return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
424 }
425
426 #define KVM_SSBD_UNKNOWN -1
427 #define KVM_SSBD_FORCE_DISABLE 0
428 #define KVM_SSBD_KERNEL 1
429 #define KVM_SSBD_FORCE_ENABLE 2
430 #define KVM_SSBD_MITIGATED 3
431
kvm_arm_have_ssbd(void)432 static inline int kvm_arm_have_ssbd(void)
433 {
434 switch (arm64_get_ssbd_state()) {
435 case ARM64_SSBD_FORCE_DISABLE:
436 return KVM_SSBD_FORCE_DISABLE;
437 case ARM64_SSBD_KERNEL:
438 return KVM_SSBD_KERNEL;
439 case ARM64_SSBD_FORCE_ENABLE:
440 return KVM_SSBD_FORCE_ENABLE;
441 case ARM64_SSBD_MITIGATED:
442 return KVM_SSBD_MITIGATED;
443 case ARM64_SSBD_UNKNOWN:
444 default:
445 return KVM_SSBD_UNKNOWN;
446 }
447 }
448
449 #endif /* __ARM64_KVM_HOST_H__ */
450