1 /*
2 * (c) 2005-2016 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 *
7 * Written by Jacob Shin - AMD, Inc.
8 * Maintained by: Borislav Petkov <bp@alien8.de>
9 *
10 * All MC4_MISCi registers are shared between cores on a node.
11 */
12 #include <linux/interrupt.h>
13 #include <linux/notifier.h>
14 #include <linux/kobject.h>
15 #include <linux/percpu.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/cpu.h>
22 #include <linux/smp.h>
23 #include <linux/string.h>
24
25 #include <asm/amd_nb.h>
26 #include <asm/traps.h>
27 #include <asm/apic.h>
28 #include <asm/mce.h>
29 #include <asm/msr.h>
30 #include <asm/trace/irq_vectors.h>
31
32 #include "mce-internal.h"
33
34 #define NR_BLOCKS 5
35 #define THRESHOLD_MAX 0xFFF
36 #define INT_TYPE_APIC 0x00020000
37 #define MASK_VALID_HI 0x80000000
38 #define MASK_CNTP_HI 0x40000000
39 #define MASK_LOCKED_HI 0x20000000
40 #define MASK_LVTOFF_HI 0x00F00000
41 #define MASK_COUNT_EN_HI 0x00080000
42 #define MASK_INT_TYPE_HI 0x00060000
43 #define MASK_OVERFLOW_HI 0x00010000
44 #define MASK_ERR_COUNT_HI 0x00000FFF
45 #define MASK_BLKPTR_LO 0xFF000000
46 #define MCG_XBLK_ADDR 0xC0000400
47
48 /* Deferred error settings */
49 #define MSR_CU_DEF_ERR 0xC0000410
50 #define MASK_DEF_LVTOFF 0x000000F0
51 #define MASK_DEF_INT_TYPE 0x00000006
52 #define DEF_LVT_OFF 0x2
53 #define DEF_INT_TYPE_APIC 0x2
54
55 /* Scalable MCA: */
56
57 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
58 #define SMCA_THR_LVT_OFF 0xF000
59
60 static bool thresholding_irq_en;
61
62 static const char * const th_names[] = {
63 "load_store",
64 "insn_fetch",
65 "combined_unit",
66 "decode_unit",
67 "northbridge",
68 "execution_unit",
69 };
70
71 static const char * const smca_umc_block_names[] = {
72 "dram_ecc",
73 "misc_umc"
74 };
75
76 struct smca_bank_name {
77 const char *name; /* Short name for sysfs */
78 const char *long_name; /* Long name for pretty-printing */
79 };
80
81 static struct smca_bank_name smca_names[] = {
82 [SMCA_LS] = { "load_store", "Load Store Unit" },
83 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" },
84 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" },
85 [SMCA_DE] = { "decode_unit", "Decode Unit" },
86 [SMCA_RESERVED] = { "reserved", "Reserved" },
87 [SMCA_EX] = { "execution_unit", "Execution Unit" },
88 [SMCA_FP] = { "floating_point", "Floating Point Unit" },
89 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" },
90 [SMCA_CS] = { "coherent_slave", "Coherent Slave" },
91 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." },
92 [SMCA_UMC] = { "umc", "Unified Memory Controller" },
93 [SMCA_PB] = { "param_block", "Parameter Block" },
94 [SMCA_PSP] = { "psp", "Platform Security Processor" },
95 [SMCA_SMU] = { "smu", "System Management Unit" },
96 };
97
98 static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init =
99 {
100 [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 }
101 };
102
smca_get_name(enum smca_bank_types t)103 static const char *smca_get_name(enum smca_bank_types t)
104 {
105 if (t >= N_SMCA_BANK_TYPES)
106 return NULL;
107
108 return smca_names[t].name;
109 }
110
smca_get_long_name(enum smca_bank_types t)111 const char *smca_get_long_name(enum smca_bank_types t)
112 {
113 if (t >= N_SMCA_BANK_TYPES)
114 return NULL;
115
116 return smca_names[t].long_name;
117 }
118 EXPORT_SYMBOL_GPL(smca_get_long_name);
119
smca_get_bank_type(unsigned int bank)120 static enum smca_bank_types smca_get_bank_type(unsigned int bank)
121 {
122 struct smca_bank *b;
123
124 if (bank >= MAX_NR_BANKS)
125 return N_SMCA_BANK_TYPES;
126
127 b = &smca_banks[bank];
128 if (!b->hwid)
129 return N_SMCA_BANK_TYPES;
130
131 return b->hwid->bank_type;
132 }
133
134 static struct smca_hwid smca_hwid_mcatypes[] = {
135 /* { bank_type, hwid_mcatype, xec_bitmap } */
136
137 /* Reserved type */
138 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
139
140 /* ZN Core (HWID=0xB0) MCA types */
141 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
142 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
143 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
144 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF },
145 /* HWID 0xB0 MCATYPE 0x4 is Reserved */
146 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF },
147 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F },
148 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
149
150 /* Data Fabric MCA types */
151 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF },
152 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF },
153
154 /* Unified Memory Controller MCA type */
155 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F },
156
157 /* Parameter Block MCA type */
158 { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 },
159
160 /* Platform Security Processor MCA type */
161 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 },
162
163 /* System Management Unit MCA type */
164 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 },
165 };
166
167 struct smca_bank smca_banks[MAX_NR_BANKS];
168 EXPORT_SYMBOL_GPL(smca_banks);
169
170 /*
171 * In SMCA enabled processors, we can have multiple banks for a given IP type.
172 * So to define a unique name for each bank, we use a temp c-string to append
173 * the MCA_IPID[InstanceId] to type's name in get_name().
174 *
175 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
176 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
177 */
178 #define MAX_MCATYPE_NAME_LEN 30
179 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
180
181 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
182 static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */
183
184 static void amd_threshold_interrupt(void);
185 static void amd_deferred_error_interrupt(void);
186
default_deferred_error_interrupt(void)187 static void default_deferred_error_interrupt(void)
188 {
189 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
190 }
191 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
192
smca_configure(unsigned int bank,unsigned int cpu)193 static void smca_configure(unsigned int bank, unsigned int cpu)
194 {
195 unsigned int i, hwid_mcatype;
196 struct smca_hwid *s_hwid;
197 u32 high, low;
198 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
199
200 /* Set appropriate bits in MCA_CONFIG */
201 if (!rdmsr_safe(smca_config, &low, &high)) {
202 /*
203 * OS is required to set the MCAX bit to acknowledge that it is
204 * now using the new MSR ranges and new registers under each
205 * bank. It also means that the OS will configure deferred
206 * errors in the new MCx_CONFIG register. If the bit is not set,
207 * uncorrectable errors will cause a system panic.
208 *
209 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
210 */
211 high |= BIT(0);
212
213 /*
214 * SMCA sets the Deferred Error Interrupt type per bank.
215 *
216 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
217 * if the DeferredIntType bit field is available.
218 *
219 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
220 * high portion of the MSR). OS should set this to 0x1 to enable
221 * APIC based interrupt. First, check that no interrupt has been
222 * set.
223 */
224 if ((low & BIT(5)) && !((high >> 5) & 0x3))
225 high |= BIT(5);
226
227 wrmsr(smca_config, low, high);
228 }
229
230 /* Return early if this bank was already initialized. */
231 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0)
232 return;
233
234 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
235 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
236 return;
237 }
238
239 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
240 (high & MCI_IPID_MCATYPE) >> 16);
241
242 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
243 s_hwid = &smca_hwid_mcatypes[i];
244 if (hwid_mcatype == s_hwid->hwid_mcatype) {
245 smca_banks[bank].hwid = s_hwid;
246 smca_banks[bank].id = low;
247 smca_banks[bank].sysfs_id = s_hwid->count++;
248 break;
249 }
250 }
251 }
252
253 struct thresh_restart {
254 struct threshold_block *b;
255 int reset;
256 int set_lvt_off;
257 int lvt_off;
258 u16 old_limit;
259 };
260
is_shared_bank(int bank)261 static inline bool is_shared_bank(int bank)
262 {
263 /*
264 * Scalable MCA provides for only one core to have access to the MSRs of
265 * a shared bank.
266 */
267 if (mce_flags.smca)
268 return false;
269
270 /* Bank 4 is for northbridge reporting and is thus shared */
271 return (bank == 4);
272 }
273
bank4_names(const struct threshold_block * b)274 static const char *bank4_names(const struct threshold_block *b)
275 {
276 switch (b->address) {
277 /* MSR4_MISC0 */
278 case 0x00000413:
279 return "dram";
280
281 case 0xc0000408:
282 return "ht_links";
283
284 case 0xc0000409:
285 return "l3_cache";
286
287 default:
288 WARN(1, "Funny MSR: 0x%08x\n", b->address);
289 return "";
290 }
291 };
292
293
lvt_interrupt_supported(unsigned int bank,u32 msr_high_bits)294 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
295 {
296 /*
297 * bank 4 supports APIC LVT interrupts implicitly since forever.
298 */
299 if (bank == 4)
300 return true;
301
302 /*
303 * IntP: interrupt present; if this bit is set, the thresholding
304 * bank can generate APIC LVT interrupts
305 */
306 return msr_high_bits & BIT(28);
307 }
308
lvt_off_valid(struct threshold_block * b,int apic,u32 lo,u32 hi)309 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
310 {
311 int msr = (hi & MASK_LVTOFF_HI) >> 20;
312
313 if (apic < 0) {
314 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
315 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
316 b->bank, b->block, b->address, hi, lo);
317 return 0;
318 }
319
320 if (apic != msr) {
321 /*
322 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
323 * the BIOS provides the value. The original field where LVT offset
324 * was set is reserved. Return early here:
325 */
326 if (mce_flags.smca)
327 return 0;
328
329 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
330 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
331 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
332 return 0;
333 }
334
335 return 1;
336 };
337
338 /* Reprogram MCx_MISC MSR behind this threshold bank. */
threshold_restart_bank(void * _tr)339 static void threshold_restart_bank(void *_tr)
340 {
341 struct thresh_restart *tr = _tr;
342 u32 hi, lo;
343
344 rdmsr(tr->b->address, lo, hi);
345
346 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
347 tr->reset = 1; /* limit cannot be lower than err count */
348
349 if (tr->reset) { /* reset err count and overflow bit */
350 hi =
351 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
352 (THRESHOLD_MAX - tr->b->threshold_limit);
353 } else if (tr->old_limit) { /* change limit w/o reset */
354 int new_count = (hi & THRESHOLD_MAX) +
355 (tr->old_limit - tr->b->threshold_limit);
356
357 hi = (hi & ~MASK_ERR_COUNT_HI) |
358 (new_count & THRESHOLD_MAX);
359 }
360
361 /* clear IntType */
362 hi &= ~MASK_INT_TYPE_HI;
363
364 if (!tr->b->interrupt_capable)
365 goto done;
366
367 if (tr->set_lvt_off) {
368 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
369 /* set new lvt offset */
370 hi &= ~MASK_LVTOFF_HI;
371 hi |= tr->lvt_off << 20;
372 }
373 }
374
375 if (tr->b->interrupt_enable)
376 hi |= INT_TYPE_APIC;
377
378 done:
379
380 hi |= MASK_COUNT_EN_HI;
381 wrmsr(tr->b->address, lo, hi);
382 }
383
mce_threshold_block_init(struct threshold_block * b,int offset)384 static void mce_threshold_block_init(struct threshold_block *b, int offset)
385 {
386 struct thresh_restart tr = {
387 .b = b,
388 .set_lvt_off = 1,
389 .lvt_off = offset,
390 };
391
392 b->threshold_limit = THRESHOLD_MAX;
393 threshold_restart_bank(&tr);
394 };
395
setup_APIC_mce_threshold(int reserved,int new)396 static int setup_APIC_mce_threshold(int reserved, int new)
397 {
398 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
399 APIC_EILVT_MSG_FIX, 0))
400 return new;
401
402 return reserved;
403 }
404
setup_APIC_deferred_error(int reserved,int new)405 static int setup_APIC_deferred_error(int reserved, int new)
406 {
407 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
408 APIC_EILVT_MSG_FIX, 0))
409 return new;
410
411 return reserved;
412 }
413
deferred_error_interrupt_enable(struct cpuinfo_x86 * c)414 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
415 {
416 u32 low = 0, high = 0;
417 int def_offset = -1, def_new;
418
419 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
420 return;
421
422 def_new = (low & MASK_DEF_LVTOFF) >> 4;
423 if (!(low & MASK_DEF_LVTOFF)) {
424 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
425 def_new = DEF_LVT_OFF;
426 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
427 }
428
429 def_offset = setup_APIC_deferred_error(def_offset, def_new);
430 if ((def_offset == def_new) &&
431 (deferred_error_int_vector != amd_deferred_error_interrupt))
432 deferred_error_int_vector = amd_deferred_error_interrupt;
433
434 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
435 wrmsr(MSR_CU_DEF_ERR, low, high);
436 }
437
smca_get_block_address(unsigned int cpu,unsigned int bank,unsigned int block)438 static u32 smca_get_block_address(unsigned int cpu, unsigned int bank,
439 unsigned int block)
440 {
441 u32 low, high;
442 u32 addr = 0;
443
444 if (smca_get_bank_type(bank) == SMCA_RESERVED)
445 return addr;
446
447 if (!block)
448 return MSR_AMD64_SMCA_MCx_MISC(bank);
449
450 /* Check our cache first: */
451 if (smca_bank_addrs[bank][block] != -1)
452 return smca_bank_addrs[bank][block];
453
454 /*
455 * For SMCA enabled processors, BLKPTR field of the first MISC register
456 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
457 */
458 if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
459 goto out;
460
461 if (!(low & MCI_CONFIG_MCAX))
462 goto out;
463
464 if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
465 (low & MASK_BLKPTR_LO))
466 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
467
468 out:
469 smca_bank_addrs[bank][block] = addr;
470 return addr;
471 }
472
get_block_address(unsigned int cpu,u32 current_addr,u32 low,u32 high,unsigned int bank,unsigned int block)473 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
474 unsigned int bank, unsigned int block)
475 {
476 u32 addr = 0, offset = 0;
477
478 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
479 return addr;
480
481 if (mce_flags.smca)
482 return smca_get_block_address(cpu, bank, block);
483
484 /* Fall back to method we used for older processors: */
485 switch (block) {
486 case 0:
487 addr = msr_ops.misc(bank);
488 break;
489 case 1:
490 offset = ((low & MASK_BLKPTR_LO) >> 21);
491 if (offset)
492 addr = MCG_XBLK_ADDR + offset;
493 break;
494 default:
495 addr = ++current_addr;
496 }
497 return addr;
498 }
499
500 static int
prepare_threshold_block(unsigned int bank,unsigned int block,u32 addr,int offset,u32 misc_high)501 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
502 int offset, u32 misc_high)
503 {
504 unsigned int cpu = smp_processor_id();
505 u32 smca_low, smca_high;
506 struct threshold_block b;
507 int new;
508
509 if (!block)
510 per_cpu(bank_map, cpu) |= (1 << bank);
511
512 memset(&b, 0, sizeof(b));
513 b.cpu = cpu;
514 b.bank = bank;
515 b.block = block;
516 b.address = addr;
517 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);
518
519 if (!b.interrupt_capable)
520 goto done;
521
522 b.interrupt_enable = 1;
523
524 if (!mce_flags.smca) {
525 new = (misc_high & MASK_LVTOFF_HI) >> 20;
526 goto set_offset;
527 }
528
529 /* Gather LVT offset for thresholding: */
530 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
531 goto out;
532
533 new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
534
535 set_offset:
536 offset = setup_APIC_mce_threshold(offset, new);
537 if (offset == new)
538 thresholding_irq_en = true;
539
540 done:
541 mce_threshold_block_init(&b, offset);
542
543 out:
544 return offset;
545 }
546
547 /*
548 * Turn off MC4_MISC thresholding banks on all family 0x15 models since
549 * they're not supported there.
550 */
disable_err_thresholding(struct cpuinfo_x86 * c)551 void disable_err_thresholding(struct cpuinfo_x86 *c)
552 {
553 int i;
554 u64 hwcr;
555 bool need_toggle;
556 u32 msrs[] = {
557 0x00000413, /* MC4_MISC0 */
558 0xc0000408, /* MC4_MISC1 */
559 };
560
561 if (c->x86 != 0x15)
562 return;
563
564 rdmsrl(MSR_K7_HWCR, hwcr);
565
566 /* McStatusWrEn has to be set */
567 need_toggle = !(hwcr & BIT(18));
568
569 if (need_toggle)
570 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
571
572 /* Clear CntP bit safely */
573 for (i = 0; i < ARRAY_SIZE(msrs); i++)
574 msr_clear_bit(msrs[i], 62);
575
576 /* restore old settings */
577 if (need_toggle)
578 wrmsrl(MSR_K7_HWCR, hwcr);
579 }
580
581 /* cpu init entry point, called from mce.c with preempt off */
mce_amd_feature_init(struct cpuinfo_x86 * c)582 void mce_amd_feature_init(struct cpuinfo_x86 *c)
583 {
584 u32 low = 0, high = 0, address = 0;
585 unsigned int bank, block, cpu = smp_processor_id();
586 int offset = -1;
587
588 disable_err_thresholding(c);
589
590 for (bank = 0; bank < mca_cfg.banks; ++bank) {
591 if (mce_flags.smca)
592 smca_configure(bank, cpu);
593
594 for (block = 0; block < NR_BLOCKS; ++block) {
595 address = get_block_address(cpu, address, low, high, bank, block);
596 if (!address)
597 break;
598
599 if (rdmsr_safe(address, &low, &high))
600 break;
601
602 if (!(high & MASK_VALID_HI))
603 continue;
604
605 if (!(high & MASK_CNTP_HI) ||
606 (high & MASK_LOCKED_HI))
607 continue;
608
609 offset = prepare_threshold_block(bank, block, address, offset, high);
610 }
611 }
612
613 if (mce_flags.succor)
614 deferred_error_interrupt_enable(c);
615 }
616
umc_normaddr_to_sysaddr(u64 norm_addr,u16 nid,u8 umc,u64 * sys_addr)617 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
618 {
619 u64 dram_base_addr, dram_limit_addr, dram_hole_base;
620 /* We start from the normalized address */
621 u64 ret_addr = norm_addr;
622
623 u32 tmp;
624
625 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
626 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
627 u8 intlv_addr_sel, intlv_addr_bit;
628 u8 num_intlv_bits, hashed_bit;
629 u8 lgcy_mmio_hole_en, base = 0;
630 u8 cs_mask, cs_id = 0;
631 bool hash_enabled = false;
632
633 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
634 if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
635 goto out_err;
636
637 /* Remove HiAddrOffset from normalized address, if enabled: */
638 if (tmp & BIT(0)) {
639 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
640
641 if (norm_addr >= hi_addr_offset) {
642 ret_addr -= hi_addr_offset;
643 base = 1;
644 }
645 }
646
647 /* Read D18F0x110 (DramBaseAddress). */
648 if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
649 goto out_err;
650
651 /* Check if address range is valid. */
652 if (!(tmp & BIT(0))) {
653 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
654 __func__, tmp);
655 goto out_err;
656 }
657
658 lgcy_mmio_hole_en = tmp & BIT(1);
659 intlv_num_chan = (tmp >> 4) & 0xF;
660 intlv_addr_sel = (tmp >> 8) & 0x7;
661 dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16;
662
663 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
664 if (intlv_addr_sel > 3) {
665 pr_err("%s: Invalid interleave address select %d.\n",
666 __func__, intlv_addr_sel);
667 goto out_err;
668 }
669
670 /* Read D18F0x114 (DramLimitAddress). */
671 if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
672 goto out_err;
673
674 intlv_num_sockets = (tmp >> 8) & 0x1;
675 intlv_num_dies = (tmp >> 10) & 0x3;
676 dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
677
678 intlv_addr_bit = intlv_addr_sel + 8;
679
680 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
681 switch (intlv_num_chan) {
682 case 0: intlv_num_chan = 0; break;
683 case 1: intlv_num_chan = 1; break;
684 case 3: intlv_num_chan = 2; break;
685 case 5: intlv_num_chan = 3; break;
686 case 7: intlv_num_chan = 4; break;
687
688 case 8: intlv_num_chan = 1;
689 hash_enabled = true;
690 break;
691 default:
692 pr_err("%s: Invalid number of interleaved channels %d.\n",
693 __func__, intlv_num_chan);
694 goto out_err;
695 }
696
697 num_intlv_bits = intlv_num_chan;
698
699 if (intlv_num_dies > 2) {
700 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
701 __func__, intlv_num_dies);
702 goto out_err;
703 }
704
705 num_intlv_bits += intlv_num_dies;
706
707 /* Add a bit if sockets are interleaved. */
708 num_intlv_bits += intlv_num_sockets;
709
710 /* Assert num_intlv_bits <= 4 */
711 if (num_intlv_bits > 4) {
712 pr_err("%s: Invalid interleave bits %d.\n",
713 __func__, num_intlv_bits);
714 goto out_err;
715 }
716
717 if (num_intlv_bits > 0) {
718 u64 temp_addr_x, temp_addr_i, temp_addr_y;
719 u8 die_id_bit, sock_id_bit, cs_fabric_id;
720
721 /*
722 * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
723 * This is the fabric id for this coherent slave. Use
724 * umc/channel# as instance id of the coherent slave
725 * for FICAA.
726 */
727 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
728 goto out_err;
729
730 cs_fabric_id = (tmp >> 8) & 0xFF;
731 die_id_bit = 0;
732
733 /* If interleaved over more than 1 channel: */
734 if (intlv_num_chan) {
735 die_id_bit = intlv_num_chan;
736 cs_mask = (1 << die_id_bit) - 1;
737 cs_id = cs_fabric_id & cs_mask;
738 }
739
740 sock_id_bit = die_id_bit;
741
742 /* Read D18F1x208 (SystemFabricIdMask). */
743 if (intlv_num_dies || intlv_num_sockets)
744 if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
745 goto out_err;
746
747 /* If interleaved over more than 1 die. */
748 if (intlv_num_dies) {
749 sock_id_bit = die_id_bit + intlv_num_dies;
750 die_id_shift = (tmp >> 24) & 0xF;
751 die_id_mask = (tmp >> 8) & 0xFF;
752
753 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
754 }
755
756 /* If interleaved over more than 1 socket. */
757 if (intlv_num_sockets) {
758 socket_id_shift = (tmp >> 28) & 0xF;
759 socket_id_mask = (tmp >> 16) & 0xFF;
760
761 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
762 }
763
764 /*
765 * The pre-interleaved address consists of XXXXXXIIIYYYYY
766 * where III is the ID for this CS, and XXXXXXYYYYY are the
767 * address bits from the post-interleaved address.
768 * "num_intlv_bits" has been calculated to tell us how many "I"
769 * bits there are. "intlv_addr_bit" tells us how many "Y" bits
770 * there are (where "I" starts).
771 */
772 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
773 temp_addr_i = (cs_id << intlv_addr_bit);
774 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
775 ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
776 }
777
778 /* Add dram base address */
779 ret_addr += dram_base_addr;
780
781 /* If legacy MMIO hole enabled */
782 if (lgcy_mmio_hole_en) {
783 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
784 goto out_err;
785
786 dram_hole_base = tmp & GENMASK(31, 24);
787 if (ret_addr >= dram_hole_base)
788 ret_addr += (BIT_ULL(32) - dram_hole_base);
789 }
790
791 if (hash_enabled) {
792 /* Save some parentheses and grab ls-bit at the end. */
793 hashed_bit = (ret_addr >> 12) ^
794 (ret_addr >> 18) ^
795 (ret_addr >> 21) ^
796 (ret_addr >> 30) ^
797 cs_id;
798
799 hashed_bit &= BIT(0);
800
801 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
802 ret_addr ^= BIT(intlv_addr_bit);
803 }
804
805 /* Is calculated system address is above DRAM limit address? */
806 if (ret_addr > dram_limit_addr)
807 goto out_err;
808
809 *sys_addr = ret_addr;
810 return 0;
811
812 out_err:
813 return -EINVAL;
814 }
815 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
816
amd_mce_is_memory_error(struct mce * m)817 bool amd_mce_is_memory_error(struct mce *m)
818 {
819 /* ErrCodeExt[20:16] */
820 u8 xec = (m->status >> 16) & 0x1f;
821
822 if (mce_flags.smca)
823 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;
824
825 return m->bank == 4 && xec == 0x8;
826 }
827
__log_error(unsigned int bank,u64 status,u64 addr,u64 misc)828 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
829 {
830 struct mce m;
831
832 mce_setup(&m);
833
834 m.status = status;
835 m.misc = misc;
836 m.bank = bank;
837 m.tsc = rdtsc();
838
839 if (m.status & MCI_STATUS_ADDRV) {
840 m.addr = addr;
841
842 /*
843 * Extract [55:<lsb>] where lsb is the least significant
844 * *valid* bit of the address bits.
845 */
846 if (mce_flags.smca) {
847 u8 lsb = (m.addr >> 56) & 0x3f;
848
849 m.addr &= GENMASK_ULL(55, lsb);
850 }
851 }
852
853 if (mce_flags.smca) {
854 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
855
856 if (m.status & MCI_STATUS_SYNDV)
857 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
858 }
859
860 mce_log(&m);
861 }
862
smp_deferred_error_interrupt(struct pt_regs * regs)863 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs)
864 {
865 entering_irq();
866 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
867 inc_irq_stat(irq_deferred_error_count);
868 deferred_error_int_vector();
869 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
870 exiting_ack_irq();
871 }
872
873 /*
874 * Returns true if the logged error is deferred. False, otherwise.
875 */
876 static inline bool
_log_error_bank(unsigned int bank,u32 msr_stat,u32 msr_addr,u64 misc)877 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
878 {
879 u64 status, addr = 0;
880
881 rdmsrl(msr_stat, status);
882 if (!(status & MCI_STATUS_VAL))
883 return false;
884
885 if (status & MCI_STATUS_ADDRV)
886 rdmsrl(msr_addr, addr);
887
888 __log_error(bank, status, addr, misc);
889
890 wrmsrl(msr_stat, 0);
891
892 return status & MCI_STATUS_DEFERRED;
893 }
894
895 /*
896 * We have three scenarios for checking for Deferred errors:
897 *
898 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
899 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
900 * clear MCA_DESTAT.
901 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
902 * log it.
903 */
log_error_deferred(unsigned int bank)904 static void log_error_deferred(unsigned int bank)
905 {
906 bool defrd;
907
908 defrd = _log_error_bank(bank, msr_ops.status(bank),
909 msr_ops.addr(bank), 0);
910
911 if (!mce_flags.smca)
912 return;
913
914 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
915 if (defrd) {
916 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
917 return;
918 }
919
920 /*
921 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
922 * for a valid error.
923 */
924 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
925 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
926 }
927
928 /* APIC interrupt handler for deferred errors */
amd_deferred_error_interrupt(void)929 static void amd_deferred_error_interrupt(void)
930 {
931 unsigned int bank;
932
933 for (bank = 0; bank < mca_cfg.banks; ++bank)
934 log_error_deferred(bank);
935 }
936
log_error_thresholding(unsigned int bank,u64 misc)937 static void log_error_thresholding(unsigned int bank, u64 misc)
938 {
939 _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
940 }
941
log_and_reset_block(struct threshold_block * block)942 static void log_and_reset_block(struct threshold_block *block)
943 {
944 struct thresh_restart tr;
945 u32 low = 0, high = 0;
946
947 if (!block)
948 return;
949
950 if (rdmsr_safe(block->address, &low, &high))
951 return;
952
953 if (!(high & MASK_OVERFLOW_HI))
954 return;
955
956 /* Log the MCE which caused the threshold event. */
957 log_error_thresholding(block->bank, ((u64)high << 32) | low);
958
959 /* Reset threshold block after logging error. */
960 memset(&tr, 0, sizeof(tr));
961 tr.b = block;
962 threshold_restart_bank(&tr);
963 }
964
965 /*
966 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
967 * goes off when error_count reaches threshold_limit.
968 */
amd_threshold_interrupt(void)969 static void amd_threshold_interrupt(void)
970 {
971 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
972 unsigned int bank, cpu = smp_processor_id();
973
974 for (bank = 0; bank < mca_cfg.banks; ++bank) {
975 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
976 continue;
977
978 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
979 if (!first_block)
980 continue;
981
982 /*
983 * The first block is also the head of the list. Check it first
984 * before iterating over the rest.
985 */
986 log_and_reset_block(first_block);
987 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
988 log_and_reset_block(block);
989 }
990 }
991
992 /*
993 * Sysfs Interface
994 */
995
996 struct threshold_attr {
997 struct attribute attr;
998 ssize_t (*show) (struct threshold_block *, char *);
999 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
1000 };
1001
1002 #define SHOW_FIELDS(name) \
1003 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
1004 { \
1005 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
1006 }
1007 SHOW_FIELDS(interrupt_enable)
SHOW_FIELDS(threshold_limit)1008 SHOW_FIELDS(threshold_limit)
1009
1010 static ssize_t
1011 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
1012 {
1013 struct thresh_restart tr;
1014 unsigned long new;
1015
1016 if (!b->interrupt_capable)
1017 return -EINVAL;
1018
1019 if (kstrtoul(buf, 0, &new) < 0)
1020 return -EINVAL;
1021
1022 b->interrupt_enable = !!new;
1023
1024 memset(&tr, 0, sizeof(tr));
1025 tr.b = b;
1026
1027 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1028
1029 return size;
1030 }
1031
1032 static ssize_t
store_threshold_limit(struct threshold_block * b,const char * buf,size_t size)1033 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
1034 {
1035 struct thresh_restart tr;
1036 unsigned long new;
1037
1038 if (kstrtoul(buf, 0, &new) < 0)
1039 return -EINVAL;
1040
1041 if (new > THRESHOLD_MAX)
1042 new = THRESHOLD_MAX;
1043 if (new < 1)
1044 new = 1;
1045
1046 memset(&tr, 0, sizeof(tr));
1047 tr.old_limit = b->threshold_limit;
1048 b->threshold_limit = new;
1049 tr.b = b;
1050
1051 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1052
1053 return size;
1054 }
1055
show_error_count(struct threshold_block * b,char * buf)1056 static ssize_t show_error_count(struct threshold_block *b, char *buf)
1057 {
1058 u32 lo, hi;
1059
1060 rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
1061
1062 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
1063 (THRESHOLD_MAX - b->threshold_limit)));
1064 }
1065
1066 static struct threshold_attr error_count = {
1067 .attr = {.name = __stringify(error_count), .mode = 0444 },
1068 .show = show_error_count,
1069 };
1070
1071 #define RW_ATTR(val) \
1072 static struct threshold_attr val = { \
1073 .attr = {.name = __stringify(val), .mode = 0644 }, \
1074 .show = show_## val, \
1075 .store = store_## val, \
1076 };
1077
1078 RW_ATTR(interrupt_enable);
1079 RW_ATTR(threshold_limit);
1080
1081 static struct attribute *default_attrs[] = {
1082 &threshold_limit.attr,
1083 &error_count.attr,
1084 NULL, /* possibly interrupt_enable if supported, see below */
1085 NULL,
1086 };
1087
1088 #define to_block(k) container_of(k, struct threshold_block, kobj)
1089 #define to_attr(a) container_of(a, struct threshold_attr, attr)
1090
show(struct kobject * kobj,struct attribute * attr,char * buf)1091 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1092 {
1093 struct threshold_block *b = to_block(kobj);
1094 struct threshold_attr *a = to_attr(attr);
1095 ssize_t ret;
1096
1097 ret = a->show ? a->show(b, buf) : -EIO;
1098
1099 return ret;
1100 }
1101
store(struct kobject * kobj,struct attribute * attr,const char * buf,size_t count)1102 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1103 const char *buf, size_t count)
1104 {
1105 struct threshold_block *b = to_block(kobj);
1106 struct threshold_attr *a = to_attr(attr);
1107 ssize_t ret;
1108
1109 ret = a->store ? a->store(b, buf, count) : -EIO;
1110
1111 return ret;
1112 }
1113
1114 static const struct sysfs_ops threshold_ops = {
1115 .show = show,
1116 .store = store,
1117 };
1118
1119 static void threshold_block_release(struct kobject *kobj);
1120
1121 static struct kobj_type threshold_ktype = {
1122 .sysfs_ops = &threshold_ops,
1123 .default_attrs = default_attrs,
1124 .release = threshold_block_release,
1125 };
1126
get_name(unsigned int bank,struct threshold_block * b)1127 static const char *get_name(unsigned int bank, struct threshold_block *b)
1128 {
1129 enum smca_bank_types bank_type;
1130
1131 if (!mce_flags.smca) {
1132 if (b && bank == 4)
1133 return bank4_names(b);
1134
1135 return th_names[bank];
1136 }
1137
1138 bank_type = smca_get_bank_type(bank);
1139 if (bank_type >= N_SMCA_BANK_TYPES)
1140 return NULL;
1141
1142 if (b && bank_type == SMCA_UMC) {
1143 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1144 return smca_umc_block_names[b->block];
1145 return NULL;
1146 }
1147
1148 if (smca_banks[bank].hwid->count == 1)
1149 return smca_get_name(bank_type);
1150
1151 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1152 "%s_%x", smca_get_name(bank_type),
1153 smca_banks[bank].sysfs_id);
1154 return buf_mcatype;
1155 }
1156
allocate_threshold_blocks(unsigned int cpu,struct threshold_bank * tb,unsigned int bank,unsigned int block,u32 address)1157 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1158 unsigned int bank, unsigned int block,
1159 u32 address)
1160 {
1161 struct threshold_block *b = NULL;
1162 u32 low, high;
1163 int err;
1164
1165 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1166 return 0;
1167
1168 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1169 return 0;
1170
1171 if (!(high & MASK_VALID_HI)) {
1172 if (block)
1173 goto recurse;
1174 else
1175 return 0;
1176 }
1177
1178 if (!(high & MASK_CNTP_HI) ||
1179 (high & MASK_LOCKED_HI))
1180 goto recurse;
1181
1182 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1183 if (!b)
1184 return -ENOMEM;
1185
1186 b->block = block;
1187 b->bank = bank;
1188 b->cpu = cpu;
1189 b->address = address;
1190 b->interrupt_enable = 0;
1191 b->interrupt_capable = lvt_interrupt_supported(bank, high);
1192 b->threshold_limit = THRESHOLD_MAX;
1193
1194 if (b->interrupt_capable) {
1195 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1196 b->interrupt_enable = 1;
1197 } else {
1198 threshold_ktype.default_attrs[2] = NULL;
1199 }
1200
1201 INIT_LIST_HEAD(&b->miscj);
1202
1203 if (tb->blocks)
1204 list_add(&b->miscj, &tb->blocks->miscj);
1205 else
1206 tb->blocks = b;
1207
1208 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b));
1209 if (err)
1210 goto out_free;
1211 recurse:
1212 address = get_block_address(cpu, address, low, high, bank, ++block);
1213 if (!address)
1214 return 0;
1215
1216 err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1217 if (err)
1218 goto out_free;
1219
1220 if (b)
1221 kobject_uevent(&b->kobj, KOBJ_ADD);
1222
1223 return err;
1224
1225 out_free:
1226 if (b) {
1227 kobject_put(&b->kobj);
1228 list_del(&b->miscj);
1229 kfree(b);
1230 }
1231 return err;
1232 }
1233
__threshold_add_blocks(struct threshold_bank * b)1234 static int __threshold_add_blocks(struct threshold_bank *b)
1235 {
1236 struct list_head *head = &b->blocks->miscj;
1237 struct threshold_block *pos = NULL;
1238 struct threshold_block *tmp = NULL;
1239 int err = 0;
1240
1241 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1242 if (err)
1243 return err;
1244
1245 list_for_each_entry_safe(pos, tmp, head, miscj) {
1246
1247 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1248 if (err) {
1249 list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1250 kobject_del(&pos->kobj);
1251
1252 return err;
1253 }
1254 }
1255 return err;
1256 }
1257
threshold_create_bank(unsigned int cpu,unsigned int bank)1258 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1259 {
1260 struct device *dev = per_cpu(mce_device, cpu);
1261 struct amd_northbridge *nb = NULL;
1262 struct threshold_bank *b = NULL;
1263 const char *name = get_name(bank, NULL);
1264 int err = 0;
1265
1266 if (!dev)
1267 return -ENODEV;
1268
1269 if (is_shared_bank(bank)) {
1270 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1271
1272 /* threshold descriptor already initialized on this node? */
1273 if (nb && nb->bank4) {
1274 /* yes, use it */
1275 b = nb->bank4;
1276 err = kobject_add(b->kobj, &dev->kobj, name);
1277 if (err)
1278 goto out;
1279
1280 per_cpu(threshold_banks, cpu)[bank] = b;
1281 refcount_inc(&b->cpus);
1282
1283 err = __threshold_add_blocks(b);
1284
1285 goto out;
1286 }
1287 }
1288
1289 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1290 if (!b) {
1291 err = -ENOMEM;
1292 goto out;
1293 }
1294
1295 b->kobj = kobject_create_and_add(name, &dev->kobj);
1296 if (!b->kobj) {
1297 err = -EINVAL;
1298 goto out_free;
1299 }
1300
1301 if (is_shared_bank(bank)) {
1302 refcount_set(&b->cpus, 1);
1303
1304 /* nb is already initialized, see above */
1305 if (nb) {
1306 WARN_ON(nb->bank4);
1307 nb->bank4 = b;
1308 }
1309 }
1310
1311 err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank));
1312 if (err)
1313 goto out_free;
1314
1315 per_cpu(threshold_banks, cpu)[bank] = b;
1316
1317 return 0;
1318
1319 out_free:
1320 kfree(b);
1321
1322 out:
1323 return err;
1324 }
1325
threshold_block_release(struct kobject * kobj)1326 static void threshold_block_release(struct kobject *kobj)
1327 {
1328 kfree(to_block(kobj));
1329 }
1330
deallocate_threshold_block(unsigned int cpu,unsigned int bank)1331 static void deallocate_threshold_block(unsigned int cpu, unsigned int bank)
1332 {
1333 struct threshold_block *pos = NULL;
1334 struct threshold_block *tmp = NULL;
1335 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1336
1337 if (!head)
1338 return;
1339
1340 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1341 list_del(&pos->miscj);
1342 kobject_put(&pos->kobj);
1343 }
1344
1345 kobject_put(&head->blocks->kobj);
1346 }
1347
__threshold_remove_blocks(struct threshold_bank * b)1348 static void __threshold_remove_blocks(struct threshold_bank *b)
1349 {
1350 struct threshold_block *pos = NULL;
1351 struct threshold_block *tmp = NULL;
1352
1353 kobject_del(b->kobj);
1354
1355 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1356 kobject_del(&pos->kobj);
1357 }
1358
threshold_remove_bank(unsigned int cpu,int bank)1359 static void threshold_remove_bank(unsigned int cpu, int bank)
1360 {
1361 struct amd_northbridge *nb;
1362 struct threshold_bank *b;
1363
1364 b = per_cpu(threshold_banks, cpu)[bank];
1365 if (!b)
1366 return;
1367
1368 if (!b->blocks)
1369 goto free_out;
1370
1371 if (is_shared_bank(bank)) {
1372 if (!refcount_dec_and_test(&b->cpus)) {
1373 __threshold_remove_blocks(b);
1374 per_cpu(threshold_banks, cpu)[bank] = NULL;
1375 return;
1376 } else {
1377 /*
1378 * the last CPU on this node using the shared bank is
1379 * going away, remove that bank now.
1380 */
1381 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1382 nb->bank4 = NULL;
1383 }
1384 }
1385
1386 deallocate_threshold_block(cpu, bank);
1387
1388 free_out:
1389 kobject_del(b->kobj);
1390 kobject_put(b->kobj);
1391 kfree(b);
1392 per_cpu(threshold_banks, cpu)[bank] = NULL;
1393 }
1394
mce_threshold_remove_device(unsigned int cpu)1395 int mce_threshold_remove_device(unsigned int cpu)
1396 {
1397 unsigned int bank;
1398
1399 for (bank = 0; bank < mca_cfg.banks; ++bank) {
1400 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1401 continue;
1402 threshold_remove_bank(cpu, bank);
1403 }
1404 kfree(per_cpu(threshold_banks, cpu));
1405 per_cpu(threshold_banks, cpu) = NULL;
1406 return 0;
1407 }
1408
1409 /* create dir/files for all valid threshold banks */
mce_threshold_create_device(unsigned int cpu)1410 int mce_threshold_create_device(unsigned int cpu)
1411 {
1412 unsigned int bank;
1413 struct threshold_bank **bp;
1414 int err = 0;
1415
1416 bp = per_cpu(threshold_banks, cpu);
1417 if (bp)
1418 return 0;
1419
1420 bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1421 GFP_KERNEL);
1422 if (!bp)
1423 return -ENOMEM;
1424
1425 per_cpu(threshold_banks, cpu) = bp;
1426
1427 for (bank = 0; bank < mca_cfg.banks; ++bank) {
1428 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1429 continue;
1430 err = threshold_create_bank(cpu, bank);
1431 if (err)
1432 goto err;
1433 }
1434 return err;
1435 err:
1436 mce_threshold_remove_device(cpu);
1437 return err;
1438 }
1439
threshold_init_device(void)1440 static __init int threshold_init_device(void)
1441 {
1442 unsigned lcpu = 0;
1443
1444 /* to hit CPUs online before the notifier is up */
1445 for_each_online_cpu(lcpu) {
1446 int err = mce_threshold_create_device(lcpu);
1447
1448 if (err)
1449 return err;
1450 }
1451
1452 if (thresholding_irq_en)
1453 mce_threshold_vector = amd_threshold_interrupt;
1454
1455 return 0;
1456 }
1457 /*
1458 * there are 3 funcs which need to be _initcalled in a logic sequence:
1459 * 1. xen_late_init_mcelog
1460 * 2. mcheck_init_device
1461 * 3. threshold_init_device
1462 *
1463 * xen_late_init_mcelog must register xen_mce_chrdev_device before
1464 * native mce_chrdev_device registration if running under xen platform;
1465 *
1466 * mcheck_init_device should be inited before threshold_init_device to
1467 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1468 *
1469 * so we use following _initcalls
1470 * 1. device_initcall(xen_late_init_mcelog);
1471 * 2. device_initcall_sync(mcheck_init_device);
1472 * 3. late_initcall(threshold_init_device);
1473 *
1474 * when running under xen, the initcall order is 1,2,3;
1475 * on baremetal, we skip 1 and we do only 2 and 3.
1476 */
1477 late_initcall(threshold_init_device);
1478