| /drivers/clk/ti/ |
| D | divider.c | 76 unsigned int div) in _get_table_val()
86 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val()
101 unsigned int div, val; in ti_clk_divider_recalc_rate() local
124 unsigned int div) in _is_valid_table_div()
134 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div) in _is_valid_div()
148 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up() local
233 int div; in ti_clk_divider_round_rate() local
243 unsigned int div, value; in ti_clk_divider_set_rate() local
282 struct clk_omap_divider *div; in _register_divider() local
329 int div; in ti_clk_parse_divider_data() local
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| /drivers/clk/berlin/ |
| D | berlin2-div.c | 77 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
95 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
114 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_disable() local
131 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_set_parent() local
162 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_get_parent() local
189 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_recalc_rate() local
246 struct berlin2_div *div; in berlin2_div_register() local
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| /drivers/clk/ |
| D | clk-divider.c | 94 unsigned int div) in _get_table_val()
105 unsigned int div, unsigned long flags, u8 width) in _get_val()
123 unsigned int div; in divider_recalc_rate() local
151 unsigned int div) in _is_valid_table_div()
161 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div, in _is_valid_div()
171 static int _round_up_table(const struct clk_div_table *table, int div) in _round_up_table()
189 static int _round_down_table(const struct clk_div_table *table, int div) in _round_down_table()
211 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up() local
264 static int _next_div(const struct clk_div_table *table, int div, in _next_div()
339 int div; in divider_round_rate_parent() local
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| D | clk-highbank.c | 209 u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4; in clk_cpu_periphclk_recalc_rate() local
221 u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT; in clk_cpu_a9bclk_recalc_rate() local
234 u32 div; in clk_periclk_recalc_rate() local
246 u32 div; in clk_periclk_round_rate() local
259 u32 div; in clk_periclk_set_rate() local
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| D | clk-cdce706.c | 32 #define CDCE706_DIVIDER(div) (13 + (div)) argument
53 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
54 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
55 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
75 unsigned div; member
192 unsigned long mul, div; in cdce706_pll_round_rate() local
218 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
298 unsigned long mul, div; in cdce706_divider_round_rate() local
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| D | clk-fixed-factor.c | 74 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor()
109 unsigned int mult, unsigned int div) in clk_register_fixed_factor()
157 u32 div, mult; in _of_fixed_factor_clk_setup() local
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| /drivers/clk/bcm/ |
| D | clk-kona.c | 57 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value()
67 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) in scaled_div_build()
82 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min()
91 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max()
108 divider(struct bcm_clk_div *div, u64 scaled_div) in divider()
118 scale_rate(struct bcm_clk_div *div, u32 rate) in scale_rate()
563 static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div) in divider_read_scaled()
591 struct bcm_clk_div *div, struct bcm_clk_trig *trig) in __div_commit()
647 struct bcm_clk_div *div, struct bcm_clk_trig *trig) in div_init()
655 struct bcm_clk_div *div, struct bcm_clk_trig *trig, in divider_write()
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| D | clk-iproc-asiu.c | 32 struct iproc_asiu_div div; member
114 unsigned int div; in iproc_asiu_clk_round_rate() local
134 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
186 const struct iproc_asiu_div *div, in iproc_asiu_setup()
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| D | clk-kona-setup.c | 55 struct bcm_clk_div *div; in clk_requires_trigger() local
83 struct bcm_clk_div *div; in peri_clk_data_offsets_valid() local
335 static bool div_valid(struct bcm_clk_div *div, const char *field_name, in div_valid()
371 struct bcm_clk_div *div; in kona_dividers_valid() local
407 struct bcm_clk_div *div; in peri_clk_data_valid() local
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| /drivers/clk/mxs/ |
| D | clk-div.c | 44 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
52 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
60 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
79 struct clk_div *div; in mxs_clk_div() local
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| D | clk-frac.c | 43 u32 div; in clk_frac_recalc_rate() local
58 u32 div; in clk_frac_round_rate() local
84 u32 div, val; in clk_frac_set_rate() local
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| /drivers/clk/imx/ |
| D | clk-pllv3.c | 119 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate() local
137 u32 val, div; in clk_pllv3_set_rate() local
167 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate() local
178 u32 div; in clk_pllv3_sys_round_rate() local
195 u32 val, div; in clk_pllv3_sys_set_rate() local
224 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate() local
239 u32 div; in clk_pllv3_av_round_rate() local
271 u32 val, div; in clk_pllv3_av_set_rate() local
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| /drivers/clk/sunxi/ |
| D | clk-sunxi.c | 43 u8 div; in sun4i_get_pll1_factors() local
167 u8 div; in sun8i_a23_get_pll1_factors() local
211 u8 div; in sun4i_get_pll5_factors() local
238 u8 div; in sun6i_a31_get_pll6_factors() local
259 u32 div; in sun5i_a13_get_ahb_factors() local
298 u8 div, calcp, calcm = 1; in sun6i_get_ahb1_factors() local
356 int div; in sun4i_get_apb1_factors() local
394 u8 div, calcm, calcp; in sun7i_a20_get_out_factors() local
903 } div[SUNXI_DIVS_MAX_QTY]; member
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| D | clk-sun9i-cpus.c | 35 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
41 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
74 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
156 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
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| /drivers/clk/renesas/ |
| D | rcar-gen3-cpg.c | 53 unsigned int div; member
137 unsigned int div; in cpg_sd_clock_calc_div() local
151 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); in cpg_sd_clock_round_rate() local
160 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); in cpg_sd_clock_set_rate() local
272 unsigned int div = 1; in rcar_gen3_cpg_clk_register() local
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| D | clk-div6.c | 39 unsigned int div; member
95 unsigned int div; in cpg_div6_clock_calc_div() local
107 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); in cpg_div6_clock_round_rate() local
116 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); in cpg_div6_clock_set_rate() local
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| /drivers/clk/mvebu/ |
| D | orion.c | 62 int *mult, int *div) in mv88f5181_get_clk_ratio()
130 int *mult, int *div) in mv88f5182_get_clk_ratio()
187 int *mult, int *div) in mv88f5281_get_clk_ratio()
253 int *mult, int *div) in mv88f6183_get_clk_ratio()
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| /drivers/gpu/drm/pl111/ |
| D | pl111_display.c | 292 int best_div = 1, div; in pl111_clk_div_choose_div() local
322 int div = pl111_clk_div_choose_div(hw, rate, prate, true); in pl111_clk_div_round_rate() local
333 int div; in pl111_clk_div_recalc_rate() local
351 int div = pl111_clk_div_choose_div(hw, rate, &prate, false); in pl111_clk_div_set_rate() local
383 struct clk_hw *div = &priv->clk_div; in pl111_init_clock_divider() local
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| /drivers/pwm/ |
| D | pwm-rcar.c | 75 unsigned int div; in rcar_pwm_get_clock_division() local
92 unsigned int div) in rcar_pwm_set_clock_control()
108 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns, in rcar_pwm_set_counter()
153 int div, ret; in rcar_pwm_config() local
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_backlight.c | 138 u32 div = 1025; in nv50_get_intensity() local
153 u32 div = 1025; in nv50_set_intensity() local
174 u32 div, val; in nva3_get_intensity() local
192 u32 div, val; in nva3_set_intensity() local
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| /drivers/media/pci/ttpci/ |
| D | budget.c | 213 u32 div = (c->frequency + 479500) / 125; in alps_bsrv2_tuner_set_params() local
252 u32 div; in alps_tdbe2_tuner_set_params() local
281 u32 div; in grundig_29504_401_tuner_set_params() local
338 u32 div; in grundig_29504_451_tuner_set_params() local
362 u32 div; in s5h1420_tuner_set_params() local
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| /drivers/video/fbdev/omap/ |
| D | sossi.c | 125 static u32 ps_to_sossi_ticks(u32 ps, int div) in ps_to_sossi_ticks()
135 int div = t->clk_div; in calc_rd_timings() local
186 int div = t->clk_div; in calc_wr_timings() local
221 static void _set_timing(int div, int tw0, int tw1) in _set_timing()
328 int div = t->clk_div; in sossi_convert_timings() local
396 int hs_pol_inv, int vs_pol_inv, int div) in sossi_setup_tearsync()
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| /drivers/clk/tegra/ |
| D | clk-divider.c | 71 int div, mul; in clk_frac_div_recalc_rate() local
91 int div, mul; in clk_frac_div_round_rate() local
110 int div; in clk_frac_div_set_rate() local
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| /drivers/clk/qcom/ |
| D | clk-regmap-divider.c | 40 u32 div; in div_set_rate() local
55 u32 div; in div_recalc_rate() local
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| /drivers/cpufreq/ |
| D | cpufreq-nforce2.c | 25 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) argument
69 unsigned char mul, div; in nforce2_calc_fsb() local
89 unsigned char mul = 0, div = 0; in nforce2_calc_pll() local
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