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Searched defs:div0 (Results 1 – 7 of 7) sorted by relevance

/drivers/clk/samsung/
Dclk-cpu.c142 unsigned long div0; in exynos_set_safe_div() local
157 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
270 unsigned long div0; in exynos5433_set_safe_div() local
285 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
Dclk-cpu.h30 unsigned long div0; member
/drivers/clk/uniphier/
Dclk-uniphier.h119 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
123 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
127 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgf100.c278 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
Dgk104.c292 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
/drivers/i2c/busses/
Di2c-sprd.c336 u32 div0 = I2C_ADDR_DVD0_CALC(high, low); in sprd_i2c_set_clk() local
/drivers/clk/nxp/
Dclk-lpc32xx.c1441 struct clk_hw_proto0 *mux0, *div0, *gate0; in lpc32xx_clk_register() local