1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched/mm.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
37 #include <linux/libfdt.h>
38 #include <linux/cpu.h>
39
40 #include <asm/debugfs.h>
41 #include <asm/processor.h>
42 #include <asm/pgtable.h>
43 #include <asm/mmu.h>
44 #include <asm/mmu_context.h>
45 #include <asm/page.h>
46 #include <asm/types.h>
47 #include <linux/uaccess.h>
48 #include <asm/machdep.h>
49 #include <asm/prom.h>
50 #include <asm/tlbflush.h>
51 #include <asm/io.h>
52 #include <asm/eeh.h>
53 #include <asm/tlb.h>
54 #include <asm/cacheflush.h>
55 #include <asm/cputable.h>
56 #include <asm/sections.h>
57 #include <asm/copro.h>
58 #include <asm/udbg.h>
59 #include <asm/code-patching.h>
60 #include <asm/fadump.h>
61 #include <asm/firmware.h>
62 #include <asm/tm.h>
63 #include <asm/trace.h>
64 #include <asm/ps3.h>
65 #include <asm/pte-walk.h>
66
67 #ifdef DEBUG
68 #define DBG(fmt...) udbg_printf(fmt)
69 #else
70 #define DBG(fmt...)
71 #endif
72
73 #ifdef DEBUG_LOW
74 #define DBG_LOW(fmt...) udbg_printf(fmt)
75 #else
76 #define DBG_LOW(fmt...)
77 #endif
78
79 #define KB (1024)
80 #define MB (1024*KB)
81 #define GB (1024L*MB)
82
83 /*
84 * Note: pte --> Linux PTE
85 * HPTE --> PowerPC Hashed Page Table Entry
86 *
87 * Execution context:
88 * htab_initialize is called with the MMU off (of course), but
89 * the kernel has been copied down to zero so it can directly
90 * reference global data. At this point it is very difficult
91 * to print debug info.
92 *
93 */
94
95 static unsigned long _SDR1;
96 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
97 EXPORT_SYMBOL_GPL(mmu_psize_defs);
98
99 u8 hpte_page_sizes[1 << LP_BITS];
100 EXPORT_SYMBOL_GPL(hpte_page_sizes);
101
102 struct hash_pte *htab_address;
103 unsigned long htab_size_bytes;
104 unsigned long htab_hash_mask;
105 EXPORT_SYMBOL_GPL(htab_hash_mask);
106 int mmu_linear_psize = MMU_PAGE_4K;
107 EXPORT_SYMBOL_GPL(mmu_linear_psize);
108 int mmu_virtual_psize = MMU_PAGE_4K;
109 int mmu_vmalloc_psize = MMU_PAGE_4K;
110 #ifdef CONFIG_SPARSEMEM_VMEMMAP
111 int mmu_vmemmap_psize = MMU_PAGE_4K;
112 #endif
113 int mmu_io_psize = MMU_PAGE_4K;
114 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
115 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
116 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
117 u16 mmu_slb_size = 64;
118 EXPORT_SYMBOL_GPL(mmu_slb_size);
119 #ifdef CONFIG_PPC_64K_PAGES
120 int mmu_ci_restrictions;
121 #endif
122 #ifdef CONFIG_DEBUG_PAGEALLOC
123 static u8 *linear_map_hash_slots;
124 static unsigned long linear_map_hash_count;
125 static DEFINE_SPINLOCK(linear_map_hash_lock);
126 #endif /* CONFIG_DEBUG_PAGEALLOC */
127 struct mmu_hash_ops mmu_hash_ops;
128 EXPORT_SYMBOL(mmu_hash_ops);
129
130 /* There are definitions of page sizes arrays to be used when none
131 * is provided by the firmware.
132 */
133
134 /* Pre-POWER4 CPUs (4k pages only)
135 */
136 static struct mmu_psize_def mmu_psize_defaults_old[] = {
137 [MMU_PAGE_4K] = {
138 .shift = 12,
139 .sllp = 0,
140 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
141 .avpnm = 0,
142 .tlbiel = 0,
143 },
144 };
145
146 /* POWER4, GPUL, POWER5
147 *
148 * Support for 16Mb large pages
149 */
150 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
151 [MMU_PAGE_4K] = {
152 .shift = 12,
153 .sllp = 0,
154 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
155 .avpnm = 0,
156 .tlbiel = 1,
157 },
158 [MMU_PAGE_16M] = {
159 .shift = 24,
160 .sllp = SLB_VSID_L,
161 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
162 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
163 .avpnm = 0x1UL,
164 .tlbiel = 0,
165 },
166 };
167
168 /*
169 * 'R' and 'C' update notes:
170 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
171 * create writeable HPTEs without C set, because the hcall H_PROTECT
172 * that we use in that case will not update C
173 * - The above is however not a problem, because we also don't do that
174 * fancy "no flush" variant of eviction and we use H_REMOVE which will
175 * do the right thing and thus we don't have the race I described earlier
176 *
177 * - Under bare metal, we do have the race, so we need R and C set
178 * - We make sure R is always set and never lost
179 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
180 */
htab_convert_pte_flags(unsigned long pteflags)181 unsigned long htab_convert_pte_flags(unsigned long pteflags)
182 {
183 unsigned long rflags = 0;
184
185 /* _PAGE_EXEC -> NOEXEC */
186 if ((pteflags & _PAGE_EXEC) == 0)
187 rflags |= HPTE_R_N;
188 /*
189 * PPP bits:
190 * Linux uses slb key 0 for kernel and 1 for user.
191 * kernel RW areas are mapped with PPP=0b000
192 * User area is mapped with PPP=0b010 for read/write
193 * or PPP=0b011 for read-only (including writeable but clean pages).
194 */
195 if (pteflags & _PAGE_PRIVILEGED) {
196 /*
197 * Kernel read only mapped with ppp bits 0b110
198 */
199 if (!(pteflags & _PAGE_WRITE)) {
200 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
201 rflags |= (HPTE_R_PP0 | 0x2);
202 else
203 rflags |= 0x3;
204 }
205 } else {
206 if (pteflags & _PAGE_RWX)
207 rflags |= 0x2;
208 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
209 rflags |= 0x1;
210 }
211 /*
212 * We can't allow hardware to update hpte bits. Hence always
213 * set 'R' bit and set 'C' if it is a write fault
214 */
215 rflags |= HPTE_R_R;
216
217 if (pteflags & _PAGE_DIRTY)
218 rflags |= HPTE_R_C;
219 /*
220 * Add in WIG bits
221 */
222
223 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
224 rflags |= HPTE_R_I;
225 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
226 rflags |= (HPTE_R_I | HPTE_R_G);
227 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
228 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
229 else
230 /*
231 * Add memory coherence if cache inhibited is not set
232 */
233 rflags |= HPTE_R_M;
234
235 return rflags;
236 }
237
htab_bolt_mapping(unsigned long vstart,unsigned long vend,unsigned long pstart,unsigned long prot,int psize,int ssize)238 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
239 unsigned long pstart, unsigned long prot,
240 int psize, int ssize)
241 {
242 unsigned long vaddr, paddr;
243 unsigned int step, shift;
244 int ret = 0;
245
246 shift = mmu_psize_defs[psize].shift;
247 step = 1 << shift;
248
249 prot = htab_convert_pte_flags(prot);
250
251 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
252 vstart, vend, pstart, prot, psize, ssize);
253
254 for (vaddr = vstart, paddr = pstart; vaddr < vend;
255 vaddr += step, paddr += step) {
256 unsigned long hash, hpteg;
257 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
258 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
259 unsigned long tprot = prot;
260
261 /*
262 * If we hit a bad address return error.
263 */
264 if (!vsid)
265 return -1;
266 /* Make kernel text executable */
267 if (overlaps_kernel_text(vaddr, vaddr + step))
268 tprot &= ~HPTE_R_N;
269
270 /* Make kvm guest trampolines executable */
271 if (overlaps_kvm_tmp(vaddr, vaddr + step))
272 tprot &= ~HPTE_R_N;
273
274 /*
275 * If relocatable, check if it overlaps interrupt vectors that
276 * are copied down to real 0. For relocatable kernel
277 * (e.g. kdump case) we copy interrupt vectors down to real
278 * address 0. Mark that region as executable. This is
279 * because on p8 system with relocation on exception feature
280 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
281 * in order to execute the interrupt handlers in virtual
282 * mode the vector region need to be marked as executable.
283 */
284 if ((PHYSICAL_START > MEMORY_START) &&
285 overlaps_interrupt_vector_text(vaddr, vaddr + step))
286 tprot &= ~HPTE_R_N;
287
288 hash = hpt_hash(vpn, shift, ssize);
289 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
290
291 BUG_ON(!mmu_hash_ops.hpte_insert);
292 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
293 HPTE_V_BOLTED, psize, psize,
294 ssize);
295 if (ret == -1) {
296 /* Try to remove a non bolted entry */
297 ret = mmu_hash_ops.hpte_remove(hpteg);
298 if (ret != -1)
299 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
300 HPTE_V_BOLTED, psize, psize,
301 ssize);
302 }
303 if (ret < 0)
304 break;
305
306 cond_resched();
307 #ifdef CONFIG_DEBUG_PAGEALLOC
308 if (debug_pagealloc_enabled() &&
309 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
310 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
311 #endif /* CONFIG_DEBUG_PAGEALLOC */
312 }
313 return ret < 0 ? ret : 0;
314 }
315
htab_remove_mapping(unsigned long vstart,unsigned long vend,int psize,int ssize)316 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
317 int psize, int ssize)
318 {
319 unsigned long vaddr;
320 unsigned int step, shift;
321 int rc;
322 int ret = 0;
323
324 shift = mmu_psize_defs[psize].shift;
325 step = 1 << shift;
326
327 if (!mmu_hash_ops.hpte_removebolted)
328 return -ENODEV;
329
330 for (vaddr = vstart; vaddr < vend; vaddr += step) {
331 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
332 if (rc == -ENOENT) {
333 ret = -ENOENT;
334 continue;
335 }
336 if (rc < 0)
337 return rc;
338 }
339
340 return ret;
341 }
342
343 static bool disable_1tb_segments = false;
344
parse_disable_1tb_segments(char * p)345 static int __init parse_disable_1tb_segments(char *p)
346 {
347 disable_1tb_segments = true;
348 return 0;
349 }
350 early_param("disable_1tb_segments", parse_disable_1tb_segments);
351
htab_dt_scan_seg_sizes(unsigned long node,const char * uname,int depth,void * data)352 static int __init htab_dt_scan_seg_sizes(unsigned long node,
353 const char *uname, int depth,
354 void *data)
355 {
356 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
357 const __be32 *prop;
358 int size = 0;
359
360 /* We are scanning "cpu" nodes only */
361 if (type == NULL || strcmp(type, "cpu") != 0)
362 return 0;
363
364 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
365 if (prop == NULL)
366 return 0;
367 for (; size >= 4; size -= 4, ++prop) {
368 if (be32_to_cpu(prop[0]) == 40) {
369 DBG("1T segment support detected\n");
370
371 if (disable_1tb_segments) {
372 DBG("1T segments disabled by command line\n");
373 break;
374 }
375
376 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
377 return 1;
378 }
379 }
380 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
381 return 0;
382 }
383
get_idx_from_shift(unsigned int shift)384 static int __init get_idx_from_shift(unsigned int shift)
385 {
386 int idx = -1;
387
388 switch (shift) {
389 case 0xc:
390 idx = MMU_PAGE_4K;
391 break;
392 case 0x10:
393 idx = MMU_PAGE_64K;
394 break;
395 case 0x14:
396 idx = MMU_PAGE_1M;
397 break;
398 case 0x18:
399 idx = MMU_PAGE_16M;
400 break;
401 case 0x22:
402 idx = MMU_PAGE_16G;
403 break;
404 }
405 return idx;
406 }
407
htab_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)408 static int __init htab_dt_scan_page_sizes(unsigned long node,
409 const char *uname, int depth,
410 void *data)
411 {
412 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
413 const __be32 *prop;
414 int size = 0;
415
416 /* We are scanning "cpu" nodes only */
417 if (type == NULL || strcmp(type, "cpu") != 0)
418 return 0;
419
420 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
421 if (!prop)
422 return 0;
423
424 pr_info("Page sizes from device-tree:\n");
425 size /= 4;
426 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
427 while(size > 0) {
428 unsigned int base_shift = be32_to_cpu(prop[0]);
429 unsigned int slbenc = be32_to_cpu(prop[1]);
430 unsigned int lpnum = be32_to_cpu(prop[2]);
431 struct mmu_psize_def *def;
432 int idx, base_idx;
433
434 size -= 3; prop += 3;
435 base_idx = get_idx_from_shift(base_shift);
436 if (base_idx < 0) {
437 /* skip the pte encoding also */
438 prop += lpnum * 2; size -= lpnum * 2;
439 continue;
440 }
441 def = &mmu_psize_defs[base_idx];
442 if (base_idx == MMU_PAGE_16M)
443 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
444
445 def->shift = base_shift;
446 if (base_shift <= 23)
447 def->avpnm = 0;
448 else
449 def->avpnm = (1 << (base_shift - 23)) - 1;
450 def->sllp = slbenc;
451 /*
452 * We don't know for sure what's up with tlbiel, so
453 * for now we only set it for 4K and 64K pages
454 */
455 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
456 def->tlbiel = 1;
457 else
458 def->tlbiel = 0;
459
460 while (size > 0 && lpnum) {
461 unsigned int shift = be32_to_cpu(prop[0]);
462 int penc = be32_to_cpu(prop[1]);
463
464 prop += 2; size -= 2;
465 lpnum--;
466
467 idx = get_idx_from_shift(shift);
468 if (idx < 0)
469 continue;
470
471 if (penc == -1)
472 pr_err("Invalid penc for base_shift=%d "
473 "shift=%d\n", base_shift, shift);
474
475 def->penc[idx] = penc;
476 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
477 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
478 base_shift, shift, def->sllp,
479 def->avpnm, def->tlbiel, def->penc[idx]);
480 }
481 }
482
483 return 1;
484 }
485
486 #ifdef CONFIG_HUGETLB_PAGE
487 /* Scan for 16G memory blocks that have been set aside for huge pages
488 * and reserve those blocks for 16G huge pages.
489 */
htab_dt_scan_hugepage_blocks(unsigned long node,const char * uname,int depth,void * data)490 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
491 const char *uname, int depth,
492 void *data) {
493 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
494 const __be64 *addr_prop;
495 const __be32 *page_count_prop;
496 unsigned int expected_pages;
497 long unsigned int phys_addr;
498 long unsigned int block_size;
499
500 /* We are scanning "memory" nodes only */
501 if (type == NULL || strcmp(type, "memory") != 0)
502 return 0;
503
504 /* This property is the log base 2 of the number of virtual pages that
505 * will represent this memory block. */
506 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
507 if (page_count_prop == NULL)
508 return 0;
509 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
510 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
511 if (addr_prop == NULL)
512 return 0;
513 phys_addr = be64_to_cpu(addr_prop[0]);
514 block_size = be64_to_cpu(addr_prop[1]);
515 if (block_size != (16 * GB))
516 return 0;
517 printk(KERN_INFO "Huge page(16GB) memory: "
518 "addr = 0x%lX size = 0x%lX pages = %d\n",
519 phys_addr, block_size, expected_pages);
520 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
521 memblock_reserve(phys_addr, block_size * expected_pages);
522 pseries_add_gpage(phys_addr, block_size, expected_pages);
523 }
524 return 0;
525 }
526 #endif /* CONFIG_HUGETLB_PAGE */
527
mmu_psize_set_default_penc(void)528 static void mmu_psize_set_default_penc(void)
529 {
530 int bpsize, apsize;
531 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
532 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
533 mmu_psize_defs[bpsize].penc[apsize] = -1;
534 }
535
536 #ifdef CONFIG_PPC_64K_PAGES
537
might_have_hea(void)538 static bool might_have_hea(void)
539 {
540 /*
541 * The HEA ethernet adapter requires awareness of the
542 * GX bus. Without that awareness we can easily assume
543 * we will never see an HEA ethernet device.
544 */
545 #ifdef CONFIG_IBMEBUS
546 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
547 firmware_has_feature(FW_FEATURE_SPLPAR);
548 #else
549 return false;
550 #endif
551 }
552
553 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
554
htab_scan_page_sizes(void)555 static void __init htab_scan_page_sizes(void)
556 {
557 int rc;
558
559 /* se the invalid penc to -1 */
560 mmu_psize_set_default_penc();
561
562 /* Default to 4K pages only */
563 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
564 sizeof(mmu_psize_defaults_old));
565
566 /*
567 * Try to find the available page sizes in the device-tree
568 */
569 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
570 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
571 /*
572 * Nothing in the device-tree, but the CPU supports 16M pages,
573 * so let's fallback on a known size list for 16M capable CPUs.
574 */
575 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
576 sizeof(mmu_psize_defaults_gp));
577 }
578
579 #ifdef CONFIG_HUGETLB_PAGE
580 /* Reserve 16G huge page memory sections for huge pages */
581 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
582 #endif /* CONFIG_HUGETLB_PAGE */
583 }
584
585 /*
586 * Fill in the hpte_page_sizes[] array.
587 * We go through the mmu_psize_defs[] array looking for all the
588 * supported base/actual page size combinations. Each combination
589 * has a unique pagesize encoding (penc) value in the low bits of
590 * the LP field of the HPTE. For actual page sizes less than 1MB,
591 * some of the upper LP bits are used for RPN bits, meaning that
592 * we need to fill in several entries in hpte_page_sizes[].
593 *
594 * In diagrammatic form, with r = RPN bits and z = page size bits:
595 * PTE LP actual page size
596 * rrrr rrrz >=8KB
597 * rrrr rrzz >=16KB
598 * rrrr rzzz >=32KB
599 * rrrr zzzz >=64KB
600 * ...
601 *
602 * The zzzz bits are implementation-specific but are chosen so that
603 * no encoding for a larger page size uses the same value in its
604 * low-order N bits as the encoding for the 2^(12+N) byte page size
605 * (if it exists).
606 */
init_hpte_page_sizes(void)607 static void init_hpte_page_sizes(void)
608 {
609 long int ap, bp;
610 long int shift, penc;
611
612 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
613 if (!mmu_psize_defs[bp].shift)
614 continue; /* not a supported page size */
615 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
616 penc = mmu_psize_defs[bp].penc[ap];
617 if (penc == -1)
618 continue;
619 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
620 if (shift <= 0)
621 continue; /* should never happen */
622 /*
623 * For page sizes less than 1MB, this loop
624 * replicates the entry for all possible values
625 * of the rrrr bits.
626 */
627 while (penc < (1 << LP_BITS)) {
628 hpte_page_sizes[penc] = (ap << 4) | bp;
629 penc += 1 << shift;
630 }
631 }
632 }
633 }
634
htab_init_page_sizes(void)635 static void __init htab_init_page_sizes(void)
636 {
637 init_hpte_page_sizes();
638
639 if (!debug_pagealloc_enabled()) {
640 /*
641 * Pick a size for the linear mapping. Currently, we only
642 * support 16M, 1M and 4K which is the default
643 */
644 if (mmu_psize_defs[MMU_PAGE_16M].shift)
645 mmu_linear_psize = MMU_PAGE_16M;
646 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
647 mmu_linear_psize = MMU_PAGE_1M;
648 }
649
650 #ifdef CONFIG_PPC_64K_PAGES
651 /*
652 * Pick a size for the ordinary pages. Default is 4K, we support
653 * 64K for user mappings and vmalloc if supported by the processor.
654 * We only use 64k for ioremap if the processor
655 * (and firmware) support cache-inhibited large pages.
656 * If not, we use 4k and set mmu_ci_restrictions so that
657 * hash_page knows to switch processes that use cache-inhibited
658 * mappings to 4k pages.
659 */
660 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
661 mmu_virtual_psize = MMU_PAGE_64K;
662 mmu_vmalloc_psize = MMU_PAGE_64K;
663 if (mmu_linear_psize == MMU_PAGE_4K)
664 mmu_linear_psize = MMU_PAGE_64K;
665 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
666 /*
667 * When running on pSeries using 64k pages for ioremap
668 * would stop us accessing the HEA ethernet. So if we
669 * have the chance of ever seeing one, stay at 4k.
670 */
671 if (!might_have_hea())
672 mmu_io_psize = MMU_PAGE_64K;
673 } else
674 mmu_ci_restrictions = 1;
675 }
676 #endif /* CONFIG_PPC_64K_PAGES */
677
678 #ifdef CONFIG_SPARSEMEM_VMEMMAP
679 /* We try to use 16M pages for vmemmap if that is supported
680 * and we have at least 1G of RAM at boot
681 */
682 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
683 memblock_phys_mem_size() >= 0x40000000)
684 mmu_vmemmap_psize = MMU_PAGE_16M;
685 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
686 mmu_vmemmap_psize = MMU_PAGE_64K;
687 else
688 mmu_vmemmap_psize = MMU_PAGE_4K;
689 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
690
691 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
692 "virtual = %d, io = %d"
693 #ifdef CONFIG_SPARSEMEM_VMEMMAP
694 ", vmemmap = %d"
695 #endif
696 "\n",
697 mmu_psize_defs[mmu_linear_psize].shift,
698 mmu_psize_defs[mmu_virtual_psize].shift,
699 mmu_psize_defs[mmu_io_psize].shift
700 #ifdef CONFIG_SPARSEMEM_VMEMMAP
701 ,mmu_psize_defs[mmu_vmemmap_psize].shift
702 #endif
703 );
704 }
705
htab_dt_scan_pftsize(unsigned long node,const char * uname,int depth,void * data)706 static int __init htab_dt_scan_pftsize(unsigned long node,
707 const char *uname, int depth,
708 void *data)
709 {
710 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
711 const __be32 *prop;
712
713 /* We are scanning "cpu" nodes only */
714 if (type == NULL || strcmp(type, "cpu") != 0)
715 return 0;
716
717 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
718 if (prop != NULL) {
719 /* pft_size[0] is the NUMA CEC cookie */
720 ppc64_pft_size = be32_to_cpu(prop[1]);
721 return 1;
722 }
723 return 0;
724 }
725
htab_shift_for_mem_size(unsigned long mem_size)726 unsigned htab_shift_for_mem_size(unsigned long mem_size)
727 {
728 unsigned memshift = __ilog2(mem_size);
729 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
730 unsigned pteg_shift;
731
732 /* round mem_size up to next power of 2 */
733 if ((1UL << memshift) < mem_size)
734 memshift += 1;
735
736 /* aim for 2 pages / pteg */
737 pteg_shift = memshift - (pshift + 1);
738
739 /*
740 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
741 * size permitted by the architecture.
742 */
743 return max(pteg_shift + 7, 18U);
744 }
745
htab_get_table_size(void)746 static unsigned long __init htab_get_table_size(void)
747 {
748 /* If hash size isn't already provided by the platform, we try to
749 * retrieve it from the device-tree. If it's not there neither, we
750 * calculate it now based on the total RAM size
751 */
752 if (ppc64_pft_size == 0)
753 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
754 if (ppc64_pft_size)
755 return 1UL << ppc64_pft_size;
756
757 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
758 }
759
760 #ifdef CONFIG_MEMORY_HOTPLUG
resize_hpt_for_hotplug(unsigned long new_mem_size)761 void resize_hpt_for_hotplug(unsigned long new_mem_size)
762 {
763 unsigned target_hpt_shift;
764
765 if (!mmu_hash_ops.resize_hpt)
766 return;
767
768 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
769
770 /*
771 * To avoid lots of HPT resizes if memory size is fluctuating
772 * across a boundary, we deliberately have some hysterisis
773 * here: we immediately increase the HPT size if the target
774 * shift exceeds the current shift, but we won't attempt to
775 * reduce unless the target shift is at least 2 below the
776 * current shift
777 */
778 if ((target_hpt_shift > ppc64_pft_size)
779 || (target_hpt_shift < (ppc64_pft_size - 1))) {
780 int rc;
781
782 rc = mmu_hash_ops.resize_hpt(target_hpt_shift);
783 if (rc)
784 printk(KERN_WARNING
785 "Unable to resize hash page table to target order %d: %d\n",
786 target_hpt_shift, rc);
787 }
788 }
789
hash__create_section_mapping(unsigned long start,unsigned long end)790 int hash__create_section_mapping(unsigned long start, unsigned long end)
791 {
792 int rc = htab_bolt_mapping(start, end, __pa(start),
793 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
794 mmu_kernel_ssize);
795
796 if (rc < 0) {
797 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
798 mmu_kernel_ssize);
799 BUG_ON(rc2 && (rc2 != -ENOENT));
800 }
801 return rc;
802 }
803
hash__remove_section_mapping(unsigned long start,unsigned long end)804 int hash__remove_section_mapping(unsigned long start, unsigned long end)
805 {
806 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
807 mmu_kernel_ssize);
808 WARN_ON(rc < 0);
809 return rc;
810 }
811 #endif /* CONFIG_MEMORY_HOTPLUG */
812
update_hid_for_hash(void)813 static void update_hid_for_hash(void)
814 {
815 unsigned long hid0;
816 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
817
818 asm volatile("ptesync": : :"memory");
819 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
820 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
821 : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
822 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
823 trace_tlbie(0, 0, rb, 0, 2, 0, 0);
824
825 /*
826 * now switch the HID
827 */
828 hid0 = mfspr(SPRN_HID0);
829 hid0 &= ~HID0_POWER9_RADIX;
830 mtspr(SPRN_HID0, hid0);
831 asm volatile("isync": : :"memory");
832
833 /* Wait for it to happen */
834 while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
835 cpu_relax();
836 }
837
hash_init_partition_table(phys_addr_t hash_table,unsigned long htab_size)838 static void __init hash_init_partition_table(phys_addr_t hash_table,
839 unsigned long htab_size)
840 {
841 mmu_partition_table_init();
842
843 /*
844 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
845 * For now, UPRT is 0 and we have no segment table.
846 */
847 htab_size = __ilog2(htab_size) - 18;
848 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
849 pr_info("Partition table %p\n", partition_tb);
850 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
851 update_hid_for_hash();
852 }
853
htab_initialize(void)854 static void __init htab_initialize(void)
855 {
856 unsigned long table;
857 unsigned long pteg_count;
858 unsigned long prot;
859 unsigned long base = 0, size = 0;
860 struct memblock_region *reg;
861
862 DBG(" -> htab_initialize()\n");
863
864 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
865 mmu_kernel_ssize = MMU_SEGSIZE_1T;
866 mmu_highuser_ssize = MMU_SEGSIZE_1T;
867 printk(KERN_INFO "Using 1TB segments\n");
868 }
869
870 /*
871 * Calculate the required size of the htab. We want the number of
872 * PTEGs to equal one half the number of real pages.
873 */
874 htab_size_bytes = htab_get_table_size();
875 pteg_count = htab_size_bytes >> 7;
876
877 htab_hash_mask = pteg_count - 1;
878
879 if (firmware_has_feature(FW_FEATURE_LPAR) ||
880 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
881 /* Using a hypervisor which owns the htab */
882 htab_address = NULL;
883 _SDR1 = 0;
884 /*
885 * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
886 * to inform the hypervisor that we wish to use the HPT.
887 */
888 if (cpu_has_feature(CPU_FTR_ARCH_300))
889 register_process_table(0, 0, 0);
890 #ifdef CONFIG_FA_DUMP
891 /*
892 * If firmware assisted dump is active firmware preserves
893 * the contents of htab along with entire partition memory.
894 * Clear the htab if firmware assisted dump is active so
895 * that we dont end up using old mappings.
896 */
897 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
898 mmu_hash_ops.hpte_clear_all();
899 #endif
900 } else {
901 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
902
903 #ifdef CONFIG_PPC_CELL
904 /*
905 * Cell may require the hash table down low when using the
906 * Axon IOMMU in order to fit the dynamic region over it, see
907 * comments in cell/iommu.c
908 */
909 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
910 limit = 0x80000000;
911 pr_info("Hash table forced below 2G for Axon IOMMU\n");
912 }
913 #endif /* CONFIG_PPC_CELL */
914
915 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
916 limit);
917
918 DBG("Hash table allocated at %lx, size: %lx\n", table,
919 htab_size_bytes);
920
921 htab_address = __va(table);
922
923 /* htab absolute addr + encoded htabsize */
924 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
925
926 /* Initialize the HPT with no entries */
927 memset((void *)table, 0, htab_size_bytes);
928
929 if (!cpu_has_feature(CPU_FTR_ARCH_300))
930 /* Set SDR1 */
931 mtspr(SPRN_SDR1, _SDR1);
932 else
933 hash_init_partition_table(table, htab_size_bytes);
934 }
935
936 prot = pgprot_val(PAGE_KERNEL);
937
938 #ifdef CONFIG_DEBUG_PAGEALLOC
939 if (debug_pagealloc_enabled()) {
940 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
941 linear_map_hash_slots = __va(memblock_alloc_base(
942 linear_map_hash_count, 1, ppc64_rma_size));
943 memset(linear_map_hash_slots, 0, linear_map_hash_count);
944 }
945 #endif /* CONFIG_DEBUG_PAGEALLOC */
946
947 /* create bolted the linear mapping in the hash table */
948 for_each_memblock(memory, reg) {
949 base = (unsigned long)__va(reg->base);
950 size = reg->size;
951
952 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
953 base, size, prot);
954
955 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
956 prot, mmu_linear_psize, mmu_kernel_ssize));
957 }
958 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
959
960 /*
961 * If we have a memory_limit and we've allocated TCEs then we need to
962 * explicitly map the TCE area at the top of RAM. We also cope with the
963 * case that the TCEs start below memory_limit.
964 * tce_alloc_start/end are 16MB aligned so the mapping should work
965 * for either 4K or 16MB pages.
966 */
967 if (tce_alloc_start) {
968 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
969 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
970
971 if (base + size >= tce_alloc_start)
972 tce_alloc_start = base + size + 1;
973
974 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
975 __pa(tce_alloc_start), prot,
976 mmu_linear_psize, mmu_kernel_ssize));
977 }
978
979
980 DBG(" <- htab_initialize()\n");
981 }
982 #undef KB
983 #undef MB
984
hash__early_init_devtree(void)985 void __init hash__early_init_devtree(void)
986 {
987 /* Initialize segment sizes */
988 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
989
990 /* Initialize page sizes */
991 htab_scan_page_sizes();
992 }
993
hash__early_init_mmu(void)994 void __init hash__early_init_mmu(void)
995 {
996 /*
997 * We have code in __hash_page_64K() and elsewhere, which assumes it can
998 * do the following:
999 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1000 *
1001 * Where the slot number is between 0-15, and values of 8-15 indicate
1002 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
1003 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1004 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1005 * with a BUILD_BUG_ON().
1006 */
1007 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1008
1009 htab_init_page_sizes();
1010
1011 /*
1012 * initialize page table size
1013 */
1014 __pte_frag_nr = H_PTE_FRAG_NR;
1015 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1016
1017 __pte_index_size = H_PTE_INDEX_SIZE;
1018 __pmd_index_size = H_PMD_INDEX_SIZE;
1019 __pud_index_size = H_PUD_INDEX_SIZE;
1020 __pgd_index_size = H_PGD_INDEX_SIZE;
1021 __pmd_cache_index = H_PMD_CACHE_INDEX;
1022 __pte_table_size = H_PTE_TABLE_SIZE;
1023 __pmd_table_size = H_PMD_TABLE_SIZE;
1024 __pud_table_size = H_PUD_TABLE_SIZE;
1025 __pgd_table_size = H_PGD_TABLE_SIZE;
1026 /*
1027 * 4k use hugepd format, so for hash set then to
1028 * zero
1029 */
1030 __pmd_val_bits = 0;
1031 __pud_val_bits = 0;
1032 __pgd_val_bits = 0;
1033
1034 __kernel_virt_start = H_KERN_VIRT_START;
1035 __kernel_virt_size = H_KERN_VIRT_SIZE;
1036 __vmalloc_start = H_VMALLOC_START;
1037 __vmalloc_end = H_VMALLOC_END;
1038 __kernel_io_start = H_KERN_IO_START;
1039 vmemmap = (struct page *)H_VMEMMAP_BASE;
1040 ioremap_bot = IOREMAP_BASE;
1041
1042 #ifdef CONFIG_PCI
1043 pci_io_base = ISA_IO_BASE;
1044 #endif
1045
1046 /* Select appropriate backend */
1047 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1048 ps3_early_mm_init();
1049 else if (firmware_has_feature(FW_FEATURE_LPAR))
1050 hpte_init_pseries();
1051 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1052 hpte_init_native();
1053
1054 if (!mmu_hash_ops.hpte_insert)
1055 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1056
1057 /* Initialize the MMU Hash table and create the linear mapping
1058 * of memory. Has to be done before SLB initialization as this is
1059 * currently where the page size encoding is obtained.
1060 */
1061 htab_initialize();
1062
1063 pr_info("Initializing hash mmu with SLB\n");
1064 /* Initialize SLB management */
1065 slb_initialize();
1066 }
1067
1068 #ifdef CONFIG_SMP
hash__early_init_mmu_secondary(void)1069 void hash__early_init_mmu_secondary(void)
1070 {
1071 /* Initialize hash table for that CPU */
1072 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1073
1074 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
1075 update_hid_for_hash();
1076
1077 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1078 mtspr(SPRN_SDR1, _SDR1);
1079 else
1080 mtspr(SPRN_PTCR,
1081 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1082 }
1083 /* Initialize SLB */
1084 slb_initialize();
1085 }
1086 #endif /* CONFIG_SMP */
1087
1088 /*
1089 * Called by asm hashtable.S for doing lazy icache flush
1090 */
hash_page_do_lazy_icache(unsigned int pp,pte_t pte,int trap)1091 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1092 {
1093 struct page *page;
1094
1095 if (!pfn_valid(pte_pfn(pte)))
1096 return pp;
1097
1098 page = pte_page(pte);
1099
1100 /* page is dirty */
1101 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1102 if (trap == 0x400) {
1103 flush_dcache_icache_page(page);
1104 set_bit(PG_arch_1, &page->flags);
1105 } else
1106 pp |= HPTE_R_N;
1107 }
1108 return pp;
1109 }
1110
1111 #ifdef CONFIG_PPC_MM_SLICES
get_paca_psize(unsigned long addr)1112 static unsigned int get_paca_psize(unsigned long addr)
1113 {
1114 u64 lpsizes;
1115 unsigned char *hpsizes;
1116 unsigned long index, mask_index;
1117
1118 if (addr < SLICE_LOW_TOP) {
1119 lpsizes = get_paca()->mm_ctx_low_slices_psize;
1120 index = GET_LOW_SLICE_INDEX(addr);
1121 return (lpsizes >> (index * 4)) & 0xF;
1122 }
1123 hpsizes = get_paca()->mm_ctx_high_slices_psize;
1124 index = GET_HIGH_SLICE_INDEX(addr);
1125 mask_index = index & 0x1;
1126 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1127 }
1128
1129 #else
get_paca_psize(unsigned long addr)1130 unsigned int get_paca_psize(unsigned long addr)
1131 {
1132 return get_paca()->mm_ctx_user_psize;
1133 }
1134 #endif
1135
1136 /*
1137 * Demote a segment to using 4k pages.
1138 * For now this makes the whole process use 4k pages.
1139 */
1140 #ifdef CONFIG_PPC_64K_PAGES
demote_segment_4k(struct mm_struct * mm,unsigned long addr)1141 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1142 {
1143 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1144 return;
1145 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1146 copro_flush_all_slbs(mm);
1147 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1148
1149 copy_mm_to_paca(mm);
1150 slb_flush_and_rebolt();
1151 }
1152 }
1153 #endif /* CONFIG_PPC_64K_PAGES */
1154
1155 #ifdef CONFIG_PPC_SUBPAGE_PROT
1156 /*
1157 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1158 * Userspace sets the subpage permissions using the subpage_prot system call.
1159 *
1160 * Result is 0: full permissions, _PAGE_RW: read-only,
1161 * _PAGE_RWX: no access.
1162 */
subpage_protection(struct mm_struct * mm,unsigned long ea)1163 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1164 {
1165 struct subpage_prot_table *spt = &mm->context.spt;
1166 u32 spp = 0;
1167 u32 **sbpm, *sbpp;
1168
1169 if (ea >= spt->maxaddr)
1170 return 0;
1171 if (ea < 0x100000000UL) {
1172 /* addresses below 4GB use spt->low_prot */
1173 sbpm = spt->low_prot;
1174 } else {
1175 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1176 if (!sbpm)
1177 return 0;
1178 }
1179 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1180 if (!sbpp)
1181 return 0;
1182 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1183
1184 /* extract 2-bit bitfield for this 4k subpage */
1185 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1186
1187 /*
1188 * 0 -> full premission
1189 * 1 -> Read only
1190 * 2 -> no access.
1191 * We return the flag that need to be cleared.
1192 */
1193 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1194 return spp;
1195 }
1196
1197 #else /* CONFIG_PPC_SUBPAGE_PROT */
subpage_protection(struct mm_struct * mm,unsigned long ea)1198 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1199 {
1200 return 0;
1201 }
1202 #endif
1203
hash_failure_debug(unsigned long ea,unsigned long access,unsigned long vsid,unsigned long trap,int ssize,int psize,int lpsize,unsigned long pte)1204 void hash_failure_debug(unsigned long ea, unsigned long access,
1205 unsigned long vsid, unsigned long trap,
1206 int ssize, int psize, int lpsize, unsigned long pte)
1207 {
1208 if (!printk_ratelimit())
1209 return;
1210 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1211 ea, access, current->comm);
1212 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1213 trap, vsid, ssize, psize, lpsize, pte);
1214 }
1215
check_paca_psize(unsigned long ea,struct mm_struct * mm,int psize,bool user_region)1216 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1217 int psize, bool user_region)
1218 {
1219 if (user_region) {
1220 if (psize != get_paca_psize(ea)) {
1221 copy_mm_to_paca(mm);
1222 slb_flush_and_rebolt();
1223 }
1224 } else if (get_paca()->vmalloc_sllp !=
1225 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1226 get_paca()->vmalloc_sllp =
1227 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1228 slb_vmalloc_update();
1229 }
1230 }
1231
1232 /* Result code is:
1233 * 0 - handled
1234 * 1 - normal page fault
1235 * -1 - critical hash insertion error
1236 * -2 - access not permitted by subpage protection mechanism
1237 */
hash_page_mm(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap,unsigned long flags)1238 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1239 unsigned long access, unsigned long trap,
1240 unsigned long flags)
1241 {
1242 bool is_thp;
1243 enum ctx_state prev_state = exception_enter();
1244 pgd_t *pgdir;
1245 unsigned long vsid;
1246 pte_t *ptep;
1247 unsigned hugeshift;
1248 int rc, user_region = 0;
1249 int psize, ssize;
1250
1251 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1252 ea, access, trap);
1253 trace_hash_fault(ea, access, trap);
1254
1255 /* Get region & vsid */
1256 switch (REGION_ID(ea)) {
1257 case USER_REGION_ID:
1258 user_region = 1;
1259 if (! mm) {
1260 DBG_LOW(" user region with no mm !\n");
1261 rc = 1;
1262 goto bail;
1263 }
1264 psize = get_slice_psize(mm, ea);
1265 ssize = user_segment_size(ea);
1266 vsid = get_vsid(mm->context.id, ea, ssize);
1267 break;
1268 case VMALLOC_REGION_ID:
1269 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1270 if (ea < VMALLOC_END)
1271 psize = mmu_vmalloc_psize;
1272 else
1273 psize = mmu_io_psize;
1274 ssize = mmu_kernel_ssize;
1275 break;
1276 default:
1277 /* Not a valid range
1278 * Send the problem up to do_page_fault
1279 */
1280 rc = 1;
1281 goto bail;
1282 }
1283 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1284
1285 /* Bad address. */
1286 if (!vsid) {
1287 DBG_LOW("Bad address!\n");
1288 rc = 1;
1289 goto bail;
1290 }
1291 /* Get pgdir */
1292 pgdir = mm->pgd;
1293 if (pgdir == NULL) {
1294 rc = 1;
1295 goto bail;
1296 }
1297
1298 /* Check CPU locality */
1299 if (user_region && mm_is_thread_local(mm))
1300 flags |= HPTE_LOCAL_UPDATE;
1301
1302 #ifndef CONFIG_PPC_64K_PAGES
1303 /* If we use 4K pages and our psize is not 4K, then we might
1304 * be hitting a special driver mapping, and need to align the
1305 * address before we fetch the PTE.
1306 *
1307 * It could also be a hugepage mapping, in which case this is
1308 * not necessary, but it's not harmful, either.
1309 */
1310 if (psize != MMU_PAGE_4K)
1311 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1312 #endif /* CONFIG_PPC_64K_PAGES */
1313
1314 /* Get PTE and page size from page tables */
1315 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1316 if (ptep == NULL || !pte_present(*ptep)) {
1317 DBG_LOW(" no PTE !\n");
1318 rc = 1;
1319 goto bail;
1320 }
1321
1322 /* Add _PAGE_PRESENT to the required access perm */
1323 access |= _PAGE_PRESENT;
1324
1325 /* Pre-check access permissions (will be re-checked atomically
1326 * in __hash_page_XX but this pre-check is a fast path
1327 */
1328 if (!check_pte_access(access, pte_val(*ptep))) {
1329 DBG_LOW(" no access !\n");
1330 rc = 1;
1331 goto bail;
1332 }
1333
1334 if (hugeshift) {
1335 if (is_thp)
1336 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1337 trap, flags, ssize, psize);
1338 #ifdef CONFIG_HUGETLB_PAGE
1339 else
1340 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1341 flags, ssize, hugeshift, psize);
1342 #else
1343 else {
1344 /*
1345 * if we have hugeshift, and is not transhuge with
1346 * hugetlb disabled, something is really wrong.
1347 */
1348 rc = 1;
1349 WARN_ON(1);
1350 }
1351 #endif
1352 if (current->mm == mm)
1353 check_paca_psize(ea, mm, psize, user_region);
1354
1355 goto bail;
1356 }
1357
1358 #ifndef CONFIG_PPC_64K_PAGES
1359 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1360 #else
1361 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1362 pte_val(*(ptep + PTRS_PER_PTE)));
1363 #endif
1364 /* Do actual hashing */
1365 #ifdef CONFIG_PPC_64K_PAGES
1366 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1367 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1368 demote_segment_4k(mm, ea);
1369 psize = MMU_PAGE_4K;
1370 }
1371
1372 /* If this PTE is non-cacheable and we have restrictions on
1373 * using non cacheable large pages, then we switch to 4k
1374 */
1375 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1376 if (user_region) {
1377 demote_segment_4k(mm, ea);
1378 psize = MMU_PAGE_4K;
1379 } else if (ea < VMALLOC_END) {
1380 /*
1381 * some driver did a non-cacheable mapping
1382 * in vmalloc space, so switch vmalloc
1383 * to 4k pages
1384 */
1385 printk(KERN_ALERT "Reducing vmalloc segment "
1386 "to 4kB pages because of "
1387 "non-cacheable mapping\n");
1388 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1389 copro_flush_all_slbs(mm);
1390 }
1391 }
1392
1393 #endif /* CONFIG_PPC_64K_PAGES */
1394
1395 if (current->mm == mm)
1396 check_paca_psize(ea, mm, psize, user_region);
1397
1398 #ifdef CONFIG_PPC_64K_PAGES
1399 if (psize == MMU_PAGE_64K)
1400 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1401 flags, ssize);
1402 else
1403 #endif /* CONFIG_PPC_64K_PAGES */
1404 {
1405 int spp = subpage_protection(mm, ea);
1406 if (access & spp)
1407 rc = -2;
1408 else
1409 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1410 flags, ssize, spp);
1411 }
1412
1413 /* Dump some info in case of hash insertion failure, they should
1414 * never happen so it is really useful to know if/when they do
1415 */
1416 if (rc == -1)
1417 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1418 psize, pte_val(*ptep));
1419 #ifndef CONFIG_PPC_64K_PAGES
1420 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1421 #else
1422 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1423 pte_val(*(ptep + PTRS_PER_PTE)));
1424 #endif
1425 DBG_LOW(" -> rc=%d\n", rc);
1426
1427 bail:
1428 exception_exit(prev_state);
1429 return rc;
1430 }
1431 EXPORT_SYMBOL_GPL(hash_page_mm);
1432
hash_page(unsigned long ea,unsigned long access,unsigned long trap,unsigned long dsisr)1433 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1434 unsigned long dsisr)
1435 {
1436 unsigned long flags = 0;
1437 struct mm_struct *mm = current->mm;
1438
1439 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1440 mm = &init_mm;
1441
1442 if (dsisr & DSISR_NOHPTE)
1443 flags |= HPTE_NOHPTE_UPDATE;
1444
1445 return hash_page_mm(mm, ea, access, trap, flags);
1446 }
1447 EXPORT_SYMBOL_GPL(hash_page);
1448
__hash_page(unsigned long ea,unsigned long msr,unsigned long trap,unsigned long dsisr)1449 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1450 unsigned long dsisr)
1451 {
1452 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1453 unsigned long flags = 0;
1454 struct mm_struct *mm = current->mm;
1455
1456 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1457 mm = &init_mm;
1458
1459 if (dsisr & DSISR_NOHPTE)
1460 flags |= HPTE_NOHPTE_UPDATE;
1461
1462 if (dsisr & DSISR_ISSTORE)
1463 access |= _PAGE_WRITE;
1464 /*
1465 * We set _PAGE_PRIVILEGED only when
1466 * kernel mode access kernel space.
1467 *
1468 * _PAGE_PRIVILEGED is NOT set
1469 * 1) when kernel mode access user space
1470 * 2) user space access kernel space.
1471 */
1472 access |= _PAGE_PRIVILEGED;
1473 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1474 access &= ~_PAGE_PRIVILEGED;
1475
1476 if (trap == 0x400)
1477 access |= _PAGE_EXEC;
1478
1479 return hash_page_mm(mm, ea, access, trap, flags);
1480 }
1481
1482 #ifdef CONFIG_PPC_MM_SLICES
should_hash_preload(struct mm_struct * mm,unsigned long ea)1483 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1484 {
1485 int psize = get_slice_psize(mm, ea);
1486
1487 /* We only prefault standard pages for now */
1488 if (unlikely(psize != mm->context.user_psize))
1489 return false;
1490
1491 /*
1492 * Don't prefault if subpage protection is enabled for the EA.
1493 */
1494 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1495 return false;
1496
1497 return true;
1498 }
1499 #else
should_hash_preload(struct mm_struct * mm,unsigned long ea)1500 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1501 {
1502 return true;
1503 }
1504 #endif
1505
hash_preload(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap)1506 void hash_preload(struct mm_struct *mm, unsigned long ea,
1507 unsigned long access, unsigned long trap)
1508 {
1509 int hugepage_shift;
1510 unsigned long vsid;
1511 pgd_t *pgdir;
1512 pte_t *ptep;
1513 unsigned long flags;
1514 int rc, ssize, update_flags = 0;
1515
1516 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1517
1518 if (!should_hash_preload(mm, ea))
1519 return;
1520
1521 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1522 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1523
1524 /* Get Linux PTE if available */
1525 pgdir = mm->pgd;
1526 if (pgdir == NULL)
1527 return;
1528
1529 /* Get VSID */
1530 ssize = user_segment_size(ea);
1531 vsid = get_vsid(mm->context.id, ea, ssize);
1532 if (!vsid)
1533 return;
1534 /*
1535 * Hash doesn't like irqs. Walking linux page table with irq disabled
1536 * saves us from holding multiple locks.
1537 */
1538 local_irq_save(flags);
1539
1540 /*
1541 * THP pages use update_mmu_cache_pmd. We don't do
1542 * hash preload there. Hence can ignore THP here
1543 */
1544 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1545 if (!ptep)
1546 goto out_exit;
1547
1548 WARN_ON(hugepage_shift);
1549 #ifdef CONFIG_PPC_64K_PAGES
1550 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1551 * a 64K kernel), then we don't preload, hash_page() will take
1552 * care of it once we actually try to access the page.
1553 * That way we don't have to duplicate all of the logic for segment
1554 * page size demotion here
1555 */
1556 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1557 goto out_exit;
1558 #endif /* CONFIG_PPC_64K_PAGES */
1559
1560 /* Is that local to this CPU ? */
1561 if (mm_is_thread_local(mm))
1562 update_flags |= HPTE_LOCAL_UPDATE;
1563
1564 /* Hash it in */
1565 #ifdef CONFIG_PPC_64K_PAGES
1566 if (mm->context.user_psize == MMU_PAGE_64K)
1567 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1568 update_flags, ssize);
1569 else
1570 #endif /* CONFIG_PPC_64K_PAGES */
1571 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1572 ssize, subpage_protection(mm, ea));
1573
1574 /* Dump some info in case of hash insertion failure, they should
1575 * never happen so it is really useful to know if/when they do
1576 */
1577 if (rc == -1)
1578 hash_failure_debug(ea, access, vsid, trap, ssize,
1579 mm->context.user_psize,
1580 mm->context.user_psize,
1581 pte_val(*ptep));
1582 out_exit:
1583 local_irq_restore(flags);
1584 }
1585
1586 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
tm_flush_hash_page(int local)1587 static inline void tm_flush_hash_page(int local)
1588 {
1589 /*
1590 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1591 * page back to a block device w/PIO could pick up transactional data
1592 * (bad!) so we force an abort here. Before the sync the page will be
1593 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1594 * kernel uses a page from userspace without unmapping it first, it may
1595 * see the speculated version.
1596 */
1597 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1598 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1599 tm_enable();
1600 tm_abort(TM_CAUSE_TLBI);
1601 }
1602 }
1603 #else
tm_flush_hash_page(int local)1604 static inline void tm_flush_hash_page(int local)
1605 {
1606 }
1607 #endif
1608
1609 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1610 * do not forget to update the assembly call site !
1611 */
flush_hash_page(unsigned long vpn,real_pte_t pte,int psize,int ssize,unsigned long flags)1612 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1613 unsigned long flags)
1614 {
1615 unsigned long hash, index, shift, hidx, slot;
1616 int local = flags & HPTE_LOCAL_UPDATE;
1617
1618 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1619 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1620 hash = hpt_hash(vpn, shift, ssize);
1621 hidx = __rpte_to_hidx(pte, index);
1622 if (hidx & _PTEIDX_SECONDARY)
1623 hash = ~hash;
1624 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1625 slot += hidx & _PTEIDX_GROUP_IX;
1626 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1627 /*
1628 * We use same base page size and actual psize, because we don't
1629 * use these functions for hugepage
1630 */
1631 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1632 ssize, local);
1633 } pte_iterate_hashed_end();
1634
1635 tm_flush_hash_page(local);
1636 }
1637
1638 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
flush_hash_hugepage(unsigned long vsid,unsigned long addr,pmd_t * pmdp,unsigned int psize,int ssize,unsigned long flags)1639 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1640 pmd_t *pmdp, unsigned int psize, int ssize,
1641 unsigned long flags)
1642 {
1643 int i, max_hpte_count, valid;
1644 unsigned long s_addr;
1645 unsigned char *hpte_slot_array;
1646 unsigned long hidx, shift, vpn, hash, slot;
1647 int local = flags & HPTE_LOCAL_UPDATE;
1648
1649 s_addr = addr & HPAGE_PMD_MASK;
1650 hpte_slot_array = get_hpte_slot_array(pmdp);
1651 /*
1652 * IF we try to do a HUGE PTE update after a withdraw is done.
1653 * we will find the below NULL. This happens when we do
1654 * split_huge_page_pmd
1655 */
1656 if (!hpte_slot_array)
1657 return;
1658
1659 if (mmu_hash_ops.hugepage_invalidate) {
1660 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1661 psize, ssize, local);
1662 goto tm_abort;
1663 }
1664 /*
1665 * No bluk hpte removal support, invalidate each entry
1666 */
1667 shift = mmu_psize_defs[psize].shift;
1668 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1669 for (i = 0; i < max_hpte_count; i++) {
1670 /*
1671 * 8 bits per each hpte entries
1672 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1673 */
1674 valid = hpte_valid(hpte_slot_array, i);
1675 if (!valid)
1676 continue;
1677 hidx = hpte_hash_index(hpte_slot_array, i);
1678
1679 /* get the vpn */
1680 addr = s_addr + (i * (1ul << shift));
1681 vpn = hpt_vpn(addr, vsid, ssize);
1682 hash = hpt_hash(vpn, shift, ssize);
1683 if (hidx & _PTEIDX_SECONDARY)
1684 hash = ~hash;
1685
1686 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1687 slot += hidx & _PTEIDX_GROUP_IX;
1688 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1689 MMU_PAGE_16M, ssize, local);
1690 }
1691 tm_abort:
1692 tm_flush_hash_page(local);
1693 }
1694 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1695
flush_hash_range(unsigned long number,int local)1696 void flush_hash_range(unsigned long number, int local)
1697 {
1698 if (mmu_hash_ops.flush_hash_range)
1699 mmu_hash_ops.flush_hash_range(number, local);
1700 else {
1701 int i;
1702 struct ppc64_tlb_batch *batch =
1703 this_cpu_ptr(&ppc64_tlb_batch);
1704
1705 for (i = 0; i < number; i++)
1706 flush_hash_page(batch->vpn[i], batch->pte[i],
1707 batch->psize, batch->ssize, local);
1708 }
1709 }
1710
1711 /*
1712 * low_hash_fault is called when we the low level hash code failed
1713 * to instert a PTE due to an hypervisor error
1714 */
low_hash_fault(struct pt_regs * regs,unsigned long address,int rc)1715 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1716 {
1717 enum ctx_state prev_state = exception_enter();
1718
1719 if (user_mode(regs)) {
1720 #ifdef CONFIG_PPC_SUBPAGE_PROT
1721 if (rc == -2)
1722 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1723 else
1724 #endif
1725 _exception(SIGBUS, regs, BUS_ADRERR, address);
1726 } else
1727 bad_page_fault(regs, address, SIGBUS);
1728
1729 exception_exit(prev_state);
1730 }
1731
hpte_insert_repeating(unsigned long hash,unsigned long vpn,unsigned long pa,unsigned long rflags,unsigned long vflags,int psize,int ssize)1732 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1733 unsigned long pa, unsigned long rflags,
1734 unsigned long vflags, int psize, int ssize)
1735 {
1736 unsigned long hpte_group;
1737 long slot;
1738
1739 repeat:
1740 hpte_group = ((hash & htab_hash_mask) *
1741 HPTES_PER_GROUP) & ~0x7UL;
1742
1743 /* Insert into the hash table, primary slot */
1744 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1745 psize, psize, ssize);
1746
1747 /* Primary is full, try the secondary */
1748 if (unlikely(slot == -1)) {
1749 hpte_group = ((~hash & htab_hash_mask) *
1750 HPTES_PER_GROUP) & ~0x7UL;
1751 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1752 vflags | HPTE_V_SECONDARY,
1753 psize, psize, ssize);
1754 if (slot == -1) {
1755 if (mftb() & 0x1)
1756 hpte_group = ((hash & htab_hash_mask) *
1757 HPTES_PER_GROUP)&~0x7UL;
1758
1759 mmu_hash_ops.hpte_remove(hpte_group);
1760 goto repeat;
1761 }
1762 }
1763
1764 return slot;
1765 }
1766
1767 #ifdef CONFIG_DEBUG_PAGEALLOC
kernel_map_linear_page(unsigned long vaddr,unsigned long lmi)1768 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1769 {
1770 unsigned long hash;
1771 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1772 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1773 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1774 long ret;
1775
1776 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1777
1778 /* Don't create HPTE entries for bad address */
1779 if (!vsid)
1780 return;
1781
1782 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1783 HPTE_V_BOLTED,
1784 mmu_linear_psize, mmu_kernel_ssize);
1785
1786 BUG_ON (ret < 0);
1787 spin_lock(&linear_map_hash_lock);
1788 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1789 linear_map_hash_slots[lmi] = ret | 0x80;
1790 spin_unlock(&linear_map_hash_lock);
1791 }
1792
kernel_unmap_linear_page(unsigned long vaddr,unsigned long lmi)1793 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1794 {
1795 unsigned long hash, hidx, slot;
1796 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1797 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1798
1799 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1800 spin_lock(&linear_map_hash_lock);
1801 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1802 hidx = linear_map_hash_slots[lmi] & 0x7f;
1803 linear_map_hash_slots[lmi] = 0;
1804 spin_unlock(&linear_map_hash_lock);
1805 if (hidx & _PTEIDX_SECONDARY)
1806 hash = ~hash;
1807 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1808 slot += hidx & _PTEIDX_GROUP_IX;
1809 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1810 mmu_linear_psize,
1811 mmu_kernel_ssize, 0);
1812 }
1813
__kernel_map_pages(struct page * page,int numpages,int enable)1814 void __kernel_map_pages(struct page *page, int numpages, int enable)
1815 {
1816 unsigned long flags, vaddr, lmi;
1817 int i;
1818
1819 local_irq_save(flags);
1820 for (i = 0; i < numpages; i++, page++) {
1821 vaddr = (unsigned long)page_address(page);
1822 lmi = __pa(vaddr) >> PAGE_SHIFT;
1823 if (lmi >= linear_map_hash_count)
1824 continue;
1825 if (enable)
1826 kernel_map_linear_page(vaddr, lmi);
1827 else
1828 kernel_unmap_linear_page(vaddr, lmi);
1829 }
1830 local_irq_restore(flags);
1831 }
1832 #endif /* CONFIG_DEBUG_PAGEALLOC */
1833
hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)1834 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1835 phys_addr_t first_memblock_size)
1836 {
1837 /* We don't currently support the first MEMBLOCK not mapping 0
1838 * physical on those processors
1839 */
1840 BUG_ON(first_memblock_base != 0);
1841
1842 /* On LPAR systems, the first entry is our RMA region,
1843 * non-LPAR 64-bit hash MMU systems don't have a limitation
1844 * on real mode access, but using the first entry works well
1845 * enough. We also clamp it to 1G to avoid some funky things
1846 * such as RTAS bugs etc...
1847 */
1848 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1849
1850 /* Finally limit subsequent allocations */
1851 memblock_set_current_limit(ppc64_rma_size);
1852 }
1853
1854 #ifdef CONFIG_DEBUG_FS
1855
hpt_order_get(void * data,u64 * val)1856 static int hpt_order_get(void *data, u64 *val)
1857 {
1858 *val = ppc64_pft_size;
1859 return 0;
1860 }
1861
hpt_order_set(void * data,u64 val)1862 static int hpt_order_set(void *data, u64 val)
1863 {
1864 int ret;
1865
1866 if (!mmu_hash_ops.resize_hpt)
1867 return -ENODEV;
1868
1869 cpus_read_lock();
1870 ret = mmu_hash_ops.resize_hpt(val);
1871 cpus_read_unlock();
1872
1873 return ret;
1874 }
1875
1876 DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1877
hash64_debugfs(void)1878 static int __init hash64_debugfs(void)
1879 {
1880 if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root,
1881 NULL, &fops_hpt_order)) {
1882 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1883 }
1884
1885 return 0;
1886 }
1887 machine_device_initcall(pseries, hash64_debugfs);
1888 #endif /* CONFIG_DEBUG_FS */
1889