1 /*
2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/pci.h>
49 #include <linux/io.h>
50 #include <linux/delay.h>
51 #include <linux/vmalloc.h>
52 #include <linux/aer.h>
53 #include <linux/module.h>
54
55 #include "hfi.h"
56 #include "chip_registers.h"
57 #include "aspm.h"
58
59 /* link speed vector for Gen3 speed - not in Linux headers */
60 #define GEN1_SPEED_VECTOR 0x1
61 #define GEN2_SPEED_VECTOR 0x2
62 #define GEN3_SPEED_VECTOR 0x3
63
64 /*
65 * This file contains PCIe utility routines.
66 */
67
68 /*
69 * Code to adjust PCIe capabilities.
70 */
71 static void tune_pcie_caps(struct hfi1_devdata *);
72
73 /*
74 * Do all the common PCIe setup and initialization.
75 * devdata is not yet allocated, and is not allocated until after this
76 * routine returns success. Therefore dd_dev_err() can't be used for error
77 * printing.
78 */
hfi1_pcie_init(struct pci_dev * pdev,const struct pci_device_id * ent)79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
80 {
81 int ret;
82
83 ret = pci_enable_device(pdev);
84 if (ret) {
85 /*
86 * This can happen (in theory) iff:
87 * We did a chip reset, and then failed to reprogram the
88 * BAR, or the chip reset due to an internal error. We then
89 * unloaded the driver and reloaded it.
90 *
91 * Both reset cases set the BAR back to initial state. For
92 * the latter case, the AER sticky error bit at offset 0x718
93 * should be set, but the Linux kernel doesn't yet know
94 * about that, it appears. If the original BAR was retained
95 * in the kernel data structures, this may be OK.
96 */
97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n",
98 -ret);
99 goto done;
100 }
101
102 ret = pci_request_regions(pdev, DRIVER_NAME);
103 if (ret) {
104 hfi1_early_err(&pdev->dev,
105 "pci_request_regions fails: err %d\n", -ret);
106 goto bail;
107 }
108
109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
110 if (ret) {
111 /*
112 * If the 64 bit setup fails, try 32 bit. Some systems
113 * do not setup 64 bit maps on systems with 2GB or less
114 * memory installed.
115 */
116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
117 if (ret) {
118 hfi1_early_err(&pdev->dev,
119 "Unable to set DMA mask: %d\n", ret);
120 goto bail;
121 }
122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
123 } else {
124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
125 }
126 if (ret) {
127 hfi1_early_err(&pdev->dev,
128 "Unable to set DMA consistent mask: %d\n", ret);
129 goto bail;
130 }
131
132 pci_set_master(pdev);
133 (void)pci_enable_pcie_error_reporting(pdev);
134 goto done;
135
136 bail:
137 hfi1_pcie_cleanup(pdev);
138 done:
139 return ret;
140 }
141
142 /*
143 * Clean what was done in hfi1_pcie_init()
144 */
hfi1_pcie_cleanup(struct pci_dev * pdev)145 void hfi1_pcie_cleanup(struct pci_dev *pdev)
146 {
147 pci_disable_device(pdev);
148 /*
149 * Release regions should be called after the disable. OK to
150 * call if request regions has not been called or failed.
151 */
152 pci_release_regions(pdev);
153 }
154
155 /*
156 * Do remaining PCIe setup, once dd is allocated, and save away
157 * fields required to re-initialize after a chip reset, or for
158 * various other purposes
159 */
hfi1_pcie_ddinit(struct hfi1_devdata * dd,struct pci_dev * pdev)160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
161 {
162 unsigned long len;
163 resource_size_t addr;
164 int ret = 0;
165
166 addr = pci_resource_start(pdev, 0);
167 len = pci_resource_len(pdev, 0);
168
169 /*
170 * The TXE PIO buffers are at the tail end of the chip space.
171 * Cut them off and map them separately.
172 */
173
174 /* sanity check vs expectations */
175 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) {
176 dd_dev_err(dd, "chip PIO range does not match\n");
177 return -EINVAL;
178 }
179
180 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY);
181 if (!dd->kregbase1) {
182 dd_dev_err(dd, "UC mapping of kregbase1 failed\n");
183 return -ENOMEM;
184 }
185 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY);
186 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT);
187 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count);
188 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8;
189
190 dd->kregbase2 = ioremap_nocache(
191 addr + dd->base2_start,
192 TXE_PIO_SEND - dd->base2_start);
193 if (!dd->kregbase2) {
194 dd_dev_err(dd, "UC mapping of kregbase2 failed\n");
195 goto nomem;
196 }
197 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2,
198 TXE_PIO_SEND - dd->base2_start);
199
200 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE);
201 if (!dd->piobase) {
202 dd_dev_err(dd, "WC mapping of send buffers failed\n");
203 goto nomem;
204 }
205 dd_dev_info(dd, "WC piobase: %p\n for %x", dd->piobase, TXE_PIO_SIZE);
206
207 dd->physaddr = addr; /* used for io_remap, etc. */
208
209 /*
210 * Map the chip's RcvArray as write-combining to allow us
211 * to write an entire cacheline worth of entries in one shot.
212 */
213 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY,
214 dd->chip_rcv_array_count * 8);
215 if (!dd->rcvarray_wc) {
216 dd_dev_err(dd, "WC mapping of receive array failed\n");
217 goto nomem;
218 }
219 dd_dev_info(dd, "WC RcvArray: %p for %x\n",
220 dd->rcvarray_wc, dd->chip_rcv_array_count * 8);
221
222 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */
223 return 0;
224 nomem:
225 ret = -ENOMEM;
226 hfi1_pcie_ddcleanup(dd);
227 return ret;
228 }
229
230 /*
231 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
232 * to releasing the dd memory.
233 * Void because all of the core pcie cleanup functions are void.
234 */
hfi1_pcie_ddcleanup(struct hfi1_devdata * dd)235 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
236 {
237 dd->flags &= ~HFI1_PRESENT;
238 if (dd->kregbase1)
239 iounmap(dd->kregbase1);
240 dd->kregbase1 = NULL;
241 if (dd->kregbase2)
242 iounmap(dd->kregbase2);
243 dd->kregbase2 = NULL;
244 if (dd->rcvarray_wc)
245 iounmap(dd->rcvarray_wc);
246 dd->rcvarray_wc = NULL;
247 if (dd->piobase)
248 iounmap(dd->piobase);
249 dd->piobase = NULL;
250 }
251
252 /* return the PCIe link speed from the given link status */
extract_speed(u16 linkstat)253 static u32 extract_speed(u16 linkstat)
254 {
255 u32 speed;
256
257 switch (linkstat & PCI_EXP_LNKSTA_CLS) {
258 default: /* not defined, assume Gen1 */
259 case PCI_EXP_LNKSTA_CLS_2_5GB:
260 speed = 2500; /* Gen 1, 2.5GHz */
261 break;
262 case PCI_EXP_LNKSTA_CLS_5_0GB:
263 speed = 5000; /* Gen 2, 5GHz */
264 break;
265 case GEN3_SPEED_VECTOR:
266 speed = 8000; /* Gen 3, 8GHz */
267 break;
268 }
269 return speed;
270 }
271
272 /* return the PCIe link speed from the given link status */
extract_width(u16 linkstat)273 static u32 extract_width(u16 linkstat)
274 {
275 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
276 }
277
278 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
update_lbus_info(struct hfi1_devdata * dd)279 static void update_lbus_info(struct hfi1_devdata *dd)
280 {
281 u16 linkstat;
282 int ret;
283
284 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
285 if (ret) {
286 dd_dev_err(dd, "Unable to read from PCI config\n");
287 return;
288 }
289
290 dd->lbus_width = extract_width(linkstat);
291 dd->lbus_speed = extract_speed(linkstat);
292 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
293 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width);
294 }
295
296 /*
297 * Read in the current PCIe link width and speed. Find if the link is
298 * Gen3 capable.
299 */
pcie_speeds(struct hfi1_devdata * dd)300 int pcie_speeds(struct hfi1_devdata *dd)
301 {
302 u32 linkcap;
303 struct pci_dev *parent = dd->pcidev->bus->self;
304 int ret;
305
306 if (!pci_is_pcie(dd->pcidev)) {
307 dd_dev_err(dd, "Can't find PCI Express capability!\n");
308 return -EINVAL;
309 }
310
311 /* find if our max speed is Gen3 and parent supports Gen3 speeds */
312 dd->link_gen3_capable = 1;
313
314 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap);
315 if (ret) {
316 dd_dev_err(dd, "Unable to read from PCI config\n");
317 return ret;
318 }
319
320 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) {
321 dd_dev_info(dd,
322 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
323 linkcap & PCI_EXP_LNKCAP_SLS);
324 dd->link_gen3_capable = 0;
325 }
326
327 /*
328 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
329 */
330 if (parent &&
331 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT ||
332 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) {
333 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
334 dd->link_gen3_capable = 0;
335 }
336
337 /* obtain the link width and current speed */
338 update_lbus_info(dd);
339
340 dd_dev_info(dd, "%s\n", dd->lbus_info);
341
342 return 0;
343 }
344
345 /*
346 * Returns:
347 * - actual number of interrupts allocated or
348 * - 0 if fell back to INTx.
349 * - error
350 */
request_msix(struct hfi1_devdata * dd,u32 msireq)351 int request_msix(struct hfi1_devdata *dd, u32 msireq)
352 {
353 int nvec;
354
355 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq,
356 PCI_IRQ_MSIX | PCI_IRQ_LEGACY);
357 if (nvec < 0) {
358 dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", nvec);
359 return nvec;
360 }
361
362 tune_pcie_caps(dd);
363
364 /* check for legacy IRQ */
365 if (nvec == 1 && !dd->pcidev->msix_enabled)
366 return 0;
367
368 return nvec;
369 }
370
371 /* restore command and BARs after a reset has wiped them out */
restore_pci_variables(struct hfi1_devdata * dd)372 int restore_pci_variables(struct hfi1_devdata *dd)
373 {
374 int ret = 0;
375
376 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command);
377 if (ret)
378 goto error;
379
380 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
381 dd->pcibar0);
382 if (ret)
383 goto error;
384
385 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
386 dd->pcibar1);
387 if (ret)
388 goto error;
389
390 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
391 if (ret)
392 goto error;
393
394 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL,
395 dd->pcie_devctl);
396 if (ret)
397 goto error;
398
399 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL,
400 dd->pcie_lnkctl);
401 if (ret)
402 goto error;
403
404 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2,
405 dd->pcie_devctl2);
406 if (ret)
407 goto error;
408
409 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0);
410 if (ret)
411 goto error;
412
413 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
414 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
415 dd->pci_tph2);
416 if (ret)
417 goto error;
418 }
419 return 0;
420
421 error:
422 dd_dev_err(dd, "Unable to write to PCI config\n");
423 return ret;
424 }
425
426 /* Save BARs and command to rewrite after device reset */
save_pci_variables(struct hfi1_devdata * dd)427 int save_pci_variables(struct hfi1_devdata *dd)
428 {
429 int ret = 0;
430
431 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
432 &dd->pcibar0);
433 if (ret)
434 goto error;
435
436 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
437 &dd->pcibar1);
438 if (ret)
439 goto error;
440
441 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
442 if (ret)
443 goto error;
444
445 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
446 if (ret)
447 goto error;
448
449 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
450 &dd->pcie_devctl);
451 if (ret)
452 goto error;
453
454 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
455 &dd->pcie_lnkctl);
456 if (ret)
457 goto error;
458
459 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
460 &dd->pcie_devctl2);
461 if (ret)
462 goto error;
463
464 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
465 if (ret)
466 goto error;
467
468 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
469 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
470 &dd->pci_tph2);
471 if (ret)
472 goto error;
473 }
474 return 0;
475
476 error:
477 dd_dev_err(dd, "Unable to read from PCI config\n");
478 return ret;
479 }
480
481 /*
482 * BIOS may not set PCIe bus-utilization parameters for best performance.
483 * Check and optionally adjust them to maximize our throughput.
484 */
485 static int hfi1_pcie_caps;
486 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO);
487 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
488
489 uint aspm_mode = ASPM_MODE_DISABLED;
490 module_param_named(aspm, aspm_mode, uint, S_IRUGO);
491 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic");
492
tune_pcie_caps(struct hfi1_devdata * dd)493 static void tune_pcie_caps(struct hfi1_devdata *dd)
494 {
495 struct pci_dev *parent;
496 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
497 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl;
498 int ret;
499
500 /*
501 * Turn on extended tags in DevCtl in case the BIOS has turned it off
502 * to improve WFR SDMA bandwidth
503 */
504 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
505 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
506 dd_dev_info(dd, "Enabling PCIe extended tags\n");
507 ectl |= PCI_EXP_DEVCTL_EXT_TAG;
508 ret = pcie_capability_write_word(dd->pcidev,
509 PCI_EXP_DEVCTL, ectl);
510 if (ret)
511 dd_dev_info(dd, "Unable to write to PCI config\n");
512 }
513 /* Find out supported and configured values for parent (root) */
514 parent = dd->pcidev->bus->self;
515 /*
516 * The driver cannot perform the tuning if it does not have
517 * access to the upstream component.
518 */
519 if (!parent) {
520 dd_dev_info(dd, "Parent not found\n");
521 return;
522 }
523 if (!pci_is_root_bus(parent->bus)) {
524 dd_dev_info(dd, "Parent not root\n");
525 return;
526 }
527 if (!pci_is_pcie(parent)) {
528 dd_dev_info(dd, "Parent is not PCI Express capable\n");
529 return;
530 }
531 if (!pci_is_pcie(dd->pcidev)) {
532 dd_dev_info(dd, "PCI device is not PCI Express capable\n");
533 return;
534 }
535 rc_mpss = parent->pcie_mpss;
536 rc_mps = ffs(pcie_get_mps(parent)) - 8;
537 /* Find out supported and configured values for endpoint (us) */
538 ep_mpss = dd->pcidev->pcie_mpss;
539 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
540
541 /* Find max payload supported by root, endpoint */
542 if (rc_mpss > ep_mpss)
543 rc_mpss = ep_mpss;
544
545 /* If Supported greater than limit in module param, limit it */
546 if (rc_mpss > (hfi1_pcie_caps & 7))
547 rc_mpss = hfi1_pcie_caps & 7;
548 /* If less than (allowed, supported), bump root payload */
549 if (rc_mpss > rc_mps) {
550 rc_mps = rc_mpss;
551 pcie_set_mps(parent, 128 << rc_mps);
552 }
553 /* If less than (allowed, supported), bump endpoint payload */
554 if (rc_mpss > ep_mps) {
555 ep_mps = rc_mpss;
556 pcie_set_mps(dd->pcidev, 128 << ep_mps);
557 }
558
559 /*
560 * Now the Read Request size.
561 * No field for max supported, but PCIe spec limits it to 4096,
562 * which is code '5' (log2(4096) - 7)
563 */
564 max_mrrs = 5;
565 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7))
566 max_mrrs = (hfi1_pcie_caps >> 4) & 7;
567
568 max_mrrs = 128 << max_mrrs;
569 rc_mrrs = pcie_get_readrq(parent);
570 ep_mrrs = pcie_get_readrq(dd->pcidev);
571
572 if (max_mrrs > rc_mrrs) {
573 rc_mrrs = max_mrrs;
574 pcie_set_readrq(parent, rc_mrrs);
575 }
576 if (max_mrrs > ep_mrrs) {
577 ep_mrrs = max_mrrs;
578 pcie_set_readrq(dd->pcidev, ep_mrrs);
579 }
580 }
581
582 /* End of PCIe capability tuning */
583
584 /*
585 * From here through hfi1_pci_err_handler definition is invoked via
586 * PCI error infrastructure, registered via pci
587 */
588 static pci_ers_result_t
pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)589 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
590 {
591 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
592 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
593
594 switch (state) {
595 case pci_channel_io_normal:
596 dd_dev_info(dd, "State Normal, ignoring\n");
597 break;
598
599 case pci_channel_io_frozen:
600 dd_dev_info(dd, "State Frozen, requesting reset\n");
601 pci_disable_device(pdev);
602 ret = PCI_ERS_RESULT_NEED_RESET;
603 break;
604
605 case pci_channel_io_perm_failure:
606 if (dd) {
607 dd_dev_info(dd, "State Permanent Failure, disabling\n");
608 /* no more register accesses! */
609 dd->flags &= ~HFI1_PRESENT;
610 hfi1_disable_after_error(dd);
611 }
612 /* else early, or other problem */
613 ret = PCI_ERS_RESULT_DISCONNECT;
614 break;
615
616 default: /* shouldn't happen */
617 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n",
618 state);
619 break;
620 }
621 return ret;
622 }
623
624 static pci_ers_result_t
pci_mmio_enabled(struct pci_dev * pdev)625 pci_mmio_enabled(struct pci_dev *pdev)
626 {
627 u64 words = 0U;
628 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
629 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
630
631 if (dd && dd->pport) {
632 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL);
633 if (words == ~0ULL)
634 ret = PCI_ERS_RESULT_NEED_RESET;
635 dd_dev_info(dd,
636 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n",
637 words, ret);
638 }
639 return ret;
640 }
641
642 static pci_ers_result_t
pci_slot_reset(struct pci_dev * pdev)643 pci_slot_reset(struct pci_dev *pdev)
644 {
645 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
646
647 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n");
648 return PCI_ERS_RESULT_CAN_RECOVER;
649 }
650
651 static void
pci_resume(struct pci_dev * pdev)652 pci_resume(struct pci_dev *pdev)
653 {
654 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
655
656 dd_dev_info(dd, "HFI1 resume function called\n");
657 pci_cleanup_aer_uncorrect_error_status(pdev);
658 /*
659 * Running jobs will fail, since it's asynchronous
660 * unlike sysfs-requested reset. Better than
661 * doing nothing.
662 */
663 hfi1_init(dd, 1); /* same as re-init after reset */
664 }
665
666 const struct pci_error_handlers hfi1_pci_err_handler = {
667 .error_detected = pci_error_detected,
668 .mmio_enabled = pci_mmio_enabled,
669 .slot_reset = pci_slot_reset,
670 .resume = pci_resume,
671 };
672
673 /*============================================================================*/
674 /* PCIe Gen3 support */
675
676 /*
677 * This code is separated out because it is expected to be removed in the
678 * final shipping product. If not, then it will be revisited and items
679 * will be moved to more standard locations.
680 */
681
682 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
683 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */
684 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */
685 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */
686
687 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
688 #define DL_ERR_NONE 0x0 /* no error */
689 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */
690 /* or response data */
691 #define DL_ERR_DISABLED 0x2 /* hfi disabled */
692 #define DL_ERR_SECURITY 0x3 /* security check failed */
693 #define DL_ERR_SBUS 0x4 /* SBus status error */
694 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/
695
696 /* gasket block secondary bus reset delay */
697 #define SBR_DELAY_US 200000 /* 200ms */
698
699 /* mask for PCIe capability register lnkctl2 target link speed */
700 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf
701
702 static uint pcie_target = 3;
703 module_param(pcie_target, uint, S_IRUGO);
704 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
705
706 static uint pcie_force;
707 module_param(pcie_force, uint, S_IRUGO);
708 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed");
709
710 static uint pcie_retry = 5;
711 module_param(pcie_retry, uint, S_IRUGO);
712 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed");
713
714 #define UNSET_PSET 255
715 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
716 #define DEFAULT_MCP_PSET 6 /* MCP HFI */
717 static uint pcie_pset = UNSET_PSET;
718 module_param(pcie_pset, uint, S_IRUGO);
719 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
720
721 static uint pcie_ctle = 3; /* discrete on, integrated on */
722 module_param(pcie_ctle, uint, S_IRUGO);
723 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");
724
725 /* equalization columns */
726 #define PREC 0
727 #define ATTN 1
728 #define POST 2
729
730 /* discrete silicon preliminary equalization values */
731 static const u8 discrete_preliminary_eq[11][3] = {
732 /* prec attn post */
733 { 0x00, 0x00, 0x12 }, /* p0 */
734 { 0x00, 0x00, 0x0c }, /* p1 */
735 { 0x00, 0x00, 0x0f }, /* p2 */
736 { 0x00, 0x00, 0x09 }, /* p3 */
737 { 0x00, 0x00, 0x00 }, /* p4 */
738 { 0x06, 0x00, 0x00 }, /* p5 */
739 { 0x09, 0x00, 0x00 }, /* p6 */
740 { 0x06, 0x00, 0x0f }, /* p7 */
741 { 0x09, 0x00, 0x09 }, /* p8 */
742 { 0x0c, 0x00, 0x00 }, /* p9 */
743 { 0x00, 0x00, 0x18 }, /* p10 */
744 };
745
746 /* integrated silicon preliminary equalization values */
747 static const u8 integrated_preliminary_eq[11][3] = {
748 /* prec attn post */
749 { 0x00, 0x1e, 0x07 }, /* p0 */
750 { 0x00, 0x1e, 0x05 }, /* p1 */
751 { 0x00, 0x1e, 0x06 }, /* p2 */
752 { 0x00, 0x1e, 0x04 }, /* p3 */
753 { 0x00, 0x1e, 0x00 }, /* p4 */
754 { 0x03, 0x1e, 0x00 }, /* p5 */
755 { 0x04, 0x1e, 0x00 }, /* p6 */
756 { 0x03, 0x1e, 0x06 }, /* p7 */
757 { 0x03, 0x1e, 0x04 }, /* p8 */
758 { 0x05, 0x1e, 0x00 }, /* p9 */
759 { 0x00, 0x1e, 0x0a }, /* p10 */
760 };
761
762 static const u8 discrete_ctle_tunings[11][4] = {
763 /* DC LF HF BW */
764 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */
765 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */
766 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */
767 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */
768 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */
769 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */
770 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */
771 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
772 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */
773 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */
774 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */
775 };
776
777 static const u8 integrated_ctle_tunings[11][4] = {
778 /* DC LF HF BW */
779 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */
780 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */
781 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */
782 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */
783 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */
784 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */
785 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */
786 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
787 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */
788 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */
789 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */
790 };
791
792 /* helper to format the value to write to hardware */
793 #define eq_value(pre, curr, post) \
794 ((((u32)(pre)) << \
795 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \
796 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \
797 | (((u32)(post)) << \
798 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT))
799
800 /*
801 * Load the given EQ preset table into the PCIe hardware.
802 */
load_eq_table(struct hfi1_devdata * dd,const u8 eq[11][3],u8 fs,u8 div)803 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
804 u8 div)
805 {
806 struct pci_dev *pdev = dd->pcidev;
807 u32 hit_error = 0;
808 u32 violation;
809 u32 i;
810 u8 c_minus1, c0, c_plus1;
811 int ret;
812
813 for (i = 0; i < 11; i++) {
814 /* set index */
815 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i);
816 /* write the value */
817 c_minus1 = eq[i][PREC] / div;
818 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div);
819 c_plus1 = eq[i][POST] / div;
820 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102,
821 eq_value(c_minus1, c0, c_plus1));
822 /* check if these coefficients violate EQ rules */
823 ret = pci_read_config_dword(dd->pcidev,
824 PCIE_CFG_REG_PL105, &violation);
825 if (ret) {
826 dd_dev_err(dd, "Unable to read from PCI config\n");
827 hit_error = 1;
828 break;
829 }
830
831 if (violation
832 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){
833 if (hit_error == 0) {
834 dd_dev_err(dd,
835 "Gen3 EQ Table Coefficient rule violations\n");
836 dd_dev_err(dd, " prec attn post\n");
837 }
838 dd_dev_err(dd, " p%02d: %02x %02x %02x\n",
839 i, (u32)eq[i][0], (u32)eq[i][1],
840 (u32)eq[i][2]);
841 dd_dev_err(dd, " %02x %02x %02x\n",
842 (u32)c_minus1, (u32)c0, (u32)c_plus1);
843 hit_error = 1;
844 }
845 }
846 if (hit_error)
847 return -EINVAL;
848 return 0;
849 }
850
851 /*
852 * Steps to be done after the PCIe firmware is downloaded and
853 * before the SBR for the Pcie Gen3.
854 * The SBus resource is already being held.
855 */
pcie_post_steps(struct hfi1_devdata * dd)856 static void pcie_post_steps(struct hfi1_devdata *dd)
857 {
858 int i;
859
860 set_sbus_fast_mode(dd);
861 /*
862 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1.
863 * This avoids a spurious framing error that can otherwise be
864 * generated by the MAC layer.
865 *
866 * Use individual addresses since no broadcast is set up.
867 */
868 for (i = 0; i < NUM_PCIE_SERDES; i++) {
869 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i],
870 0x03, WRITE_SBUS_RECEIVER, 0x00022132);
871 }
872
873 clear_sbus_fast_mode(dd);
874 }
875
876 /*
877 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
878 *
879 * Based on pci_parent_bus_reset() which is not exported by the
880 * kernel core.
881 */
trigger_sbr(struct hfi1_devdata * dd)882 static int trigger_sbr(struct hfi1_devdata *dd)
883 {
884 struct pci_dev *dev = dd->pcidev;
885 struct pci_dev *pdev;
886
887 /* need a parent */
888 if (!dev->bus->self) {
889 dd_dev_err(dd, "%s: no parent device\n", __func__);
890 return -ENOTTY;
891 }
892
893 /* should not be anyone else on the bus */
894 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
895 if (pdev != dev) {
896 dd_dev_err(dd,
897 "%s: another device is on the same bus\n",
898 __func__);
899 return -ENOTTY;
900 }
901
902 /*
903 * A secondary bus reset (SBR) issues a hot reset to our device.
904 * The following routine does a 1s wait after the reset is dropped
905 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
906 * Conventional Reset, paragraph 3, line 35 also says that a 1s
907 * delay after a reset is required. Per spec requirements,
908 * the link is either working or not after that point.
909 */
910 pci_reset_bridge_secondary_bus(dev->bus->self);
911
912 return 0;
913 }
914
915 /*
916 * Write the given gasket interrupt register.
917 */
write_gasket_interrupt(struct hfi1_devdata * dd,int index,u16 code,u16 data)918 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
919 u16 code, u16 data)
920 {
921 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
922 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) |
923 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
924 }
925
926 /*
927 * Tell the gasket logic how to react to the reset.
928 */
arm_gasket_logic(struct hfi1_devdata * dd)929 static void arm_gasket_logic(struct hfi1_devdata *dd)
930 {
931 u64 reg;
932
933 reg = (((u64)1 << dd->hfi1_id) <<
934 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) |
935 ((u64)pcie_serdes_broadcast[dd->hfi1_id] <<
936 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT |
937 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK |
938 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) <<
939 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT);
940 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
941 /* read back to push the write */
942 read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
943 }
944
945 /*
946 * CCE_PCIE_CTRL long name helpers
947 * We redefine these shorter macros to use in the code while leaving
948 * chip_registers.h to be autogenerated from the hardware spec.
949 */
950 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK
951 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT
952 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK
953 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT
954 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT
955 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT
956 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK
957 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT
958 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK
959 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT
960
961 /*
962 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
963 */
write_xmt_margin(struct hfi1_devdata * dd,const char * fname)964 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
965 {
966 u64 pcie_ctrl;
967 u64 xmt_margin;
968 u64 xmt_margin_oe;
969 u64 lane_delay;
970 u64 lane_bundle;
971
972 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL);
973
974 /*
975 * For Discrete, use full-swing.
976 * - PCIe TX defaults to full-swing.
977 * Leave this register as default.
978 * For Integrated, use half-swing
979 * - Copy xmt_margin and xmt_margin_oe
980 * from Gen1/Gen2 to Gen3.
981 */
982 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */
983 /* extract initial fields */
984 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT)
985 & MARGIN_GEN1_GEN2_MASK;
986 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT)
987 & MARGIN_G1_G2_OVERWRITE_MASK;
988 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK;
989 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT)
990 & LANE_BUNDLE_MASK;
991
992 /*
993 * For A0, EFUSE values are not set. Override with the
994 * correct values.
995 */
996 if (is_ax(dd)) {
997 /*
998 * xmt_margin and OverwiteEnabel should be the
999 * same for Gen1/Gen2 and Gen3
1000 */
1001 xmt_margin = 0x5;
1002 xmt_margin_oe = 0x1;
1003 lane_delay = 0xF; /* Delay 240ns. */
1004 lane_bundle = 0x0; /* Set to 1 lane. */
1005 }
1006
1007 /* overwrite existing values */
1008 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT)
1009 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT)
1010 | (xmt_margin << MARGIN_SHIFT)
1011 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT)
1012 | (lane_delay << LANE_DELAY_SHIFT)
1013 | (lane_bundle << LANE_BUNDLE_SHIFT);
1014
1015 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
1016 }
1017
1018 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n",
1019 fname, pcie_ctrl);
1020 }
1021
1022 /*
1023 * Do all the steps needed to transition the PCIe link to Gen3 speed.
1024 */
do_pcie_gen3_transition(struct hfi1_devdata * dd)1025 int do_pcie_gen3_transition(struct hfi1_devdata *dd)
1026 {
1027 struct pci_dev *parent = dd->pcidev->bus->self;
1028 u64 fw_ctrl;
1029 u64 reg, therm;
1030 u32 reg32, fs, lf;
1031 u32 status, err;
1032 int ret;
1033 int do_retry, retry_count = 0;
1034 int intnum = 0;
1035 uint default_pset;
1036 u16 target_vector, target_speed;
1037 u16 lnkctl2, vendor;
1038 u8 div;
1039 const u8 (*eq)[3];
1040 const u8 (*ctle_tunings)[4];
1041 uint static_ctle_mode;
1042 int return_error = 0;
1043
1044 /* PCIe Gen3 is for the ASIC only */
1045 if (dd->icode != ICODE_RTL_SILICON)
1046 return 0;
1047
1048 if (pcie_target == 1) { /* target Gen1 */
1049 target_vector = GEN1_SPEED_VECTOR;
1050 target_speed = 2500;
1051 } else if (pcie_target == 2) { /* target Gen2 */
1052 target_vector = GEN2_SPEED_VECTOR;
1053 target_speed = 5000;
1054 } else if (pcie_target == 3) { /* target Gen3 */
1055 target_vector = GEN3_SPEED_VECTOR;
1056 target_speed = 8000;
1057 } else {
1058 /* off or invalid target - skip */
1059 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__);
1060 return 0;
1061 }
1062
1063 /* if already at target speed, done (unless forced) */
1064 if (dd->lbus_speed == target_speed) {
1065 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__,
1066 pcie_target,
1067 pcie_force ? "re-doing anyway" : "skipping");
1068 if (!pcie_force)
1069 return 0;
1070 }
1071
1072 /*
1073 * The driver cannot do the transition if it has no access to the
1074 * upstream component
1075 */
1076 if (!parent) {
1077 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n",
1078 __func__);
1079 return 0;
1080 }
1081
1082 /*
1083 * Do the Gen3 transition. Steps are those of the PCIe Gen3
1084 * recipe.
1085 */
1086
1087 /* step 1: pcie link working in gen1/gen2 */
1088
1089 /* step 2: if either side is not capable of Gen3, done */
1090 if (pcie_target == 3 && !dd->link_gen3_capable) {
1091 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");
1092 ret = -ENOSYS;
1093 goto done_no_mutex;
1094 }
1095
1096 /* hold the SBus resource across the firmware download and SBR */
1097 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1098 if (ret) {
1099 dd_dev_err(dd, "%s: unable to acquire SBus resource\n",
1100 __func__);
1101 return ret;
1102 }
1103
1104 /* make sure thermal polling is not causing interrupts */
1105 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN);
1106 if (therm) {
1107 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
1108 msleep(100);
1109 dd_dev_info(dd, "%s: Disabled therm polling\n",
1110 __func__);
1111 }
1112
1113 retry:
1114 /* the SBus download will reset the spico for thermal */
1115
1116 /* step 3: download SBus Master firmware */
1117 /* step 4: download PCIe Gen3 SerDes firmware */
1118 dd_dev_info(dd, "%s: downloading firmware\n", __func__);
1119 ret = load_pcie_firmware(dd);
1120 if (ret) {
1121 /* do not proceed if the firmware cannot be downloaded */
1122 return_error = 1;
1123 goto done;
1124 }
1125
1126 /* step 5: set up device parameter settings */
1127 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__);
1128
1129 /*
1130 * PcieCfgSpcie1 - Link Control 3
1131 * Leave at reset value. No need to set PerfEq - link equalization
1132 * will be performed automatically after the SBR when the target
1133 * speed is 8GT/s.
1134 */
1135
1136 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */
1137 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff);
1138
1139 /* step 5a: Set Synopsys Port Logic registers */
1140
1141 /*
1142 * PcieCfgRegPl2 - Port Force Link
1143 *
1144 * Set the low power field to 0x10 to avoid unnecessary power
1145 * management messages. All other fields are zero.
1146 */
1147 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT;
1148 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32);
1149
1150 /*
1151 * PcieCfgRegPl100 - Gen3 Control
1152 *
1153 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl
1154 * turn on PcieCfgRegPl100.EqEieosCnt
1155 * Everything else zero.
1156 */
1157 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK;
1158 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32);
1159
1160 /*
1161 * PcieCfgRegPl101 - Gen3 EQ FS and LF
1162 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping
1163 * PcieCfgRegPl103 - Gen3 EQ Preset Index
1164 * PcieCfgRegPl105 - Gen3 EQ Status
1165 *
1166 * Give initial EQ settings.
1167 */
1168 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */
1169 /* 1000mV, FS=24, LF = 8 */
1170 fs = 24;
1171 lf = 8;
1172 div = 3;
1173 eq = discrete_preliminary_eq;
1174 default_pset = DEFAULT_DISCRETE_PSET;
1175 ctle_tunings = discrete_ctle_tunings;
1176 /* bit 0 - discrete on/off */
1177 static_ctle_mode = pcie_ctle & 0x1;
1178 } else {
1179 /* 400mV, FS=29, LF = 9 */
1180 fs = 29;
1181 lf = 9;
1182 div = 1;
1183 eq = integrated_preliminary_eq;
1184 default_pset = DEFAULT_MCP_PSET;
1185 ctle_tunings = integrated_ctle_tunings;
1186 /* bit 1 - integrated on/off */
1187 static_ctle_mode = (pcie_ctle >> 1) & 0x1;
1188 }
1189 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
1190 (fs <<
1191 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) |
1192 (lf <<
1193 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
1194 ret = load_eq_table(dd, eq, fs, div);
1195 if (ret)
1196 goto done;
1197
1198 /*
1199 * PcieCfgRegPl106 - Gen3 EQ Control
1200 *
1201 * Set Gen3EqPsetReqVec, leave other fields 0.
1202 */
1203 if (pcie_pset == UNSET_PSET)
1204 pcie_pset = default_pset;
1205 if (pcie_pset > 10) { /* valid range is 0-10, inclusive */
1206 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",
1207 __func__, pcie_pset, default_pset);
1208 pcie_pset = default_pset;
1209 }
1210 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset);
1211 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106,
1212 ((1 << pcie_pset) <<
1213 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) |
1214 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK |
1215 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
1216
1217 /*
1218 * step 5b: Do post firmware download steps via SBus
1219 */
1220 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__);
1221 pcie_post_steps(dd);
1222
1223 /*
1224 * step 5c: Program gasket interrupts
1225 */
1226 /* set the Rx Bit Rate to REFCLK ratio */
1227 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050);
1228 /* disable pCal for PCIe Gen3 RX equalization */
1229 /* select adaptive or static CTLE */
1230 write_gasket_interrupt(dd, intnum++, 0x0026,
1231 0x5b01 | (static_ctle_mode << 3));
1232 /*
1233 * Enable iCal for PCIe Gen3 RX equalization, and set which
1234 * evaluation of RX_EQ_EVAL will launch the iCal procedure.
1235 */
1236 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202);
1237
1238 if (static_ctle_mode) {
1239 /* apply static CTLE tunings */
1240 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw;
1241
1242 pcie_dc = ctle_tunings[pcie_pset][0];
1243 pcie_lf = ctle_tunings[pcie_pset][1];
1244 pcie_hf = ctle_tunings[pcie_pset][2];
1245 pcie_bw = ctle_tunings[pcie_pset][3];
1246 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc);
1247 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf);
1248 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf);
1249 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw);
1250 }
1251
1252 /* terminate list */
1253 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000);
1254
1255 /*
1256 * step 5d: program XMT margin
1257 */
1258 write_xmt_margin(dd, __func__);
1259
1260 /*
1261 * step 5e: disable active state power management (ASPM). It
1262 * will be enabled if required later
1263 */
1264 dd_dev_info(dd, "%s: clearing ASPM\n", __func__);
1265 aspm_hw_disable_l1(dd);
1266
1267 /*
1268 * step 5f: clear DirectSpeedChange
1269 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the
1270 * change in the speed target from starting before we are ready.
1271 * This field defaults to 0 and we are not changing it, so nothing
1272 * needs to be done.
1273 */
1274
1275 /* step 5g: Set target link speed */
1276 /*
1277 * Set target link speed to be target on both device and parent.
1278 * On setting the parent: Some system BIOSs "helpfully" set the
1279 * parent target speed to Gen2 to match the ASIC's initial speed.
1280 * We can set the target Gen3 because we have already checked
1281 * that it is Gen3 capable earlier.
1282 */
1283 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__);
1284 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2);
1285 if (ret) {
1286 dd_dev_err(dd, "Unable to read from PCI config\n");
1287 return_error = 1;
1288 goto done;
1289 }
1290
1291 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1292 (u32)lnkctl2);
1293 /* only write to parent if target is not as high as ours */
1294 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) {
1295 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
1296 lnkctl2 |= target_vector;
1297 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1298 (u32)lnkctl2);
1299 ret = pcie_capability_write_word(parent,
1300 PCI_EXP_LNKCTL2, lnkctl2);
1301 if (ret) {
1302 dd_dev_err(dd, "Unable to write to PCI config\n");
1303 return_error = 1;
1304 goto done;
1305 }
1306 } else {
1307 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__);
1308 }
1309
1310 dd_dev_info(dd, "%s: setting target link speed\n", __func__);
1311 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
1312 if (ret) {
1313 dd_dev_err(dd, "Unable to read from PCI config\n");
1314 return_error = 1;
1315 goto done;
1316 }
1317
1318 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1319 (u32)lnkctl2);
1320 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
1321 lnkctl2 |= target_vector;
1322 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1323 (u32)lnkctl2);
1324 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
1325 if (ret) {
1326 dd_dev_err(dd, "Unable to write to PCI config\n");
1327 return_error = 1;
1328 goto done;
1329 }
1330
1331 /* step 5h: arm gasket logic */
1332 /* hold DC in reset across the SBR */
1333 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
1334 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */
1335 /* save firmware control across the SBR */
1336 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL);
1337
1338 dd_dev_info(dd, "%s: arming gasket logic\n", __func__);
1339 arm_gasket_logic(dd);
1340
1341 /*
1342 * step 6: quiesce PCIe link
1343 * The chip has already been reset, so there will be no traffic
1344 * from the chip. Linux has no easy way to enforce that it will
1345 * not try to access the device, so we just need to hope it doesn't
1346 * do it while we are doing the reset.
1347 */
1348
1349 /*
1350 * step 7: initiate the secondary bus reset (SBR)
1351 * step 8: hardware brings the links back up
1352 * step 9: wait for link speed transition to be complete
1353 */
1354 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__);
1355 ret = trigger_sbr(dd);
1356 if (ret)
1357 goto done;
1358
1359 /* step 10: decide what to do next */
1360
1361 /* check if we can read PCI space */
1362 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor);
1363 if (ret) {
1364 dd_dev_info(dd,
1365 "%s: read of VendorID failed after SBR, err %d\n",
1366 __func__, ret);
1367 return_error = 1;
1368 goto done;
1369 }
1370 if (vendor == 0xffff) {
1371 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__);
1372 return_error = 1;
1373 ret = -EIO;
1374 goto done;
1375 }
1376
1377 /* restore PCI space registers we know were reset */
1378 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__);
1379 ret = restore_pci_variables(dd);
1380 if (ret) {
1381 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
1382 __func__);
1383 return_error = 1;
1384 goto done;
1385 }
1386
1387 /* restore firmware control */
1388 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
1389
1390 /*
1391 * Check the gasket block status.
1392 *
1393 * This is the first CSR read after the SBR. If the read returns
1394 * all 1s (fails), the link did not make it back.
1395 *
1396 * Once we're sure we can read and write, clear the DC reset after
1397 * the SBR. Then check for any per-lane errors. Then look over
1398 * the status.
1399 */
1400 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS);
1401 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg);
1402 if (reg == ~0ull) { /* PCIe read failed/timeout */
1403 dd_dev_err(dd, "SBR failed - unable to read from device\n");
1404 return_error = 1;
1405 ret = -ENOSYS;
1406 goto done;
1407 }
1408
1409 /* clear the DC reset */
1410 write_csr(dd, CCE_DC_CTRL, 0);
1411
1412 /* Set the LED off */
1413 setextled(dd, 0);
1414
1415 /* check for any per-lane errors */
1416 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32);
1417 if (ret) {
1418 dd_dev_err(dd, "Unable to read from PCI config\n");
1419 return_error = 1;
1420 goto done;
1421 }
1422
1423 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32);
1424
1425 /* extract status, look for our HFI */
1426 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT)
1427 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK;
1428 if ((status & (1 << dd->hfi1_id)) == 0) {
1429 dd_dev_err(dd,
1430 "%s: gasket status 0x%x, expecting 0x%x\n",
1431 __func__, status, 1 << dd->hfi1_id);
1432 ret = -EIO;
1433 goto done;
1434 }
1435
1436 /* extract error */
1437 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT)
1438 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK;
1439 if (err) {
1440 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);
1441 ret = -EIO;
1442 goto done;
1443 }
1444
1445 /* update our link information cache */
1446 update_lbus_info(dd);
1447 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
1448 dd->lbus_info);
1449
1450 if (dd->lbus_speed != target_speed) { /* not target */
1451 /* maybe retry */
1452 do_retry = retry_count < pcie_retry;
1453 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n",
1454 pcie_target, do_retry ? ", retrying" : "");
1455 retry_count++;
1456 if (do_retry) {
1457 msleep(100); /* allow time to settle */
1458 goto retry;
1459 }
1460 ret = -EIO;
1461 }
1462
1463 done:
1464 if (therm) {
1465 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
1466 msleep(100);
1467 dd_dev_info(dd, "%s: Re-enable therm polling\n",
1468 __func__);
1469 }
1470 release_chip_resource(dd, CR_SBUS);
1471 done_no_mutex:
1472 /* return no error if it is OK to be at current speed */
1473 if (ret && !return_error) {
1474 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");
1475 ret = 0;
1476 }
1477
1478 dd_dev_info(dd, "%s: done\n", __func__);
1479 return ret;
1480 }
1481