1 /*
2 * Huawei HiNIC PCI Express Linux driver
3 * Copyright(c) 2017 Huawei Technologies Co., Ltd
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/device.h>
20 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
24 #include <linux/jiffies.h>
25 #include <linux/log2.h>
26 #include <linux/err.h>
27
28 #include "hinic_hw_if.h"
29 #include "hinic_hw_eqs.h"
30 #include "hinic_hw_mgmt.h"
31 #include "hinic_hw_qp_ctxt.h"
32 #include "hinic_hw_qp.h"
33 #include "hinic_hw_io.h"
34 #include "hinic_hw_dev.h"
35
36 #define IO_STATUS_TIMEOUT 100
37 #define OUTBOUND_STATE_TIMEOUT 100
38 #define DB_STATE_TIMEOUT 100
39
40 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs) \
41 (2 * (max_qps) + (num_aeqs) + (num_ceqs))
42
43 #define ADDR_IN_4BYTES(addr) ((addr) >> 2)
44
45 enum intr_type {
46 INTR_MSIX_TYPE,
47 };
48
49 enum io_status {
50 IO_STOPPED = 0,
51 IO_RUNNING = 1,
52 };
53
54 enum hw_ioctxt_set_cmdq_depth {
55 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT,
56 };
57
58 /* HW struct */
59 struct hinic_dev_cap {
60 u8 status;
61 u8 version;
62 u8 rsvd0[6];
63
64 u8 rsvd1[5];
65 u8 intr_type;
66 u8 rsvd2[66];
67 u16 max_sqs;
68 u16 max_rqs;
69 u8 rsvd3[208];
70 };
71
72 /**
73 * get_capability - convert device capabilities to NIC capabilities
74 * @hwdev: the HW device to set and convert device capabilities for
75 * @dev_cap: device capabilities from FW
76 *
77 * Return 0 - Success, negative - Failure
78 **/
get_capability(struct hinic_hwdev * hwdev,struct hinic_dev_cap * dev_cap)79 static int get_capability(struct hinic_hwdev *hwdev,
80 struct hinic_dev_cap *dev_cap)
81 {
82 struct hinic_cap *nic_cap = &hwdev->nic_cap;
83 int num_aeqs, num_ceqs, num_irqs;
84
85 if (!HINIC_IS_PF(hwdev->hwif) && !HINIC_IS_PPF(hwdev->hwif))
86 return -EINVAL;
87
88 if (dev_cap->intr_type != INTR_MSIX_TYPE)
89 return -EFAULT;
90
91 num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif);
92 num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif);
93 num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif);
94
95 /* Each QP has its own (SQ + RQ) interrupts */
96 nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2;
97
98 if (nic_cap->num_qps > HINIC_Q_CTXT_MAX)
99 nic_cap->num_qps = HINIC_Q_CTXT_MAX;
100
101 /* num_qps must be power of 2 */
102 nic_cap->num_qps = BIT(fls(nic_cap->num_qps) - 1);
103
104 nic_cap->max_qps = dev_cap->max_sqs + 1;
105 if (nic_cap->max_qps != (dev_cap->max_rqs + 1))
106 return -EFAULT;
107
108 if (nic_cap->num_qps > nic_cap->max_qps)
109 nic_cap->num_qps = nic_cap->max_qps;
110
111 return 0;
112 }
113
114 /**
115 * get_cap_from_fw - get device capabilities from FW
116 * @pfhwdev: the PF HW device to get capabilities for
117 *
118 * Return 0 - Success, negative - Failure
119 **/
get_cap_from_fw(struct hinic_pfhwdev * pfhwdev)120 static int get_cap_from_fw(struct hinic_pfhwdev *pfhwdev)
121 {
122 struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
123 struct hinic_hwif *hwif = hwdev->hwif;
124 struct pci_dev *pdev = hwif->pdev;
125 struct hinic_dev_cap dev_cap;
126 u16 in_len, out_len;
127 int err;
128
129 in_len = 0;
130 out_len = sizeof(dev_cap);
131
132 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM,
133 HINIC_CFG_NIC_CAP, &dev_cap, in_len, &dev_cap,
134 &out_len, HINIC_MGMT_MSG_SYNC);
135 if (err) {
136 dev_err(&pdev->dev, "Failed to get capability from FW\n");
137 return err;
138 }
139
140 return get_capability(hwdev, &dev_cap);
141 }
142
143 /**
144 * get_dev_cap - get device capabilities
145 * @hwdev: the NIC HW device to get capabilities for
146 *
147 * Return 0 - Success, negative - Failure
148 **/
get_dev_cap(struct hinic_hwdev * hwdev)149 static int get_dev_cap(struct hinic_hwdev *hwdev)
150 {
151 struct hinic_hwif *hwif = hwdev->hwif;
152 struct pci_dev *pdev = hwif->pdev;
153 struct hinic_pfhwdev *pfhwdev;
154 int err;
155
156 switch (HINIC_FUNC_TYPE(hwif)) {
157 case HINIC_PPF:
158 case HINIC_PF:
159 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
160
161 err = get_cap_from_fw(pfhwdev);
162 if (err) {
163 dev_err(&pdev->dev, "Failed to get capability from FW\n");
164 return err;
165 }
166 break;
167
168 default:
169 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
170 return -EINVAL;
171 }
172
173 return 0;
174 }
175
176 /**
177 * init_msix - enable the msix and save the entries
178 * @hwdev: the NIC HW device
179 *
180 * Return 0 - Success, negative - Failure
181 **/
init_msix(struct hinic_hwdev * hwdev)182 static int init_msix(struct hinic_hwdev *hwdev)
183 {
184 struct hinic_hwif *hwif = hwdev->hwif;
185 struct pci_dev *pdev = hwif->pdev;
186 int nr_irqs, num_aeqs, num_ceqs;
187 size_t msix_entries_size;
188 int i, err;
189
190 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
191 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif);
192 nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs);
193 if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif))
194 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif);
195
196 msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries);
197 hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size,
198 GFP_KERNEL);
199 if (!hwdev->msix_entries)
200 return -ENOMEM;
201
202 for (i = 0; i < nr_irqs; i++)
203 hwdev->msix_entries[i].entry = i;
204
205 err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs);
206 if (err) {
207 dev_err(&pdev->dev, "Failed to enable pci msix\n");
208 return err;
209 }
210
211 return 0;
212 }
213
214 /**
215 * disable_msix - disable the msix
216 * @hwdev: the NIC HW device
217 **/
disable_msix(struct hinic_hwdev * hwdev)218 static void disable_msix(struct hinic_hwdev *hwdev)
219 {
220 struct hinic_hwif *hwif = hwdev->hwif;
221 struct pci_dev *pdev = hwif->pdev;
222
223 pci_disable_msix(pdev);
224 }
225
226 /**
227 * hinic_port_msg_cmd - send port msg to mgmt
228 * @hwdev: the NIC HW device
229 * @cmd: the port command
230 * @buf_in: input buffer
231 * @in_size: input size
232 * @buf_out: output buffer
233 * @out_size: returned output size
234 *
235 * Return 0 - Success, negative - Failure
236 **/
hinic_port_msg_cmd(struct hinic_hwdev * hwdev,enum hinic_port_cmd cmd,void * buf_in,u16 in_size,void * buf_out,u16 * out_size)237 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
238 void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
239 {
240 struct hinic_hwif *hwif = hwdev->hwif;
241 struct pci_dev *pdev = hwif->pdev;
242 struct hinic_pfhwdev *pfhwdev;
243
244 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
245 dev_err(&pdev->dev, "unsupported PCI Function type\n");
246 return -EINVAL;
247 }
248
249 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
250
251 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd,
252 buf_in, in_size, buf_out, out_size,
253 HINIC_MGMT_MSG_SYNC);
254 }
255
256 /**
257 * init_fw_ctxt- Init Firmware tables before network mgmt and io operations
258 * @hwdev: the NIC HW device
259 *
260 * Return 0 - Success, negative - Failure
261 **/
init_fw_ctxt(struct hinic_hwdev * hwdev)262 static int init_fw_ctxt(struct hinic_hwdev *hwdev)
263 {
264 struct hinic_hwif *hwif = hwdev->hwif;
265 struct pci_dev *pdev = hwif->pdev;
266 struct hinic_cmd_fw_ctxt fw_ctxt;
267 struct hinic_pfhwdev *pfhwdev;
268 u16 out_size;
269 int err;
270
271 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
272 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
273 return -EINVAL;
274 }
275
276 fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
277 fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ;
278
279 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
280
281 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT,
282 &fw_ctxt, sizeof(fw_ctxt),
283 &fw_ctxt, &out_size);
284 if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) {
285 dev_err(&pdev->dev, "Failed to init FW ctxt, ret = %d\n",
286 fw_ctxt.status);
287 return -EFAULT;
288 }
289
290 return 0;
291 }
292
293 /**
294 * set_hw_ioctxt - set the shape of the IO queues in FW
295 * @hwdev: the NIC HW device
296 * @rq_depth: rq depth
297 * @sq_depth: sq depth
298 *
299 * Return 0 - Success, negative - Failure
300 **/
set_hw_ioctxt(struct hinic_hwdev * hwdev,unsigned int rq_depth,unsigned int sq_depth)301 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth,
302 unsigned int sq_depth)
303 {
304 struct hinic_hwif *hwif = hwdev->hwif;
305 struct hinic_cmd_hw_ioctxt hw_ioctxt;
306 struct pci_dev *pdev = hwif->pdev;
307 struct hinic_pfhwdev *pfhwdev;
308
309 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
310 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
311 return -EINVAL;
312 }
313
314 hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
315 hw_ioctxt.ppf_idx = HINIC_HWIF_PPF_IDX(hwif);
316
317 hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT;
318 hw_ioctxt.cmdq_depth = 0;
319
320 hw_ioctxt.rq_depth = ilog2(rq_depth);
321
322 hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX;
323
324 hw_ioctxt.sq_depth = ilog2(sq_depth);
325
326 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
327
328 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
329 HINIC_COMM_CMD_HWCTXT_SET,
330 &hw_ioctxt, sizeof(hw_ioctxt), NULL,
331 NULL, HINIC_MGMT_MSG_SYNC);
332 }
333
wait_for_outbound_state(struct hinic_hwdev * hwdev)334 static int wait_for_outbound_state(struct hinic_hwdev *hwdev)
335 {
336 enum hinic_outbound_state outbound_state;
337 struct hinic_hwif *hwif = hwdev->hwif;
338 struct pci_dev *pdev = hwif->pdev;
339 unsigned long end;
340
341 end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT);
342 do {
343 outbound_state = hinic_outbound_state_get(hwif);
344
345 if (outbound_state == HINIC_OUTBOUND_ENABLE)
346 return 0;
347
348 msleep(20);
349 } while (time_before(jiffies, end));
350
351 dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n");
352 return -EFAULT;
353 }
354
wait_for_db_state(struct hinic_hwdev * hwdev)355 static int wait_for_db_state(struct hinic_hwdev *hwdev)
356 {
357 struct hinic_hwif *hwif = hwdev->hwif;
358 struct pci_dev *pdev = hwif->pdev;
359 enum hinic_db_state db_state;
360 unsigned long end;
361
362 end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT);
363 do {
364 db_state = hinic_db_state_get(hwif);
365
366 if (db_state == HINIC_DB_ENABLE)
367 return 0;
368
369 msleep(20);
370 } while (time_before(jiffies, end));
371
372 dev_err(&pdev->dev, "Wait for DB - Timeout\n");
373 return -EFAULT;
374 }
375
wait_for_io_stopped(struct hinic_hwdev * hwdev)376 static int wait_for_io_stopped(struct hinic_hwdev *hwdev)
377 {
378 struct hinic_cmd_io_status cmd_io_status;
379 struct hinic_hwif *hwif = hwdev->hwif;
380 struct pci_dev *pdev = hwif->pdev;
381 struct hinic_pfhwdev *pfhwdev;
382 unsigned long end;
383 u16 out_size;
384 int err;
385
386 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
387 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
388 return -EINVAL;
389 }
390
391 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
392
393 cmd_io_status.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
394
395 end = jiffies + msecs_to_jiffies(IO_STATUS_TIMEOUT);
396 do {
397 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
398 HINIC_COMM_CMD_IO_STATUS_GET,
399 &cmd_io_status, sizeof(cmd_io_status),
400 &cmd_io_status, &out_size,
401 HINIC_MGMT_MSG_SYNC);
402 if ((err) || (out_size != sizeof(cmd_io_status))) {
403 dev_err(&pdev->dev, "Failed to get IO status, ret = %d\n",
404 err);
405 return err;
406 }
407
408 if (cmd_io_status.status == IO_STOPPED) {
409 dev_info(&pdev->dev, "IO stopped\n");
410 return 0;
411 }
412
413 msleep(20);
414 } while (time_before(jiffies, end));
415
416 dev_err(&pdev->dev, "Wait for IO stopped - Timeout\n");
417 return -ETIMEDOUT;
418 }
419
420 /**
421 * clear_io_resource - set the IO resources as not active in the NIC
422 * @hwdev: the NIC HW device
423 *
424 * Return 0 - Success, negative - Failure
425 **/
clear_io_resources(struct hinic_hwdev * hwdev)426 static int clear_io_resources(struct hinic_hwdev *hwdev)
427 {
428 struct hinic_cmd_clear_io_res cmd_clear_io_res;
429 struct hinic_hwif *hwif = hwdev->hwif;
430 struct pci_dev *pdev = hwif->pdev;
431 struct hinic_pfhwdev *pfhwdev;
432 int err;
433
434 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
435 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
436 return -EINVAL;
437 }
438
439 err = wait_for_io_stopped(hwdev);
440 if (err) {
441 dev_err(&pdev->dev, "IO has not stopped yet\n");
442 return err;
443 }
444
445 cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
446
447 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
448
449 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
450 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res,
451 sizeof(cmd_clear_io_res), NULL, NULL,
452 HINIC_MGMT_MSG_SYNC);
453 if (err) {
454 dev_err(&pdev->dev, "Failed to clear IO resources\n");
455 return err;
456 }
457
458 return 0;
459 }
460
461 /**
462 * set_resources_state - set the state of the resources in the NIC
463 * @hwdev: the NIC HW device
464 * @state: the state to set
465 *
466 * Return 0 - Success, negative - Failure
467 **/
set_resources_state(struct hinic_hwdev * hwdev,enum hinic_res_state state)468 static int set_resources_state(struct hinic_hwdev *hwdev,
469 enum hinic_res_state state)
470 {
471 struct hinic_cmd_set_res_state res_state;
472 struct hinic_hwif *hwif = hwdev->hwif;
473 struct pci_dev *pdev = hwif->pdev;
474 struct hinic_pfhwdev *pfhwdev;
475
476 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
477 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
478 return -EINVAL;
479 }
480
481 res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
482 res_state.state = state;
483
484 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
485
486 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt,
487 HINIC_MOD_COMM,
488 HINIC_COMM_CMD_RES_STATE_SET,
489 &res_state, sizeof(res_state), NULL,
490 NULL, HINIC_MGMT_MSG_SYNC);
491 }
492
493 /**
494 * get_base_qpn - get the first qp number
495 * @hwdev: the NIC HW device
496 * @base_qpn: returned qp number
497 *
498 * Return 0 - Success, negative - Failure
499 **/
get_base_qpn(struct hinic_hwdev * hwdev,u16 * base_qpn)500 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn)
501 {
502 struct hinic_cmd_base_qpn cmd_base_qpn;
503 struct hinic_hwif *hwif = hwdev->hwif;
504 struct pci_dev *pdev = hwif->pdev;
505 u16 out_size;
506 int err;
507
508 cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
509
510 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN,
511 &cmd_base_qpn, sizeof(cmd_base_qpn),
512 &cmd_base_qpn, &out_size);
513 if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) {
514 dev_err(&pdev->dev, "Failed to get base qpn, status = %d\n",
515 cmd_base_qpn.status);
516 return -EFAULT;
517 }
518
519 *base_qpn = cmd_base_qpn.qpn;
520 return 0;
521 }
522
523 /**
524 * hinic_hwdev_ifup - Preparing the HW for passing IO
525 * @hwdev: the NIC HW device
526 *
527 * Return 0 - Success, negative - Failure
528 **/
hinic_hwdev_ifup(struct hinic_hwdev * hwdev)529 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev)
530 {
531 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
532 struct hinic_cap *nic_cap = &hwdev->nic_cap;
533 struct hinic_hwif *hwif = hwdev->hwif;
534 int err, num_aeqs, num_ceqs, num_qps;
535 struct msix_entry *ceq_msix_entries;
536 struct msix_entry *sq_msix_entries;
537 struct msix_entry *rq_msix_entries;
538 struct pci_dev *pdev = hwif->pdev;
539 u16 base_qpn;
540
541 err = get_base_qpn(hwdev, &base_qpn);
542 if (err) {
543 dev_err(&pdev->dev, "Failed to get global base qp number\n");
544 return err;
545 }
546
547 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
548 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif);
549
550 ceq_msix_entries = &hwdev->msix_entries[num_aeqs];
551
552 err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs,
553 ceq_msix_entries);
554 if (err) {
555 dev_err(&pdev->dev, "Failed to init IO channel\n");
556 return err;
557 }
558
559 num_qps = nic_cap->num_qps;
560 sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs];
561 rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps];
562
563 err = hinic_io_create_qps(func_to_io, base_qpn, num_qps,
564 sq_msix_entries, rq_msix_entries);
565 if (err) {
566 dev_err(&pdev->dev, "Failed to create QPs\n");
567 goto err_create_qps;
568 }
569
570 err = wait_for_db_state(hwdev);
571 if (err) {
572 dev_warn(&pdev->dev, "db - disabled, try again\n");
573 hinic_db_state_set(hwif, HINIC_DB_ENABLE);
574 }
575
576 err = set_hw_ioctxt(hwdev, HINIC_SQ_DEPTH, HINIC_RQ_DEPTH);
577 if (err) {
578 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n");
579 goto err_hw_ioctxt;
580 }
581
582 return 0;
583
584 err_hw_ioctxt:
585 hinic_io_destroy_qps(func_to_io, num_qps);
586
587 err_create_qps:
588 hinic_io_free(func_to_io);
589 return err;
590 }
591
592 /**
593 * hinic_hwdev_ifdown - Closing the HW for passing IO
594 * @hwdev: the NIC HW device
595 *
596 **/
hinic_hwdev_ifdown(struct hinic_hwdev * hwdev)597 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev)
598 {
599 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
600 struct hinic_cap *nic_cap = &hwdev->nic_cap;
601
602 clear_io_resources(hwdev);
603
604 hinic_io_destroy_qps(func_to_io, nic_cap->num_qps);
605 hinic_io_free(func_to_io);
606 }
607
608 /**
609 * hinic_hwdev_cb_register - register callback handler for MGMT events
610 * @hwdev: the NIC HW device
611 * @cmd: the mgmt event
612 * @handle: private data for the handler
613 * @handler: event handler
614 **/
hinic_hwdev_cb_register(struct hinic_hwdev * hwdev,enum hinic_mgmt_msg_cmd cmd,void * handle,void (* handler)(void * handle,void * buf_in,u16 in_size,void * buf_out,u16 * out_size))615 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
616 enum hinic_mgmt_msg_cmd cmd, void *handle,
617 void (*handler)(void *handle, void *buf_in,
618 u16 in_size, void *buf_out,
619 u16 *out_size))
620 {
621 struct hinic_hwif *hwif = hwdev->hwif;
622 struct pci_dev *pdev = hwif->pdev;
623 struct hinic_pfhwdev *pfhwdev;
624 struct hinic_nic_cb *nic_cb;
625 u8 cmd_cb;
626
627 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
628 dev_err(&pdev->dev, "unsupported PCI Function type\n");
629 return;
630 }
631
632 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
633
634 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
635 nic_cb = &pfhwdev->nic_cb[cmd_cb];
636
637 nic_cb->handler = handler;
638 nic_cb->handle = handle;
639 nic_cb->cb_state = HINIC_CB_ENABLED;
640 }
641
642 /**
643 * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events
644 * @hwdev: the NIC HW device
645 * @cmd: the mgmt event
646 **/
hinic_hwdev_cb_unregister(struct hinic_hwdev * hwdev,enum hinic_mgmt_msg_cmd cmd)647 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
648 enum hinic_mgmt_msg_cmd cmd)
649 {
650 struct hinic_hwif *hwif = hwdev->hwif;
651 struct pci_dev *pdev = hwif->pdev;
652 struct hinic_pfhwdev *pfhwdev;
653 struct hinic_nic_cb *nic_cb;
654 u8 cmd_cb;
655
656 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
657 dev_err(&pdev->dev, "unsupported PCI Function type\n");
658 return;
659 }
660
661 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
662
663 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
664 nic_cb = &pfhwdev->nic_cb[cmd_cb];
665
666 nic_cb->cb_state &= ~HINIC_CB_ENABLED;
667
668 while (nic_cb->cb_state & HINIC_CB_RUNNING)
669 schedule();
670
671 nic_cb->handler = NULL;
672 }
673
674 /**
675 * nic_mgmt_msg_handler - nic mgmt event handler
676 * @handle: private data for the handler
677 * @buf_in: input buffer
678 * @in_size: input size
679 * @buf_out: output buffer
680 * @out_size: returned output size
681 **/
nic_mgmt_msg_handler(void * handle,u8 cmd,void * buf_in,u16 in_size,void * buf_out,u16 * out_size)682 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in,
683 u16 in_size, void *buf_out, u16 *out_size)
684 {
685 struct hinic_pfhwdev *pfhwdev = handle;
686 enum hinic_cb_state cb_state;
687 struct hinic_nic_cb *nic_cb;
688 struct hinic_hwdev *hwdev;
689 struct hinic_hwif *hwif;
690 struct pci_dev *pdev;
691 u8 cmd_cb;
692
693 hwdev = &pfhwdev->hwdev;
694 hwif = hwdev->hwif;
695 pdev = hwif->pdev;
696
697 if ((cmd < HINIC_MGMT_MSG_CMD_BASE) ||
698 (cmd >= HINIC_MGMT_MSG_CMD_MAX)) {
699 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd);
700 return;
701 }
702
703 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
704
705 nic_cb = &pfhwdev->nic_cb[cmd_cb];
706
707 cb_state = cmpxchg(&nic_cb->cb_state,
708 HINIC_CB_ENABLED,
709 HINIC_CB_ENABLED | HINIC_CB_RUNNING);
710
711 if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler))
712 nic_cb->handler(nic_cb->handle, buf_in,
713 in_size, buf_out, out_size);
714 else
715 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd);
716
717 nic_cb->cb_state &= ~HINIC_CB_RUNNING;
718 }
719
720 /**
721 * init_pfhwdev - Initialize the extended components of PF
722 * @pfhwdev: the HW device for PF
723 *
724 * Return 0 - success, negative - failure
725 **/
init_pfhwdev(struct hinic_pfhwdev * pfhwdev)726 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev)
727 {
728 struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
729 struct hinic_hwif *hwif = hwdev->hwif;
730 struct pci_dev *pdev = hwif->pdev;
731 int err;
732
733 err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif);
734 if (err) {
735 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n");
736 return err;
737 }
738
739 hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC,
740 pfhwdev, nic_mgmt_msg_handler);
741
742 hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE);
743 return 0;
744 }
745
746 /**
747 * free_pfhwdev - Free the extended components of PF
748 * @pfhwdev: the HW device for PF
749 **/
free_pfhwdev(struct hinic_pfhwdev * pfhwdev)750 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev)
751 {
752 struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
753
754 hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT);
755
756 hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC);
757
758 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt);
759 }
760
761 /**
762 * hinic_init_hwdev - Initialize the NIC HW
763 * @pdev: the NIC pci device
764 *
765 * Return initialized NIC HW device
766 *
767 * Initialize the NIC HW device and return a pointer to it
768 **/
hinic_init_hwdev(struct pci_dev * pdev)769 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev)
770 {
771 struct hinic_pfhwdev *pfhwdev;
772 struct hinic_hwdev *hwdev;
773 struct hinic_hwif *hwif;
774 int err, num_aeqs;
775
776 hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL);
777 if (!hwif)
778 return ERR_PTR(-ENOMEM);
779
780 err = hinic_init_hwif(hwif, pdev);
781 if (err) {
782 dev_err(&pdev->dev, "Failed to init HW interface\n");
783 return ERR_PTR(err);
784 }
785
786 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
787 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
788 err = -EFAULT;
789 goto err_func_type;
790 }
791
792 pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL);
793 if (!pfhwdev) {
794 err = -ENOMEM;
795 goto err_pfhwdev_alloc;
796 }
797
798 hwdev = &pfhwdev->hwdev;
799 hwdev->hwif = hwif;
800
801 err = init_msix(hwdev);
802 if (err) {
803 dev_err(&pdev->dev, "Failed to init msix\n");
804 goto err_init_msix;
805 }
806
807 err = wait_for_outbound_state(hwdev);
808 if (err) {
809 dev_warn(&pdev->dev, "outbound - disabled, try again\n");
810 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE);
811 }
812
813 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
814
815 err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs,
816 HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE,
817 hwdev->msix_entries);
818 if (err) {
819 dev_err(&pdev->dev, "Failed to init async event queues\n");
820 goto err_aeqs_init;
821 }
822
823 err = init_pfhwdev(pfhwdev);
824 if (err) {
825 dev_err(&pdev->dev, "Failed to init PF HW device\n");
826 goto err_init_pfhwdev;
827 }
828
829 err = get_dev_cap(hwdev);
830 if (err) {
831 dev_err(&pdev->dev, "Failed to get device capabilities\n");
832 goto err_dev_cap;
833 }
834
835 err = init_fw_ctxt(hwdev);
836 if (err) {
837 dev_err(&pdev->dev, "Failed to init function table\n");
838 goto err_init_fw_ctxt;
839 }
840
841 err = set_resources_state(hwdev, HINIC_RES_ACTIVE);
842 if (err) {
843 dev_err(&pdev->dev, "Failed to set resources state\n");
844 goto err_resources_state;
845 }
846
847 return hwdev;
848
849 err_resources_state:
850 err_init_fw_ctxt:
851 err_dev_cap:
852 free_pfhwdev(pfhwdev);
853
854 err_init_pfhwdev:
855 hinic_aeqs_free(&hwdev->aeqs);
856
857 err_aeqs_init:
858 disable_msix(hwdev);
859
860 err_init_msix:
861 err_pfhwdev_alloc:
862 err_func_type:
863 hinic_free_hwif(hwif);
864 return ERR_PTR(err);
865 }
866
867 /**
868 * hinic_free_hwdev - Free the NIC HW device
869 * @hwdev: the NIC HW device
870 **/
hinic_free_hwdev(struct hinic_hwdev * hwdev)871 void hinic_free_hwdev(struct hinic_hwdev *hwdev)
872 {
873 struct hinic_pfhwdev *pfhwdev = container_of(hwdev,
874 struct hinic_pfhwdev,
875 hwdev);
876
877 set_resources_state(hwdev, HINIC_RES_CLEAN);
878
879 free_pfhwdev(pfhwdev);
880
881 hinic_aeqs_free(&hwdev->aeqs);
882
883 disable_msix(hwdev);
884
885 hinic_free_hwif(hwdev->hwif);
886 }
887
888 /**
889 * hinic_hwdev_num_qps - return the number QPs available for use
890 * @hwdev: the NIC HW device
891 *
892 * Return number QPs available for use
893 **/
hinic_hwdev_num_qps(struct hinic_hwdev * hwdev)894 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev)
895 {
896 struct hinic_cap *nic_cap = &hwdev->nic_cap;
897
898 return nic_cap->num_qps;
899 }
900
901 /**
902 * hinic_hwdev_get_sq - get SQ
903 * @hwdev: the NIC HW device
904 * @i: the position of the SQ
905 *
906 * Return: the SQ in the i position
907 **/
hinic_hwdev_get_sq(struct hinic_hwdev * hwdev,int i)908 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i)
909 {
910 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
911 struct hinic_qp *qp = &func_to_io->qps[i];
912
913 if (i >= hinic_hwdev_num_qps(hwdev))
914 return NULL;
915
916 return &qp->sq;
917 }
918
919 /**
920 * hinic_hwdev_get_sq - get RQ
921 * @hwdev: the NIC HW device
922 * @i: the position of the RQ
923 *
924 * Return: the RQ in the i position
925 **/
hinic_hwdev_get_rq(struct hinic_hwdev * hwdev,int i)926 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i)
927 {
928 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
929 struct hinic_qp *qp = &func_to_io->qps[i];
930
931 if (i >= hinic_hwdev_num_qps(hwdev))
932 return NULL;
933
934 return &qp->rq;
935 }
936
937 /**
938 * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry
939 * @hwdev: the NIC HW device
940 * @msix_index: msix_index
941 *
942 * Return 0 - Success, negative - Failure
943 **/
hinic_hwdev_msix_cnt_set(struct hinic_hwdev * hwdev,u16 msix_index)944 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index)
945 {
946 return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index);
947 }
948
949 /**
950 * hinic_hwdev_msix_set - set message attribute for msix entry
951 * @hwdev: the NIC HW device
952 * @msix_index: msix_index
953 * @pending_limit: the maximum pending interrupt events (unit 8)
954 * @coalesc_timer: coalesc period for interrupt (unit 8 us)
955 * @lli_timer: replenishing period for low latency credit (unit 8 us)
956 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8)
957 * @resend_timer: maximum wait for resending msix (unit coalesc period)
958 *
959 * Return 0 - Success, negative - Failure
960 **/
hinic_hwdev_msix_set(struct hinic_hwdev * hwdev,u16 msix_index,u8 pending_limit,u8 coalesc_timer,u8 lli_timer_cfg,u8 lli_credit_limit,u8 resend_timer)961 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
962 u8 pending_limit, u8 coalesc_timer,
963 u8 lli_timer_cfg, u8 lli_credit_limit,
964 u8 resend_timer)
965 {
966 return hinic_msix_attr_set(hwdev->hwif, msix_index,
967 pending_limit, coalesc_timer,
968 lli_timer_cfg, lli_credit_limit,
969 resend_timer);
970 }
971
972 /**
973 * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq
974 * @hwdev: the NIC HW device
975 * @sq: send queue
976 * @pending_limit: the maximum pending update ci events (unit 8)
977 * @coalesc_timer: coalesc period for update ci (unit 8 us)
978 *
979 * Return 0 - Success, negative - Failure
980 **/
hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev * hwdev,struct hinic_sq * sq,u8 pending_limit,u8 coalesc_timer)981 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
982 u8 pending_limit, u8 coalesc_timer)
983 {
984 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
985 struct hinic_hwif *hwif = hwdev->hwif;
986 struct pci_dev *pdev = hwif->pdev;
987 struct hinic_pfhwdev *pfhwdev;
988 struct hinic_cmd_hw_ci hw_ci;
989
990 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
991 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
992 return -EINVAL;
993 }
994
995 hw_ci.dma_attr_off = 0;
996 hw_ci.pending_limit = pending_limit;
997 hw_ci.coalesc_timer = coalesc_timer;
998
999 hw_ci.msix_en = 1;
1000 hw_ci.msix_entry_idx = sq->msix_entry;
1001
1002 hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
1003
1004 hw_ci.sq_id = qp->q_id;
1005
1006 hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr);
1007
1008 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
1009 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt,
1010 HINIC_MOD_COMM,
1011 HINIC_COMM_CMD_SQ_HI_CI_SET,
1012 &hw_ci, sizeof(hw_ci), NULL,
1013 NULL, HINIC_MGMT_MSG_SYNC);
1014 }
1015