1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/err.h>
3 #include <linux/module.h>
4 #include <linux/io.h>
5 #include <linux/of.h>
6 #include <linux/of_address.h>
7 #include <linux/slab.h>
8 #include <linux/sys_soc.h>
9
10 #include "hardware.h"
11 #include "common.h"
12
13 unsigned int __mxc_cpu_type;
14 static unsigned int imx_soc_revision;
15
mxc_set_cpu_type(unsigned int type)16 void mxc_set_cpu_type(unsigned int type)
17 {
18 __mxc_cpu_type = type;
19 }
20
imx_set_soc_revision(unsigned int rev)21 void imx_set_soc_revision(unsigned int rev)
22 {
23 imx_soc_revision = rev;
24 }
25
imx_get_soc_revision(void)26 unsigned int imx_get_soc_revision(void)
27 {
28 return imx_soc_revision;
29 }
30
imx_print_silicon_rev(const char * cpu,int srev)31 void imx_print_silicon_rev(const char *cpu, int srev)
32 {
33 if (srev == IMX_CHIP_REVISION_UNKNOWN)
34 pr_info("CPU identified as %s, unknown revision\n", cpu);
35 else
36 pr_info("CPU identified as %s, silicon rev %d.%d\n",
37 cpu, (srev >> 4) & 0xf, srev & 0xf);
38 }
39
imx_set_aips(void __iomem * base)40 void __init imx_set_aips(void __iomem *base)
41 {
42 unsigned int reg;
43 /*
44 * Set all MPROTx to be non-bufferable, trusted for R/W,
45 * not forced to user-mode.
46 */
47 imx_writel(0x77777777, base + 0x0);
48 imx_writel(0x77777777, base + 0x4);
49
50 /*
51 * Set all OPACRx to be non-bufferable, to not require
52 * supervisor privilege level for access, allow for
53 * write access and untrusted master access.
54 */
55 imx_writel(0x0, base + 0x40);
56 imx_writel(0x0, base + 0x44);
57 imx_writel(0x0, base + 0x48);
58 imx_writel(0x0, base + 0x4C);
59 reg = imx_readl(base + 0x50) & 0x00FFFFFF;
60 imx_writel(reg, base + 0x50);
61 }
62
imx_aips_allow_unprivileged_access(const char * compat)63 void __init imx_aips_allow_unprivileged_access(
64 const char *compat)
65 {
66 void __iomem *aips_base_addr;
67 struct device_node *np;
68
69 for_each_compatible_node(np, NULL, compat) {
70 aips_base_addr = of_iomap(np, 0);
71 imx_set_aips(aips_base_addr);
72 }
73 }
74
imx_soc_device_init(void)75 struct device * __init imx_soc_device_init(void)
76 {
77 struct soc_device_attribute *soc_dev_attr;
78 struct soc_device *soc_dev;
79 struct device_node *root;
80 const char *soc_id;
81 int ret;
82
83 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
84 if (!soc_dev_attr)
85 return NULL;
86
87 soc_dev_attr->family = "Freescale i.MX";
88
89 root = of_find_node_by_path("/");
90 ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
91 of_node_put(root);
92 if (ret)
93 goto free_soc;
94
95 switch (__mxc_cpu_type) {
96 case MXC_CPU_MX1:
97 soc_id = "i.MX1";
98 break;
99 case MXC_CPU_MX21:
100 soc_id = "i.MX21";
101 break;
102 case MXC_CPU_MX25:
103 soc_id = "i.MX25";
104 break;
105 case MXC_CPU_MX27:
106 soc_id = "i.MX27";
107 break;
108 case MXC_CPU_MX31:
109 soc_id = "i.MX31";
110 break;
111 case MXC_CPU_MX35:
112 soc_id = "i.MX35";
113 break;
114 case MXC_CPU_MX51:
115 soc_id = "i.MX51";
116 break;
117 case MXC_CPU_MX53:
118 soc_id = "i.MX53";
119 break;
120 case MXC_CPU_IMX6SL:
121 soc_id = "i.MX6SL";
122 break;
123 case MXC_CPU_IMX6DL:
124 soc_id = "i.MX6DL";
125 break;
126 case MXC_CPU_IMX6SX:
127 soc_id = "i.MX6SX";
128 break;
129 case MXC_CPU_IMX6Q:
130 soc_id = "i.MX6Q";
131 break;
132 case MXC_CPU_IMX6UL:
133 soc_id = "i.MX6UL";
134 break;
135 case MXC_CPU_IMX6ULL:
136 soc_id = "i.MX6ULL";
137 break;
138 case MXC_CPU_IMX7D:
139 soc_id = "i.MX7D";
140 break;
141 default:
142 soc_id = "Unknown";
143 }
144 soc_dev_attr->soc_id = soc_id;
145
146 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
147 (imx_soc_revision >> 4) & 0xf,
148 imx_soc_revision & 0xf);
149 if (!soc_dev_attr->revision)
150 goto free_soc;
151
152 soc_dev = soc_device_register(soc_dev_attr);
153 if (IS_ERR(soc_dev))
154 goto free_rev;
155
156 return soc_device_to_device(soc_dev);
157
158 free_rev:
159 kfree(soc_dev_attr->revision);
160 free_soc:
161 kfree(soc_dev_attr);
162 return NULL;
163 }
164