1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
3 #ifdef __KERNEL__
4
5 #define ARCH_HAS_IOREMAP_WC
6
7 /*
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
18
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
21 /*
22 * has legacy ISA devices ?
23 */
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25 #endif
26
27 #include <linux/device.h>
28 #include <linux/compiler.h>
29 #include <asm/page.h>
30 #include <asm/byteorder.h>
31 #include <asm/synch.h>
32 #include <asm/delay.h>
33 #include <asm/mmu.h>
34 #include <asm/ppc_asm.h>
35
36 #include <asm-generic/iomap.h>
37
38 #ifdef CONFIG_PPC64
39 #include <asm/paca.h>
40 #endif
41
42 #define SIO_CONFIG_RA 0x398
43 #define SIO_CONFIG_RD 0x399
44
45 #define SLOW_DOWN_IO
46
47 /* 32 bits uses slightly different variables for the various IO
48 * bases. Most of this file only uses _IO_BASE though which we
49 * define properly based on the platform
50 */
51 #ifndef CONFIG_PCI
52 #define _IO_BASE 0
53 #define _ISA_MEM_BASE 0
54 #define PCI_DRAM_OFFSET 0
55 #elif defined(CONFIG_PPC32)
56 #define _IO_BASE isa_io_base
57 #define _ISA_MEM_BASE isa_mem_base
58 #define PCI_DRAM_OFFSET pci_dram_offset
59 #else
60 #define _IO_BASE pci_io_base
61 #define _ISA_MEM_BASE isa_mem_base
62 #define PCI_DRAM_OFFSET 0
63 #endif
64
65 extern unsigned long isa_io_base;
66 extern unsigned long pci_io_base;
67 extern unsigned long pci_dram_offset;
68
69 extern resource_size_t isa_mem_base;
70
71 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
72 * is not set or addresses cannot be translated to MMIO. This is typically
73 * set when the platform supports "special" PIO accesses via a non memory
74 * mapped mechanism, and allows things like the early udbg UART code to
75 * function.
76 */
77 extern bool isa_io_special;
78
79 #ifdef CONFIG_PPC32
80 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
81 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
82 #endif
83 #endif
84
85 /*
86 *
87 * Low level MMIO accessors
88 *
89 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
90 * specific and thus shouldn't be used in generic code. The accessors
91 * provided here are:
92 *
93 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
94 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
95 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
96 *
97 * Those operate directly on a kernel virtual address. Note that the prototype
98 * for the out_* accessors has the arguments in opposite order from the usual
99 * linux PCI accessors. Unlike those, they take the address first and the value
100 * next.
101 *
102 * Note: I might drop the _ns suffix on the stream operations soon as it is
103 * simply normal for stream operations to not swap in the first place.
104 *
105 */
106
107 #ifdef CONFIG_PPC64
108 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
109 #else
110 #define IO_SET_SYNC_FLAG()
111 #endif
112
113 /* gcc 4.0 and older doesn't have 'Z' constraint */
114 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
115 #define DEF_MMIO_IN_X(name, size, insn) \
116 static inline u##size name(const volatile u##size __iomem *addr) \
117 { \
118 u##size ret; \
119 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
120 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
121 return ret; \
122 }
123
124 #define DEF_MMIO_OUT_X(name, size, insn) \
125 static inline void name(volatile u##size __iomem *addr, u##size val) \
126 { \
127 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
128 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
129 IO_SET_SYNC_FLAG(); \
130 }
131 #else /* newer gcc */
132 #define DEF_MMIO_IN_X(name, size, insn) \
133 static inline u##size name(const volatile u##size __iomem *addr) \
134 { \
135 u##size ret; \
136 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
137 : "=r" (ret) : "Z" (*addr) : "memory"); \
138 return ret; \
139 }
140
141 #define DEF_MMIO_OUT_X(name, size, insn) \
142 static inline void name(volatile u##size __iomem *addr, u##size val) \
143 { \
144 __asm__ __volatile__("sync;"#insn" %1,%y0" \
145 : "=Z" (*addr) : "r" (val) : "memory"); \
146 IO_SET_SYNC_FLAG(); \
147 }
148 #endif
149
150 #define DEF_MMIO_IN_D(name, size, insn) \
151 static inline u##size name(const volatile u##size __iomem *addr) \
152 { \
153 u##size ret; \
154 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
155 : "=r" (ret) : "m" (*addr) : "memory"); \
156 return ret; \
157 }
158
159 #define DEF_MMIO_OUT_D(name, size, insn) \
160 static inline void name(volatile u##size __iomem *addr, u##size val) \
161 { \
162 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
163 : "=m" (*addr) : "r" (val) : "memory"); \
164 IO_SET_SYNC_FLAG(); \
165 }
166
167 DEF_MMIO_IN_D(in_8, 8, lbz);
168 DEF_MMIO_OUT_D(out_8, 8, stb);
169
170 #ifdef __BIG_ENDIAN__
171 DEF_MMIO_IN_D(in_be16, 16, lhz);
172 DEF_MMIO_IN_D(in_be32, 32, lwz);
173 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
174 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
175
176 DEF_MMIO_OUT_D(out_be16, 16, sth);
177 DEF_MMIO_OUT_D(out_be32, 32, stw);
178 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
179 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
180 #else
181 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
182 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
183 DEF_MMIO_IN_D(in_le16, 16, lhz);
184 DEF_MMIO_IN_D(in_le32, 32, lwz);
185
186 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
187 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
188 DEF_MMIO_OUT_D(out_le16, 16, sth);
189 DEF_MMIO_OUT_D(out_le32, 32, stw);
190
191 #endif /* __BIG_ENDIAN */
192
193 #ifdef __powerpc64__
194
195 #ifdef __BIG_ENDIAN__
196 DEF_MMIO_OUT_D(out_be64, 64, std);
197 DEF_MMIO_IN_D(in_be64, 64, ld);
198
199 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)200 static inline u64 in_le64(const volatile u64 __iomem *addr)
201 {
202 return swab64(in_be64(addr));
203 }
204
out_le64(volatile u64 __iomem * addr,u64 val)205 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
206 {
207 out_be64(addr, swab64(val));
208 }
209 #else
210 DEF_MMIO_OUT_D(out_le64, 64, std);
211 DEF_MMIO_IN_D(in_le64, 64, ld);
212
213 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)214 static inline u64 in_be64(const volatile u64 __iomem *addr)
215 {
216 return swab64(in_le64(addr));
217 }
218
out_be64(volatile u64 __iomem * addr,u64 val)219 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
220 {
221 out_le64(addr, swab64(val));
222 }
223
224 #endif
225 #endif /* __powerpc64__ */
226
227 /*
228 * Low level IO stream instructions are defined out of line for now
229 */
230 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
231 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
232 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
233 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
234 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
235 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
236
237 /* The _ns naming is historical and will be removed. For now, just #define
238 * the non _ns equivalent names
239 */
240 #define _insw _insw_ns
241 #define _insl _insl_ns
242 #define _outsw _outsw_ns
243 #define _outsl _outsl_ns
244
245
246 /*
247 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
248 */
249
250 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
251 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
252 unsigned long n);
253 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
254 unsigned long n);
255
256 /*
257 *
258 * PCI and standard ISA accessors
259 *
260 * Those are globally defined linux accessors for devices on PCI or ISA
261 * busses. They follow the Linux defined semantics. The current implementation
262 * for PowerPC is as close as possible to the x86 version of these, and thus
263 * provides fairly heavy weight barriers for the non-raw versions
264 *
265 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
266 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
267 * own implementation of some or all of the accessors.
268 */
269
270 /*
271 * Include the EEH definitions when EEH is enabled only so they don't get
272 * in the way when building for 32 bits
273 */
274 #ifdef CONFIG_EEH
275 #include <asm/eeh.h>
276 #endif
277
278 /* Shortcut to the MMIO argument pointer */
279 #define PCI_IO_ADDR volatile void __iomem *
280
281 /* Indirect IO address tokens:
282 *
283 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
284 * on all MMIOs. (Note that this is all 64 bits only for now)
285 *
286 * To help platforms who may need to differentiate MMIO addresses in
287 * their hooks, a bitfield is reserved for use by the platform near the
288 * top of MMIO addresses (not PIO, those have to cope the hard way).
289 *
290 * The highest address in the kernel virtual space are:
291 *
292 * d0003fffffffffff # with Hash MMU
293 * c00fffffffffffff # with Radix MMU
294 *
295 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
296 * that can be used for the field.
297 *
298 * The direct IO mapping operations will then mask off those bits
299 * before doing the actual access, though that only happen when
300 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
301 * mechanism
302 *
303 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
304 * all PIO functions call through a hook.
305 */
306
307 #ifdef CONFIG_PPC_INDIRECT_MMIO
308 #define PCI_IO_IND_TOKEN_SHIFT 52
309 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
310 #define PCI_FIX_ADDR(addr) \
311 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
312 #define PCI_GET_ADDR_TOKEN(addr) \
313 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
314 PCI_IO_IND_TOKEN_SHIFT)
315 #define PCI_SET_ADDR_TOKEN(addr, token) \
316 do { \
317 unsigned long __a = (unsigned long)(addr); \
318 __a &= ~PCI_IO_IND_TOKEN_MASK; \
319 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
320 (addr) = (void __iomem *)__a; \
321 } while(0)
322 #else
323 #define PCI_FIX_ADDR(addr) (addr)
324 #endif
325
326
327 /*
328 * Non ordered and non-swapping "raw" accessors
329 */
330
__raw_readb(const volatile void __iomem * addr)331 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
332 {
333 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
334 }
__raw_readw(const volatile void __iomem * addr)335 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
336 {
337 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
338 }
__raw_readl(const volatile void __iomem * addr)339 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
340 {
341 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
342 }
__raw_writeb(unsigned char v,volatile void __iomem * addr)343 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
344 {
345 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
346 }
__raw_writew(unsigned short v,volatile void __iomem * addr)347 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
348 {
349 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
350 }
__raw_writel(unsigned int v,volatile void __iomem * addr)351 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
352 {
353 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
354 }
355
356 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)357 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
358 {
359 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
360 }
__raw_writeq(unsigned long v,volatile void __iomem * addr)361 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
362 {
363 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
364 }
365
366 /*
367 * Real mode versions of the above. Those instructions are only supposed
368 * to be used in hypervisor real mode as per the architecture spec.
369 */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)370 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
371 {
372 __asm__ __volatile__("stbcix %0,0,%1"
373 : : "r" (val), "r" (paddr) : "memory");
374 }
375
__raw_rm_writew(u16 val,volatile void __iomem * paddr)376 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
377 {
378 __asm__ __volatile__("sthcix %0,0,%1"
379 : : "r" (val), "r" (paddr) : "memory");
380 }
381
__raw_rm_writel(u32 val,volatile void __iomem * paddr)382 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
383 {
384 __asm__ __volatile__("stwcix %0,0,%1"
385 : : "r" (val), "r" (paddr) : "memory");
386 }
387
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)388 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
389 {
390 __asm__ __volatile__("stdcix %0,0,%1"
391 : : "r" (val), "r" (paddr) : "memory");
392 }
393
__raw_rm_readb(volatile void __iomem * paddr)394 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
395 {
396 u8 ret;
397 __asm__ __volatile__("lbzcix %0,0, %1"
398 : "=r" (ret) : "r" (paddr) : "memory");
399 return ret;
400 }
401
__raw_rm_readw(volatile void __iomem * paddr)402 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
403 {
404 u16 ret;
405 __asm__ __volatile__("lhzcix %0,0, %1"
406 : "=r" (ret) : "r" (paddr) : "memory");
407 return ret;
408 }
409
__raw_rm_readl(volatile void __iomem * paddr)410 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
411 {
412 u32 ret;
413 __asm__ __volatile__("lwzcix %0,0, %1"
414 : "=r" (ret) : "r" (paddr) : "memory");
415 return ret;
416 }
417
__raw_rm_readq(volatile void __iomem * paddr)418 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
419 {
420 u64 ret;
421 __asm__ __volatile__("ldcix %0,0, %1"
422 : "=r" (ret) : "r" (paddr) : "memory");
423 return ret;
424 }
425 #endif /* __powerpc64__ */
426
427 /*
428 *
429 * PCI PIO and MMIO accessors.
430 *
431 *
432 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
433 * machine checks (which they occasionally do when probing non existing
434 * IO ports on some platforms, like PowerMac and 8xx).
435 * I always found it to be of dubious reliability and I am tempted to get
436 * rid of it one of these days. So if you think it's important to keep it,
437 * please voice up asap. We never had it for 64 bits and I do not intend
438 * to port it over
439 */
440
441 #ifdef CONFIG_PPC32
442
443 #define __do_in_asm(name, op) \
444 static inline unsigned int name(unsigned int port) \
445 { \
446 unsigned int x; \
447 __asm__ __volatile__( \
448 "sync\n" \
449 "0:" op " %0,0,%1\n" \
450 "1: twi 0,%0,0\n" \
451 "2: isync\n" \
452 "3: nop\n" \
453 "4:\n" \
454 ".section .fixup,\"ax\"\n" \
455 "5: li %0,-1\n" \
456 " b 4b\n" \
457 ".previous\n" \
458 EX_TABLE(0b, 5b) \
459 EX_TABLE(1b, 5b) \
460 EX_TABLE(2b, 5b) \
461 EX_TABLE(3b, 5b) \
462 : "=&r" (x) \
463 : "r" (port + _IO_BASE) \
464 : "memory"); \
465 return x; \
466 }
467
468 #define __do_out_asm(name, op) \
469 static inline void name(unsigned int val, unsigned int port) \
470 { \
471 __asm__ __volatile__( \
472 "sync\n" \
473 "0:" op " %0,0,%1\n" \
474 "1: sync\n" \
475 "2:\n" \
476 EX_TABLE(0b, 2b) \
477 EX_TABLE(1b, 2b) \
478 : : "r" (val), "r" (port + _IO_BASE) \
479 : "memory"); \
480 }
481
482 __do_in_asm(_rec_inb, "lbzx")
483 __do_in_asm(_rec_inw, "lhbrx")
484 __do_in_asm(_rec_inl, "lwbrx")
485 __do_out_asm(_rec_outb, "stbx")
486 __do_out_asm(_rec_outw, "sthbrx")
487 __do_out_asm(_rec_outl, "stwbrx")
488
489 #endif /* CONFIG_PPC32 */
490
491 /* The "__do_*" operations below provide the actual "base" implementation
492 * for each of the defined accessors. Some of them use the out_* functions
493 * directly, some of them still use EEH, though we might change that in the
494 * future. Those macros below provide the necessary argument swapping and
495 * handling of the IO base for PIO.
496 *
497 * They are themselves used by the macros that define the actual accessors
498 * and can be used by the hooks if any.
499 *
500 * Note that PIO operations are always defined in terms of their corresonding
501 * MMIO operations. That allows platforms like iSeries who want to modify the
502 * behaviour of both to only hook on the MMIO version and get both. It's also
503 * possible to hook directly at the toplevel PIO operation if they have to
504 * be handled differently
505 */
506 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
507 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
508 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
509 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
510 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
511 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
512 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
513
514 #ifdef CONFIG_EEH
515 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
516 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
517 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
518 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
519 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
520 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
521 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
522 #else /* CONFIG_EEH */
523 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
524 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
525 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
526 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
527 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
528 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
529 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
530 #endif /* !defined(CONFIG_EEH) */
531
532 #ifdef CONFIG_PPC32
533 #define __do_outb(val, port) _rec_outb(val, port)
534 #define __do_outw(val, port) _rec_outw(val, port)
535 #define __do_outl(val, port) _rec_outl(val, port)
536 #define __do_inb(port) _rec_inb(port)
537 #define __do_inw(port) _rec_inw(port)
538 #define __do_inl(port) _rec_inl(port)
539 #else /* CONFIG_PPC32 */
540 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
541 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
542 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
543 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
544 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
545 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
546 #endif /* !CONFIG_PPC32 */
547
548 #ifdef CONFIG_EEH
549 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
550 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
551 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
552 #else /* CONFIG_EEH */
553 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
554 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
555 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
556 #endif /* !CONFIG_EEH */
557 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
558 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
559 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
560
561 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
562 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
563 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
564 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
565 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
566 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
567
568 #define __do_memset_io(addr, c, n) \
569 _memset_io(PCI_FIX_ADDR(addr), c, n)
570 #define __do_memcpy_toio(dst, src, n) \
571 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
572
573 #ifdef CONFIG_EEH
574 #define __do_memcpy_fromio(dst, src, n) \
575 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
576 #else /* CONFIG_EEH */
577 #define __do_memcpy_fromio(dst, src, n) \
578 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
579 #endif /* !CONFIG_EEH */
580
581 #ifdef CONFIG_PPC_INDIRECT_PIO
582 #define DEF_PCI_HOOK_pio(x) x
583 #else
584 #define DEF_PCI_HOOK_pio(x) NULL
585 #endif
586
587 #ifdef CONFIG_PPC_INDIRECT_MMIO
588 #define DEF_PCI_HOOK_mem(x) x
589 #else
590 #define DEF_PCI_HOOK_mem(x) NULL
591 #endif
592
593 /* Structure containing all the hooks */
594 extern struct ppc_pci_io {
595
596 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
597 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
598
599 #include <asm/io-defs.h>
600
601 #undef DEF_PCI_AC_RET
602 #undef DEF_PCI_AC_NORET
603
604 } ppc_pci_io;
605
606 /* The inline wrappers */
607 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
608 static inline ret name at \
609 { \
610 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
611 return ppc_pci_io.name al; \
612 return __do_##name al; \
613 }
614
615 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
616 static inline void name at \
617 { \
618 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
619 ppc_pci_io.name al; \
620 else \
621 __do_##name al; \
622 }
623
624 #include <asm/io-defs.h>
625
626 #undef DEF_PCI_AC_RET
627 #undef DEF_PCI_AC_NORET
628
629 /* Some drivers check for the presence of readq & writeq with
630 * a #ifdef, so we make them happy here.
631 */
632 #ifdef __powerpc64__
633 #define readq readq
634 #define writeq writeq
635 #endif
636
637 /*
638 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
639 * access
640 */
641 #define xlate_dev_mem_ptr(p) __va(p)
642
643 /*
644 * Convert a virtual cached pointer to an uncached pointer
645 */
646 #define xlate_dev_kmem_ptr(p) p
647
648 /*
649 * We don't do relaxed operations yet, at least not with this semantic
650 */
651 #define readb_relaxed(addr) readb(addr)
652 #define readw_relaxed(addr) readw(addr)
653 #define readl_relaxed(addr) readl(addr)
654 #define readq_relaxed(addr) readq(addr)
655 #define writeb_relaxed(v, addr) writeb(v, addr)
656 #define writew_relaxed(v, addr) writew(v, addr)
657 #define writel_relaxed(v, addr) writel(v, addr)
658 #define writeq_relaxed(v, addr) writeq(v, addr)
659
660 #ifdef CONFIG_PPC32
661 #define mmiowb()
662 #else
663 /*
664 * Enforce synchronisation of stores vs. spin_unlock
665 * (this does it explicitly, though our implementation of spin_unlock
666 * does it implicitely too)
667 */
mmiowb(void)668 static inline void mmiowb(void)
669 {
670 unsigned long tmp;
671
672 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
673 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
674 : "memory");
675 }
676 #endif /* !CONFIG_PPC32 */
677
iosync(void)678 static inline void iosync(void)
679 {
680 __asm__ __volatile__ ("sync" : : : "memory");
681 }
682
683 /* Enforce in-order execution of data I/O.
684 * No distinction between read/write on PPC; use eieio for all three.
685 * Those are fairly week though. They don't provide a barrier between
686 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
687 * they only provide barriers between 2 __raw MMIO operations and
688 * possibly break write combining.
689 */
690 #define iobarrier_rw() eieio()
691 #define iobarrier_r() eieio()
692 #define iobarrier_w() eieio()
693
694
695 /*
696 * output pause versions need a delay at least for the
697 * w83c105 ide controller in a p610.
698 */
699 #define inb_p(port) inb(port)
700 #define outb_p(val, port) (udelay(1), outb((val), (port)))
701 #define inw_p(port) inw(port)
702 #define outw_p(val, port) (udelay(1), outw((val), (port)))
703 #define inl_p(port) inl(port)
704 #define outl_p(val, port) (udelay(1), outl((val), (port)))
705
706
707 #define IO_SPACE_LIMIT ~(0UL)
708
709
710 /**
711 * ioremap - map bus memory into CPU space
712 * @address: bus address of the memory
713 * @size: size of the resource to map
714 *
715 * ioremap performs a platform specific sequence of operations to
716 * make bus memory CPU accessible via the readb/readw/readl/writeb/
717 * writew/writel functions and the other mmio helpers. The returned
718 * address is not guaranteed to be usable directly as a virtual
719 * address.
720 *
721 * We provide a few variations of it:
722 *
723 * * ioremap is the standard one and provides non-cacheable guarded mappings
724 * and can be hooked by the platform via ppc_md
725 *
726 * * ioremap_prot allows to specify the page flags as an argument and can
727 * also be hooked by the platform via ppc_md.
728 *
729 * * ioremap_nocache is identical to ioremap
730 *
731 * * ioremap_wc enables write combining
732 *
733 * * iounmap undoes such a mapping and can be hooked
734 *
735 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
736 * create hand-made mappings for use only by the PCI code and cannot
737 * currently be hooked. Must be page aligned.
738 *
739 * * __ioremap is the low level implementation used by ioremap and
740 * ioremap_prot and cannot be hooked (but can be used by a hook on one
741 * of the previous ones)
742 *
743 * * __ioremap_caller is the same as above but takes an explicit caller
744 * reference rather than using __builtin_return_address(0)
745 *
746 * * __iounmap, is the low level implementation used by iounmap and cannot
747 * be hooked (but can be used by a hook on iounmap)
748 *
749 */
750 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
751 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
752 unsigned long flags);
753 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
754 #define ioremap_nocache(addr, size) ioremap((addr), (size))
755 #define ioremap_uc(addr, size) ioremap((addr), (size))
756 #define ioremap_cache(addr, size) \
757 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
758
759 extern void iounmap(volatile void __iomem *addr);
760
761 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
762 unsigned long flags);
763 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
764 unsigned long flags, void *caller);
765
766 extern void __iounmap(volatile void __iomem *addr);
767
768 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
769 unsigned long size, unsigned long flags);
770 extern void __iounmap_at(void *ea, unsigned long size);
771
772 /*
773 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
774 * which needs some additional definitions here. They basically allow PIO
775 * space overall to be 1GB. This will work as long as we never try to use
776 * iomap to map MMIO below 1GB which should be fine on ppc64
777 */
778 #define HAVE_ARCH_PIO_SIZE 1
779 #define PIO_OFFSET 0x00000000UL
780 #define PIO_MASK (FULL_IO_SIZE - 1)
781 #define PIO_RESERVED (FULL_IO_SIZE)
782
783 #define mmio_read16be(addr) readw_be(addr)
784 #define mmio_read32be(addr) readl_be(addr)
785 #define mmio_write16be(val, addr) writew_be(val, addr)
786 #define mmio_write32be(val, addr) writel_be(val, addr)
787 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
788 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
789 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
790 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
791 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
792 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
793
794 /**
795 * virt_to_phys - map virtual addresses to physical
796 * @address: address to remap
797 *
798 * The returned physical address is the physical (CPU) mapping for
799 * the memory address given. It is only valid to use this function on
800 * addresses directly mapped or allocated via kmalloc.
801 *
802 * This function does not give bus mappings for DMA transfers. In
803 * almost all conceivable cases a device driver should not be using
804 * this function
805 */
virt_to_phys(volatile void * address)806 static inline unsigned long virt_to_phys(volatile void * address)
807 {
808 return __pa((unsigned long)address);
809 }
810
811 /**
812 * phys_to_virt - map physical address to virtual
813 * @address: address to remap
814 *
815 * The returned virtual address is a current CPU mapping for
816 * the memory address given. It is only valid to use this function on
817 * addresses that have a kernel mapping
818 *
819 * This function does not handle bus mappings for DMA transfers. In
820 * almost all conceivable cases a device driver should not be using
821 * this function
822 */
phys_to_virt(unsigned long address)823 static inline void * phys_to_virt(unsigned long address)
824 {
825 return (void *)__va(address);
826 }
827
828 /*
829 * Change "struct page" to physical address.
830 */
831 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
832
833 /*
834 * 32 bits still uses virt_to_bus() for it's implementation of DMA
835 * mappings se we have to keep it defined here. We also have some old
836 * drivers (shame shame shame) that use bus_to_virt() and haven't been
837 * fixed yet so I need to define it here.
838 */
839 #ifdef CONFIG_PPC32
840
virt_to_bus(volatile void * address)841 static inline unsigned long virt_to_bus(volatile void * address)
842 {
843 if (address == NULL)
844 return 0;
845 return __pa(address) + PCI_DRAM_OFFSET;
846 }
847
bus_to_virt(unsigned long address)848 static inline void * bus_to_virt(unsigned long address)
849 {
850 if (address == 0)
851 return NULL;
852 return __va(address - PCI_DRAM_OFFSET);
853 }
854
855 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
856
857 #endif /* CONFIG_PPC32 */
858
859 /* access ports */
860 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
861 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
862
863 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
864 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
865
866 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
867 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
868
869 /* Clear and set bits in one shot. These macros can be used to clear and
870 * set multiple bits in a register using a single read-modify-write. These
871 * macros can also be used to set a multiple-bit bit pattern using a mask,
872 * by specifying the mask in the 'clear' parameter and the new bit pattern
873 * in the 'set' parameter.
874 */
875
876 #define clrsetbits(type, addr, clear, set) \
877 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
878
879 #ifdef __powerpc64__
880 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
881 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
882 #endif
883
884 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
885 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
886
887 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
888 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
889
890 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
891
892 #endif /* __KERNEL__ */
893
894 #endif /* _ASM_POWERPC_IO_H */
895