1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
8 */
9
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/sched.h>
13 #include <linux/irqdomain.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17
18 #include <asm/bootinfo.h>
19 #include <asm/irq_cpu.h>
20
21 #include <lantiq_soc.h>
22 #include <irq.h>
23
24 /* register definitions - internal irqs */
25 #define LTQ_ICU_IM0_ISR 0x0000
26 #define LTQ_ICU_IM0_IER 0x0008
27 #define LTQ_ICU_IM0_IOSR 0x0010
28 #define LTQ_ICU_IM0_IRSR 0x0018
29 #define LTQ_ICU_IM0_IMR 0x0020
30 #define LTQ_ICU_IM1_ISR 0x0028
31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
32
33 /* register definitions - external irqs */
34 #define LTQ_EIU_EXIN_C 0x0000
35 #define LTQ_EIU_EXIN_INIC 0x0004
36 #define LTQ_EIU_EXIN_INC 0x0008
37 #define LTQ_EIU_EXIN_INEN 0x000C
38
39 /* number of external interrupts */
40 #define MAX_EIU 6
41
42 /* the performance counter */
43 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
44
45 /*
46 * irqs generated by devices attached to the EBU need to be acked in
47 * a special manner
48 */
49 #define LTQ_ICU_EBU_IRQ 22
50
51 #define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
52 #define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
53
54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
56
57 /* our 2 ipi interrupts for VSMP */
58 #define MIPS_CPU_IPI_RESCHED_IRQ 0
59 #define MIPS_CPU_IPI_CALL_IRQ 1
60
61 /* we have a cascade of 8 irqs */
62 #define MIPS_CPU_IRQ_CASCADE 8
63
64 static int exin_avail;
65 static u32 ltq_eiu_irq[MAX_EIU];
66 static void __iomem *ltq_icu_membase[MAX_IM];
67 static void __iomem *ltq_eiu_membase;
68 static struct irq_domain *ltq_domain;
69 static int ltq_perfcount_irq;
70
ltq_eiu_get_irq(int exin)71 int ltq_eiu_get_irq(int exin)
72 {
73 if (exin < exin_avail)
74 return ltq_eiu_irq[exin];
75 return -1;
76 }
77
ltq_disable_irq(struct irq_data * d)78 void ltq_disable_irq(struct irq_data *d)
79 {
80 u32 ier = LTQ_ICU_IM0_IER;
81 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
82 int im = offset / INT_NUM_IM_OFFSET;
83
84 offset %= INT_NUM_IM_OFFSET;
85 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
86 }
87
ltq_mask_and_ack_irq(struct irq_data * d)88 void ltq_mask_and_ack_irq(struct irq_data *d)
89 {
90 u32 ier = LTQ_ICU_IM0_IER;
91 u32 isr = LTQ_ICU_IM0_ISR;
92 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
93 int im = offset / INT_NUM_IM_OFFSET;
94
95 offset %= INT_NUM_IM_OFFSET;
96 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
97 ltq_icu_w32(im, BIT(offset), isr);
98 }
99
ltq_ack_irq(struct irq_data * d)100 static void ltq_ack_irq(struct irq_data *d)
101 {
102 u32 isr = LTQ_ICU_IM0_ISR;
103 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
104 int im = offset / INT_NUM_IM_OFFSET;
105
106 offset %= INT_NUM_IM_OFFSET;
107 ltq_icu_w32(im, BIT(offset), isr);
108 }
109
ltq_enable_irq(struct irq_data * d)110 void ltq_enable_irq(struct irq_data *d)
111 {
112 u32 ier = LTQ_ICU_IM0_IER;
113 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
114 int im = offset / INT_NUM_IM_OFFSET;
115
116 offset %= INT_NUM_IM_OFFSET;
117 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
118 }
119
ltq_eiu_settype(struct irq_data * d,unsigned int type)120 static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
121 {
122 int i;
123
124 for (i = 0; i < exin_avail; i++) {
125 if (d->hwirq == ltq_eiu_irq[i]) {
126 int val = 0;
127 int edge = 0;
128
129 switch (type) {
130 case IRQF_TRIGGER_NONE:
131 break;
132 case IRQF_TRIGGER_RISING:
133 val = 1;
134 edge = 1;
135 break;
136 case IRQF_TRIGGER_FALLING:
137 val = 2;
138 edge = 1;
139 break;
140 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
141 val = 3;
142 edge = 1;
143 break;
144 case IRQF_TRIGGER_HIGH:
145 val = 5;
146 break;
147 case IRQF_TRIGGER_LOW:
148 val = 6;
149 break;
150 default:
151 pr_err("invalid type %d for irq %ld\n",
152 type, d->hwirq);
153 return -EINVAL;
154 }
155
156 if (edge)
157 irq_set_handler(d->hwirq, handle_edge_irq);
158
159 ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
160 (~(7 << (i * 4)))) | (val << (i * 4)),
161 LTQ_EIU_EXIN_C);
162 }
163 }
164
165 return 0;
166 }
167
ltq_startup_eiu_irq(struct irq_data * d)168 static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
169 {
170 int i;
171
172 ltq_enable_irq(d);
173 for (i = 0; i < exin_avail; i++) {
174 if (d->hwirq == ltq_eiu_irq[i]) {
175 /* by default we are low level triggered */
176 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
177 /* clear all pending */
178 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
179 LTQ_EIU_EXIN_INC);
180 /* enable */
181 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
182 LTQ_EIU_EXIN_INEN);
183 break;
184 }
185 }
186
187 return 0;
188 }
189
ltq_shutdown_eiu_irq(struct irq_data * d)190 static void ltq_shutdown_eiu_irq(struct irq_data *d)
191 {
192 int i;
193
194 ltq_disable_irq(d);
195 for (i = 0; i < exin_avail; i++) {
196 if (d->hwirq == ltq_eiu_irq[i]) {
197 /* disable */
198 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
199 LTQ_EIU_EXIN_INEN);
200 break;
201 }
202 }
203 }
204
205 static struct irq_chip ltq_irq_type = {
206 .name = "icu",
207 .irq_enable = ltq_enable_irq,
208 .irq_disable = ltq_disable_irq,
209 .irq_unmask = ltq_enable_irq,
210 .irq_ack = ltq_ack_irq,
211 .irq_mask = ltq_disable_irq,
212 .irq_mask_ack = ltq_mask_and_ack_irq,
213 };
214
215 static struct irq_chip ltq_eiu_type = {
216 .name = "eiu",
217 .irq_startup = ltq_startup_eiu_irq,
218 .irq_shutdown = ltq_shutdown_eiu_irq,
219 .irq_enable = ltq_enable_irq,
220 .irq_disable = ltq_disable_irq,
221 .irq_unmask = ltq_enable_irq,
222 .irq_ack = ltq_ack_irq,
223 .irq_mask = ltq_disable_irq,
224 .irq_mask_ack = ltq_mask_and_ack_irq,
225 .irq_set_type = ltq_eiu_settype,
226 };
227
ltq_hw_irq_handler(struct irq_desc * desc)228 static void ltq_hw_irq_handler(struct irq_desc *desc)
229 {
230 int module = irq_desc_get_irq(desc) - 2;
231 u32 irq;
232 int hwirq;
233
234 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
235 if (irq == 0)
236 return;
237
238 /*
239 * silicon bug causes only the msb set to 1 to be valid. all
240 * other bits might be bogus
241 */
242 irq = __fls(irq);
243 hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
244 generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
245
246 /* if this is a EBU irq, we need to ack it or get a deadlock */
247 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
248 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
249 LTQ_EBU_PCC_ISTAT);
250 }
251
icu_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)252 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
253 {
254 struct irq_chip *chip = <q_irq_type;
255 int i;
256
257 if (hw < MIPS_CPU_IRQ_CASCADE)
258 return 0;
259
260 for (i = 0; i < exin_avail; i++)
261 if (hw == ltq_eiu_irq[i])
262 chip = <q_eiu_type;
263
264 irq_set_chip_and_handler(irq, chip, handle_level_irq);
265
266 return 0;
267 }
268
269 static const struct irq_domain_ops irq_domain_ops = {
270 .xlate = irq_domain_xlate_onetwocell,
271 .map = icu_map,
272 };
273
icu_of_init(struct device_node * node,struct device_node * parent)274 int __init icu_of_init(struct device_node *node, struct device_node *parent)
275 {
276 struct device_node *eiu_node;
277 struct resource res;
278 int i, ret;
279
280 for (i = 0; i < MAX_IM; i++) {
281 if (of_address_to_resource(node, i, &res))
282 panic("Failed to get icu memory range");
283
284 if (!request_mem_region(res.start, resource_size(&res),
285 res.name))
286 pr_err("Failed to request icu memory");
287
288 ltq_icu_membase[i] = ioremap_nocache(res.start,
289 resource_size(&res));
290 if (!ltq_icu_membase[i])
291 panic("Failed to remap icu memory");
292 }
293
294 /* turn off all irqs by default */
295 for (i = 0; i < MAX_IM; i++) {
296 /* make sure all irqs are turned off by default */
297 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
298 /* clear all possibly pending interrupts */
299 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
300 }
301
302 mips_cpu_irq_init();
303
304 for (i = 0; i < MAX_IM; i++)
305 irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
306
307 ltq_domain = irq_domain_add_linear(node,
308 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
309 &irq_domain_ops, 0);
310
311 /* tell oprofile which irq to use */
312 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
313
314 /*
315 * if the timer irq is not one of the mips irqs we need to
316 * create a mapping
317 */
318 if (MIPS_CPU_TIMER_IRQ != 7)
319 irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
320
321 /* the external interrupts are optional and xway only */
322 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
323 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
324 /* find out how many external irq sources we have */
325 exin_avail = of_property_count_u32_elems(eiu_node,
326 "lantiq,eiu-irqs");
327
328 if (exin_avail > MAX_EIU)
329 exin_avail = MAX_EIU;
330
331 ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
332 ltq_eiu_irq, exin_avail);
333 if (ret)
334 panic("failed to load external irq resources");
335
336 if (!request_mem_region(res.start, resource_size(&res),
337 res.name))
338 pr_err("Failed to request eiu memory");
339
340 ltq_eiu_membase = ioremap_nocache(res.start,
341 resource_size(&res));
342 if (!ltq_eiu_membase)
343 panic("Failed to remap eiu memory");
344 }
345
346 return 0;
347 }
348
get_c0_perfcount_int(void)349 int get_c0_perfcount_int(void)
350 {
351 return ltq_perfcount_irq;
352 }
353 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
354
get_c0_compare_int(void)355 unsigned int get_c0_compare_int(void)
356 {
357 return MIPS_CPU_TIMER_IRQ;
358 }
359
360 static struct of_device_id __initdata of_irq_ids[] = {
361 { .compatible = "lantiq,icu", .data = icu_of_init },
362 {},
363 };
364
arch_init_irq(void)365 void __init arch_init_irq(void)
366 {
367 of_irq_init(of_irq_ids);
368 }
369