1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/linkage.h>
3 #include <linux/errno.h>
4 #include <linux/signal.h>
5 #include <linux/sched.h>
6 #include <linux/ioport.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/timex.h>
10 #include <linux/random.h>
11 #include <linux/init.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
14 #include <linux/bitops.h>
15 #include <linux/acpi.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18
19 #include <linux/atomic.h>
20 #include <asm/timer.h>
21 #include <asm/hw_irq.h>
22 #include <asm/pgtable.h>
23 #include <asm/desc.h>
24 #include <asm/apic.h>
25 #include <asm/i8259.h>
26
27 /*
28 * This is the 'legacy' 8259A Programmable Interrupt Controller,
29 * present in the majority of PC/AT boxes.
30 * plus some generic x86 specific things if generic specifics makes
31 * any sense at all.
32 */
33 static void init_8259A(int auto_eoi);
34
35 static int i8259A_auto_eoi;
36 DEFINE_RAW_SPINLOCK(i8259A_lock);
37
38 /*
39 * 8259A PIC functions to handle ISA devices:
40 */
41
42 /*
43 * This contains the irq mask for both 8259A irq controllers,
44 */
45 unsigned int cached_irq_mask = 0xffff;
46
47 /*
48 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
49 * boards the timer interrupt is not really connected to any IO-APIC pin,
50 * it's fed to the master 8259A's IR0 line only.
51 *
52 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
53 * this 'mixed mode' IRQ handling costs nothing because it's only used
54 * at IRQ setup time.
55 */
56 unsigned long io_apic_irqs;
57
mask_8259A_irq(unsigned int irq)58 static void mask_8259A_irq(unsigned int irq)
59 {
60 unsigned int mask = 1 << irq;
61 unsigned long flags;
62
63 raw_spin_lock_irqsave(&i8259A_lock, flags);
64 cached_irq_mask |= mask;
65 if (irq & 8)
66 outb(cached_slave_mask, PIC_SLAVE_IMR);
67 else
68 outb(cached_master_mask, PIC_MASTER_IMR);
69 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
70 }
71
disable_8259A_irq(struct irq_data * data)72 static void disable_8259A_irq(struct irq_data *data)
73 {
74 mask_8259A_irq(data->irq);
75 }
76
unmask_8259A_irq(unsigned int irq)77 static void unmask_8259A_irq(unsigned int irq)
78 {
79 unsigned int mask = ~(1 << irq);
80 unsigned long flags;
81
82 raw_spin_lock_irqsave(&i8259A_lock, flags);
83 cached_irq_mask &= mask;
84 if (irq & 8)
85 outb(cached_slave_mask, PIC_SLAVE_IMR);
86 else
87 outb(cached_master_mask, PIC_MASTER_IMR);
88 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
89 }
90
enable_8259A_irq(struct irq_data * data)91 static void enable_8259A_irq(struct irq_data *data)
92 {
93 unmask_8259A_irq(data->irq);
94 }
95
i8259A_irq_pending(unsigned int irq)96 static int i8259A_irq_pending(unsigned int irq)
97 {
98 unsigned int mask = 1<<irq;
99 unsigned long flags;
100 int ret;
101
102 raw_spin_lock_irqsave(&i8259A_lock, flags);
103 if (irq < 8)
104 ret = inb(PIC_MASTER_CMD) & mask;
105 else
106 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
107 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
108
109 return ret;
110 }
111
make_8259A_irq(unsigned int irq)112 static void make_8259A_irq(unsigned int irq)
113 {
114 disable_irq_nosync(irq);
115 io_apic_irqs &= ~(1<<irq);
116 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
117 enable_irq(irq);
118 }
119
120 /*
121 * This function assumes to be called rarely. Switching between
122 * 8259A registers is slow.
123 * This has to be protected by the irq controller spinlock
124 * before being called.
125 */
i8259A_irq_real(unsigned int irq)126 static inline int i8259A_irq_real(unsigned int irq)
127 {
128 int value;
129 int irqmask = 1<<irq;
130
131 if (irq < 8) {
132 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
133 value = inb(PIC_MASTER_CMD) & irqmask;
134 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
135 return value;
136 }
137 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
138 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
139 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
140 return value;
141 }
142
143 /*
144 * Careful! The 8259A is a fragile beast, it pretty
145 * much _has_ to be done exactly like this (mask it
146 * first, _then_ send the EOI, and the order of EOI
147 * to the two 8259s is important!
148 */
mask_and_ack_8259A(struct irq_data * data)149 static void mask_and_ack_8259A(struct irq_data *data)
150 {
151 unsigned int irq = data->irq;
152 unsigned int irqmask = 1 << irq;
153 unsigned long flags;
154
155 raw_spin_lock_irqsave(&i8259A_lock, flags);
156 /*
157 * Lightweight spurious IRQ detection. We do not want
158 * to overdo spurious IRQ handling - it's usually a sign
159 * of hardware problems, so we only do the checks we can
160 * do without slowing down good hardware unnecessarily.
161 *
162 * Note that IRQ7 and IRQ15 (the two spurious IRQs
163 * usually resulting from the 8259A-1|2 PICs) occur
164 * even if the IRQ is masked in the 8259A. Thus we
165 * can check spurious 8259A IRQs without doing the
166 * quite slow i8259A_irq_real() call for every IRQ.
167 * This does not cover 100% of spurious interrupts,
168 * but should be enough to warn the user that there
169 * is something bad going on ...
170 */
171 if (cached_irq_mask & irqmask)
172 goto spurious_8259A_irq;
173 cached_irq_mask |= irqmask;
174
175 handle_real_irq:
176 if (irq & 8) {
177 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
178 outb(cached_slave_mask, PIC_SLAVE_IMR);
179 /* 'Specific EOI' to slave */
180 outb(0x60+(irq&7), PIC_SLAVE_CMD);
181 /* 'Specific EOI' to master-IRQ2 */
182 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
183 } else {
184 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
185 outb(cached_master_mask, PIC_MASTER_IMR);
186 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
187 }
188 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
189 return;
190
191 spurious_8259A_irq:
192 /*
193 * this is the slow path - should happen rarely.
194 */
195 if (i8259A_irq_real(irq))
196 /*
197 * oops, the IRQ _is_ in service according to the
198 * 8259A - not spurious, go handle it.
199 */
200 goto handle_real_irq;
201
202 {
203 static int spurious_irq_mask;
204 /*
205 * At this point we can be sure the IRQ is spurious,
206 * lets ACK and report it. [once per IRQ]
207 */
208 if (!(spurious_irq_mask & irqmask)) {
209 printk(KERN_DEBUG
210 "spurious 8259A interrupt: IRQ%d.\n", irq);
211 spurious_irq_mask |= irqmask;
212 }
213 atomic_inc(&irq_err_count);
214 /*
215 * Theoretically we do not have to handle this IRQ,
216 * but in Linux this does not cause problems and is
217 * simpler for us.
218 */
219 goto handle_real_irq;
220 }
221 }
222
223 struct irq_chip i8259A_chip = {
224 .name = "XT-PIC",
225 .irq_mask = disable_8259A_irq,
226 .irq_disable = disable_8259A_irq,
227 .irq_unmask = enable_8259A_irq,
228 .irq_mask_ack = mask_and_ack_8259A,
229 };
230
231 static char irq_trigger[2];
232 /**
233 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
234 */
restore_ELCR(char * trigger)235 static void restore_ELCR(char *trigger)
236 {
237 outb(trigger[0], 0x4d0);
238 outb(trigger[1], 0x4d1);
239 }
240
save_ELCR(char * trigger)241 static void save_ELCR(char *trigger)
242 {
243 /* IRQ 0,1,2,8,13 are marked as reserved */
244 trigger[0] = inb(0x4d0) & 0xF8;
245 trigger[1] = inb(0x4d1) & 0xDE;
246 }
247
i8259A_resume(void)248 static void i8259A_resume(void)
249 {
250 init_8259A(i8259A_auto_eoi);
251 restore_ELCR(irq_trigger);
252 }
253
i8259A_suspend(void)254 static int i8259A_suspend(void)
255 {
256 save_ELCR(irq_trigger);
257 return 0;
258 }
259
i8259A_shutdown(void)260 static void i8259A_shutdown(void)
261 {
262 /* Put the i8259A into a quiescent state that
263 * the kernel initialization code can get it
264 * out of.
265 */
266 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
267 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
268 }
269
270 static struct syscore_ops i8259_syscore_ops = {
271 .suspend = i8259A_suspend,
272 .resume = i8259A_resume,
273 .shutdown = i8259A_shutdown,
274 };
275
mask_8259A(void)276 static void mask_8259A(void)
277 {
278 unsigned long flags;
279
280 raw_spin_lock_irqsave(&i8259A_lock, flags);
281
282 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
283 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
284
285 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
286 }
287
unmask_8259A(void)288 static void unmask_8259A(void)
289 {
290 unsigned long flags;
291
292 raw_spin_lock_irqsave(&i8259A_lock, flags);
293
294 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
295 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
296
297 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
298 }
299
probe_8259A(void)300 static int probe_8259A(void)
301 {
302 unsigned long flags;
303 unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
304 unsigned char new_val;
305 /*
306 * Check to see if we have a PIC.
307 * Mask all except the cascade and read
308 * back the value we just wrote. If we don't
309 * have a PIC, we will read 0xff as opposed to the
310 * value we wrote.
311 */
312 raw_spin_lock_irqsave(&i8259A_lock, flags);
313
314 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
315 outb(probe_val, PIC_MASTER_IMR);
316 new_val = inb(PIC_MASTER_IMR);
317 if (new_val != probe_val) {
318 printk(KERN_INFO "Using NULL legacy PIC\n");
319 legacy_pic = &null_legacy_pic;
320 }
321
322 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
323 return nr_legacy_irqs();
324 }
325
init_8259A(int auto_eoi)326 static void init_8259A(int auto_eoi)
327 {
328 unsigned long flags;
329
330 i8259A_auto_eoi = auto_eoi;
331
332 raw_spin_lock_irqsave(&i8259A_lock, flags);
333
334 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
335
336 /*
337 * outb_pic - this has to work on a wide range of PC hardware.
338 */
339 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
340
341 /* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
342 outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);
343
344 /* 8259A-1 (the master) has a slave on IR2 */
345 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
346
347 if (auto_eoi) /* master does Auto EOI */
348 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
349 else /* master expects normal EOI */
350 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
351
352 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
353
354 /* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
355 outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
356 /* 8259A-2 is a slave on master's IR2 */
357 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
358 /* (slave's support for AEOI in flat mode is to be investigated) */
359 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
360
361 if (auto_eoi)
362 /*
363 * In AEOI mode we just have to mask the interrupt
364 * when acking.
365 */
366 i8259A_chip.irq_mask_ack = disable_8259A_irq;
367 else
368 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
369
370 udelay(100); /* wait for 8259A to initialize */
371
372 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
373 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
374
375 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
376 }
377
378 /*
379 * make i8259 a driver so that we can select pic functions at run time. the goal
380 * is to make x86 binary compatible among pc compatible and non-pc compatible
381 * platforms, such as x86 MID.
382 */
383
legacy_pic_noop(void)384 static void legacy_pic_noop(void) { };
legacy_pic_uint_noop(unsigned int unused)385 static void legacy_pic_uint_noop(unsigned int unused) { };
legacy_pic_int_noop(int unused)386 static void legacy_pic_int_noop(int unused) { };
legacy_pic_irq_pending_noop(unsigned int irq)387 static int legacy_pic_irq_pending_noop(unsigned int irq)
388 {
389 return 0;
390 }
legacy_pic_probe(void)391 static int legacy_pic_probe(void)
392 {
393 return 0;
394 }
395
396 struct legacy_pic null_legacy_pic = {
397 .nr_legacy_irqs = 0,
398 .chip = &dummy_irq_chip,
399 .mask = legacy_pic_uint_noop,
400 .unmask = legacy_pic_uint_noop,
401 .mask_all = legacy_pic_noop,
402 .restore_mask = legacy_pic_noop,
403 .init = legacy_pic_int_noop,
404 .probe = legacy_pic_probe,
405 .irq_pending = legacy_pic_irq_pending_noop,
406 .make_irq = legacy_pic_uint_noop,
407 };
408
409 struct legacy_pic default_legacy_pic = {
410 .nr_legacy_irqs = NR_IRQS_LEGACY,
411 .chip = &i8259A_chip,
412 .mask = mask_8259A_irq,
413 .unmask = unmask_8259A_irq,
414 .mask_all = mask_8259A,
415 .restore_mask = unmask_8259A,
416 .init = init_8259A,
417 .probe = probe_8259A,
418 .irq_pending = i8259A_irq_pending,
419 .make_irq = make_8259A_irq,
420 };
421
422 struct legacy_pic *legacy_pic = &default_legacy_pic;
423 EXPORT_SYMBOL(legacy_pic);
424
i8259A_init_ops(void)425 static int __init i8259A_init_ops(void)
426 {
427 if (legacy_pic == &default_legacy_pic)
428 register_syscore_ops(&i8259_syscore_ops);
429
430 return 0;
431 }
432
433 device_initcall(i8259A_init_ops);
434