1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41
42 #define DRIVER_NAME "mlx5_core"
43 #define DRIVER_VERSION "5.0-0"
44
45 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs(mdev->pdev))
46 #define MLX5_VPORT_MANAGER(mdev) \
47 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
48 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
49 mlx5_core_is_pf(mdev))
50
51 extern uint mlx5_core_debug_mask;
52
53 #define mlx5_core_dbg(__dev, format, ...) \
54 dev_dbg(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
55 __func__, __LINE__, current->pid, \
56 ##__VA_ARGS__)
57
58 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
59 do { \
60 if ((mask) & mlx5_core_debug_mask) \
61 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
62 } while (0)
63
64 #define mlx5_core_err(__dev, format, ...) \
65 dev_err(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
66 __func__, __LINE__, current->pid, \
67 ##__VA_ARGS__)
68
69 #define mlx5_core_warn(__dev, format, ...) \
70 dev_warn(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
71 __func__, __LINE__, current->pid, \
72 ##__VA_ARGS__)
73
74 #define mlx5_core_info(__dev, format, ...) \
75 dev_info(&(__dev)->pdev->dev, format, ##__VA_ARGS__)
76
77 enum {
78 MLX5_CMD_DATA, /* print command payload only */
79 MLX5_CMD_TIME, /* print command execution time */
80 };
81
82 enum {
83 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
84 MLX5_DRIVER_SYND = 0xbadd00de,
85 };
86
87 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
88 int mlx5_query_board_id(struct mlx5_core_dev *dev);
89 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev);
90 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
91 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
92 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
93 unsigned long param);
94 void mlx5_core_page_fault(struct mlx5_core_dev *dev,
95 struct mlx5_pagefault *pfault);
96 void mlx5_port_module_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
97 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
98 void mlx5_disable_device(struct mlx5_core_dev *dev);
99 void mlx5_recover_device(struct mlx5_core_dev *dev);
100 int mlx5_sriov_init(struct mlx5_core_dev *dev);
101 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
102 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
103 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
104 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
105 bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev);
106 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
107 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
108 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
109 void *context, u32 *element_id);
110 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
111 void *context, u32 element_id,
112 u32 modify_bitmask);
113 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
114 u32 element_id);
115 int mlx5_wait_for_vf_pages(struct mlx5_core_dev *dev);
116 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev);
117 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn);
118 void mlx5_cq_tasklet_cb(unsigned long data);
119
120 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
121 u8 access_reg_group);
122 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
123 u8 access_reg_group);
124
125 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
126 void mlx5_lag_remove(struct mlx5_core_dev *dev);
127
128 void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
129 void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
130 void mlx5_attach_device(struct mlx5_core_dev *dev);
131 void mlx5_detach_device(struct mlx5_core_dev *dev);
132 bool mlx5_device_registered(struct mlx5_core_dev *dev);
133 int mlx5_register_device(struct mlx5_core_dev *dev);
134 void mlx5_unregister_device(struct mlx5_core_dev *dev);
135 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
136 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
137 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
138 void mlx5_dev_list_lock(void);
139 void mlx5_dev_list_unlock(void);
140 int mlx5_dev_list_trylock(void);
141 int mlx5_encap_alloc(struct mlx5_core_dev *dev,
142 int header_type,
143 size_t size,
144 void *encap_header,
145 u32 *encap_id);
146 void mlx5_encap_dealloc(struct mlx5_core_dev *dev, u32 encap_id);
147
148 int mlx5_modify_header_alloc(struct mlx5_core_dev *dev,
149 u8 namespace, u8 num_actions,
150 void *modify_actions, u32 *modify_header_id);
151 void mlx5_modify_header_dealloc(struct mlx5_core_dev *dev, u32 modify_header_id);
152
153 bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);
154
155 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
156 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
157 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
158 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
159
160 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
161 MLX5_CAP_GEN((mdev), pps_modify) && \
162 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
163 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
164
165 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw);
166
167 void mlx5e_init(void);
168 void mlx5e_cleanup(void);
169
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)170 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
171 {
172 /* LACP owner conditions:
173 * 1) Function is physical.
174 * 2) LAG is supported by FW.
175 * 3) LAG is managed by driver (currently the only option).
176 */
177 return MLX5_CAP_GEN(dev, vport_group_manager) &&
178 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
179 MLX5_CAP_GEN(dev, lag_master);
180 }
181
182 int mlx5_lag_allow(struct mlx5_core_dev *dev);
183 int mlx5_lag_forbid(struct mlx5_core_dev *dev);
184
185 #endif /* __MLX5_CORE_H__ */
186