1 /*
2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
3 * Steven J. Hill <sjhill@realitydiluted.com>
4 * Thomas Gleixner <tglx@linutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Info:
11 * Contains standard defines and IDs for NAND flash devices
12 *
13 * Changelog:
14 * See git changelog.
15 */
16 #ifndef __LINUX_MTD_RAWNAND_H
17 #define __LINUX_MTD_RAWNAND_H
18
19 #include <linux/wait.h>
20 #include <linux/spinlock.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
24
25 struct mtd_info;
26 struct nand_flash_dev;
27 struct device_node;
28
29 /* Scan and identify a NAND device */
30 int nand_scan(struct mtd_info *mtd, int max_chips);
31 /*
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
34 */
35 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
37 int nand_scan_tail(struct mtd_info *mtd);
38
39 /* Unregister the MTD device and free resources held by the NAND device */
40 void nand_release(struct mtd_info *mtd);
41
42 /* Internal helper for board drivers which need to override command function */
43 void nand_wait_ready(struct mtd_info *mtd);
44
45 /* The maximum number of NAND chips in an array */
46 #define NAND_MAX_CHIPS 8
47
48 /*
49 * Constants for hardware specific CLE/ALE/NCE function
50 *
51 * These are bits which can be or'ed to set/clear multiple
52 * bits in one go.
53 */
54 /* Select the chip by setting nCE to low */
55 #define NAND_NCE 0x01
56 /* Select the command latch by setting CLE to high */
57 #define NAND_CLE 0x02
58 /* Select the address latch by setting ALE to high */
59 #define NAND_ALE 0x04
60
61 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
62 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
63 #define NAND_CTRL_CHANGE 0x80
64
65 /*
66 * Standard NAND flash commands
67 */
68 #define NAND_CMD_READ0 0
69 #define NAND_CMD_READ1 1
70 #define NAND_CMD_RNDOUT 5
71 #define NAND_CMD_PAGEPROG 0x10
72 #define NAND_CMD_READOOB 0x50
73 #define NAND_CMD_ERASE1 0x60
74 #define NAND_CMD_STATUS 0x70
75 #define NAND_CMD_SEQIN 0x80
76 #define NAND_CMD_RNDIN 0x85
77 #define NAND_CMD_READID 0x90
78 #define NAND_CMD_ERASE2 0xd0
79 #define NAND_CMD_PARAM 0xec
80 #define NAND_CMD_GET_FEATURES 0xee
81 #define NAND_CMD_SET_FEATURES 0xef
82 #define NAND_CMD_RESET 0xff
83
84 /* Extended commands for large page devices */
85 #define NAND_CMD_READSTART 0x30
86 #define NAND_CMD_RNDOUTSTART 0xE0
87 #define NAND_CMD_CACHEDPROG 0x15
88
89 #define NAND_CMD_NONE -1
90
91 /* Status bits */
92 #define NAND_STATUS_FAIL 0x01
93 #define NAND_STATUS_FAIL_N1 0x02
94 #define NAND_STATUS_TRUE_READY 0x20
95 #define NAND_STATUS_READY 0x40
96 #define NAND_STATUS_WP 0x80
97
98 #define NAND_DATA_IFACE_CHECK_ONLY -1
99
100 /*
101 * Constants for ECC_MODES
102 */
103 typedef enum {
104 NAND_ECC_NONE,
105 NAND_ECC_SOFT,
106 NAND_ECC_HW,
107 NAND_ECC_HW_SYNDROME,
108 NAND_ECC_HW_OOB_FIRST,
109 NAND_ECC_ON_DIE,
110 } nand_ecc_modes_t;
111
112 enum nand_ecc_algo {
113 NAND_ECC_UNKNOWN,
114 NAND_ECC_HAMMING,
115 NAND_ECC_BCH,
116 };
117
118 /*
119 * Constants for Hardware ECC
120 */
121 /* Reset Hardware ECC for read */
122 #define NAND_ECC_READ 0
123 /* Reset Hardware ECC for write */
124 #define NAND_ECC_WRITE 1
125 /* Enable Hardware ECC before syndrome is read back from flash */
126 #define NAND_ECC_READSYN 2
127
128 /*
129 * Enable generic NAND 'page erased' check. This check is only done when
130 * ecc.correct() returns -EBADMSG.
131 * Set this flag if your implementation does not fix bitflips in erased
132 * pages and you want to rely on the default implementation.
133 */
134 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
135 #define NAND_ECC_MAXIMIZE BIT(1)
136 /*
137 * If your controller already sends the required NAND commands when
138 * reading or writing a page, then the framework is not supposed to
139 * send READ0 and SEQIN/PAGEPROG respectively.
140 */
141 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
142
143 /* Bit mask for flags passed to do_nand_read_ecc */
144 #define NAND_GET_DEVICE 0x80
145
146
147 /*
148 * Option constants for bizarre disfunctionality and real
149 * features.
150 */
151 /* Buswidth is 16 bit */
152 #define NAND_BUSWIDTH_16 0x00000002
153 /* Chip has cache program function */
154 #define NAND_CACHEPRG 0x00000008
155 /*
156 * Chip requires ready check on read (for auto-incremented sequential read).
157 * True only for small page devices; large page devices do not support
158 * autoincrement.
159 */
160 #define NAND_NEED_READRDY 0x00000100
161
162 /* Chip does not allow subpage writes */
163 #define NAND_NO_SUBPAGE_WRITE 0x00000200
164
165 /* Device is one of 'new' xD cards that expose fake nand command set */
166 #define NAND_BROKEN_XD 0x00000400
167
168 /* Device behaves just like nand, but is readonly */
169 #define NAND_ROM 0x00000800
170
171 /* Device supports subpage reads */
172 #define NAND_SUBPAGE_READ 0x00001000
173
174 /*
175 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
176 * patterns.
177 */
178 #define NAND_NEED_SCRAMBLING 0x00002000
179
180 /* Options valid for Samsung large page devices */
181 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
182
183 /* Macros to identify the above */
184 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
185 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
186 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
187
188 /* Non chip related options */
189 /* This option skips the bbt scan during initialization. */
190 #define NAND_SKIP_BBTSCAN 0x00010000
191 /*
192 * This option is defined if the board driver allocates its own buffers
193 * (e.g. because it needs them DMA-coherent).
194 */
195 #define NAND_OWN_BUFFERS 0x00020000
196 /* Chip may not exist, so silence any errors in scan */
197 #define NAND_SCAN_SILENT_NODEV 0x00040000
198 /*
199 * Autodetect nand buswidth with readid/onfi.
200 * This suppose the driver will configure the hardware in 8 bits mode
201 * when calling nand_scan_ident, and update its configuration
202 * before calling nand_scan_tail.
203 */
204 #define NAND_BUSWIDTH_AUTO 0x00080000
205 /*
206 * This option could be defined by controller drivers to protect against
207 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
208 */
209 #define NAND_USE_BOUNCE_BUFFER 0x00100000
210
211 /*
212 * In case your controller is implementing ->cmd_ctrl() and is relying on the
213 * default ->cmdfunc() implementation, you may want to let the core handle the
214 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
215 * requested.
216 * If your controller already takes care of this delay, you don't need to set
217 * this flag.
218 */
219 #define NAND_WAIT_TCCS 0x00200000
220
221 /* Options set by nand scan */
222 /* Nand scan has allocated controller struct */
223 #define NAND_CONTROLLER_ALLOC 0x80000000
224
225 /* Cell info constants */
226 #define NAND_CI_CHIPNR_MSK 0x03
227 #define NAND_CI_CELLTYPE_MSK 0x0C
228 #define NAND_CI_CELLTYPE_SHIFT 2
229
230 /* Keep gcc happy */
231 struct nand_chip;
232
233 /* ONFI features */
234 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
235 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
236
237 /* ONFI timing mode, used in both asynchronous and synchronous mode */
238 #define ONFI_TIMING_MODE_0 (1 << 0)
239 #define ONFI_TIMING_MODE_1 (1 << 1)
240 #define ONFI_TIMING_MODE_2 (1 << 2)
241 #define ONFI_TIMING_MODE_3 (1 << 3)
242 #define ONFI_TIMING_MODE_4 (1 << 4)
243 #define ONFI_TIMING_MODE_5 (1 << 5)
244 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
245
246 /* ONFI feature address */
247 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
248
249 /* Vendor-specific feature address (Micron) */
250 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
251 #define ONFI_FEATURE_ON_DIE_ECC 0x90
252 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
253
254 /* ONFI subfeature parameters length */
255 #define ONFI_SUBFEATURE_PARAM_LEN 4
256
257 /* ONFI optional commands SET/GET FEATURES supported? */
258 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
259
260 struct nand_onfi_params {
261 /* rev info and features block */
262 /* 'O' 'N' 'F' 'I' */
263 u8 sig[4];
264 __le16 revision;
265 __le16 features;
266 __le16 opt_cmd;
267 u8 reserved0[2];
268 __le16 ext_param_page_length; /* since ONFI 2.1 */
269 u8 num_of_param_pages; /* since ONFI 2.1 */
270 u8 reserved1[17];
271
272 /* manufacturer information block */
273 char manufacturer[12];
274 char model[20];
275 u8 jedec_id;
276 __le16 date_code;
277 u8 reserved2[13];
278
279 /* memory organization block */
280 __le32 byte_per_page;
281 __le16 spare_bytes_per_page;
282 __le32 data_bytes_per_ppage;
283 __le16 spare_bytes_per_ppage;
284 __le32 pages_per_block;
285 __le32 blocks_per_lun;
286 u8 lun_count;
287 u8 addr_cycles;
288 u8 bits_per_cell;
289 __le16 bb_per_lun;
290 __le16 block_endurance;
291 u8 guaranteed_good_blocks;
292 __le16 guaranteed_block_endurance;
293 u8 programs_per_page;
294 u8 ppage_attr;
295 u8 ecc_bits;
296 u8 interleaved_bits;
297 u8 interleaved_ops;
298 u8 reserved3[13];
299
300 /* electrical parameter block */
301 u8 io_pin_capacitance_max;
302 __le16 async_timing_mode;
303 __le16 program_cache_timing_mode;
304 __le16 t_prog;
305 __le16 t_bers;
306 __le16 t_r;
307 __le16 t_ccs;
308 __le16 src_sync_timing_mode;
309 u8 src_ssync_features;
310 __le16 clk_pin_capacitance_typ;
311 __le16 io_pin_capacitance_typ;
312 __le16 input_pin_capacitance_typ;
313 u8 input_pin_capacitance_max;
314 u8 driver_strength_support;
315 __le16 t_int_r;
316 __le16 t_adl;
317 u8 reserved4[8];
318
319 /* vendor */
320 __le16 vendor_revision;
321 u8 vendor[88];
322
323 __le16 crc;
324 } __packed;
325
326 #define ONFI_CRC_BASE 0x4F4E
327
328 /* Extended ECC information Block Definition (since ONFI 2.1) */
329 struct onfi_ext_ecc_info {
330 u8 ecc_bits;
331 u8 codeword_size;
332 __le16 bb_per_lun;
333 __le16 block_endurance;
334 u8 reserved[2];
335 } __packed;
336
337 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
338 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
339 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
340 struct onfi_ext_section {
341 u8 type;
342 u8 length;
343 } __packed;
344
345 #define ONFI_EXT_SECTION_MAX 8
346
347 /* Extended Parameter Page Definition (since ONFI 2.1) */
348 struct onfi_ext_param_page {
349 __le16 crc;
350 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
351 u8 reserved0[10];
352 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
353
354 /*
355 * The actual size of the Extended Parameter Page is in
356 * @ext_param_page_length of nand_onfi_params{}.
357 * The following are the variable length sections.
358 * So we do not add any fields below. Please see the ONFI spec.
359 */
360 } __packed;
361
362 struct jedec_ecc_info {
363 u8 ecc_bits;
364 u8 codeword_size;
365 __le16 bb_per_lun;
366 __le16 block_endurance;
367 u8 reserved[2];
368 } __packed;
369
370 /* JEDEC features */
371 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
372
373 struct nand_jedec_params {
374 /* rev info and features block */
375 /* 'J' 'E' 'S' 'D' */
376 u8 sig[4];
377 __le16 revision;
378 __le16 features;
379 u8 opt_cmd[3];
380 __le16 sec_cmd;
381 u8 num_of_param_pages;
382 u8 reserved0[18];
383
384 /* manufacturer information block */
385 char manufacturer[12];
386 char model[20];
387 u8 jedec_id[6];
388 u8 reserved1[10];
389
390 /* memory organization block */
391 __le32 byte_per_page;
392 __le16 spare_bytes_per_page;
393 u8 reserved2[6];
394 __le32 pages_per_block;
395 __le32 blocks_per_lun;
396 u8 lun_count;
397 u8 addr_cycles;
398 u8 bits_per_cell;
399 u8 programs_per_page;
400 u8 multi_plane_addr;
401 u8 multi_plane_op_attr;
402 u8 reserved3[38];
403
404 /* electrical parameter block */
405 __le16 async_sdr_speed_grade;
406 __le16 toggle_ddr_speed_grade;
407 __le16 sync_ddr_speed_grade;
408 u8 async_sdr_features;
409 u8 toggle_ddr_features;
410 u8 sync_ddr_features;
411 __le16 t_prog;
412 __le16 t_bers;
413 __le16 t_r;
414 __le16 t_r_multi_plane;
415 __le16 t_ccs;
416 __le16 io_pin_capacitance_typ;
417 __le16 input_pin_capacitance_typ;
418 __le16 clk_pin_capacitance_typ;
419 u8 driver_strength_support;
420 __le16 t_adl;
421 u8 reserved4[36];
422
423 /* ECC and endurance block */
424 u8 guaranteed_good_blocks;
425 __le16 guaranteed_block_endurance;
426 struct jedec_ecc_info ecc_info[4];
427 u8 reserved5[29];
428
429 /* reserved */
430 u8 reserved6[148];
431
432 /* vendor */
433 __le16 vendor_rev_num;
434 u8 reserved7[88];
435
436 /* CRC for Parameter Page */
437 __le16 crc;
438 } __packed;
439
440 /* The maximum expected count of bytes in the NAND ID sequence */
441 #define NAND_MAX_ID_LEN 8
442
443 /**
444 * struct nand_id - NAND id structure
445 * @data: buffer containing the id bytes.
446 * @len: ID length.
447 */
448 struct nand_id {
449 u8 data[NAND_MAX_ID_LEN];
450 int len;
451 };
452
453 /**
454 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
455 * @lock: protection lock
456 * @active: the mtd device which holds the controller currently
457 * @wq: wait queue to sleep on if a NAND operation is in
458 * progress used instead of the per chip wait queue
459 * when a hw controller is available.
460 */
461 struct nand_hw_control {
462 spinlock_t lock;
463 struct nand_chip *active;
464 wait_queue_head_t wq;
465 };
466
nand_hw_control_init(struct nand_hw_control * nfc)467 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
468 {
469 nfc->active = NULL;
470 spin_lock_init(&nfc->lock);
471 init_waitqueue_head(&nfc->wq);
472 }
473
474 /**
475 * struct nand_ecc_step_info - ECC step information of ECC engine
476 * @stepsize: data bytes per ECC step
477 * @strengths: array of supported strengths
478 * @nstrengths: number of supported strengths
479 */
480 struct nand_ecc_step_info {
481 int stepsize;
482 const int *strengths;
483 int nstrengths;
484 };
485
486 /**
487 * struct nand_ecc_caps - capability of ECC engine
488 * @stepinfos: array of ECC step information
489 * @nstepinfos: number of ECC step information
490 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
491 */
492 struct nand_ecc_caps {
493 const struct nand_ecc_step_info *stepinfos;
494 int nstepinfos;
495 int (*calc_ecc_bytes)(int step_size, int strength);
496 };
497
498 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
499 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
500 static const int __name##_strengths[] = { __VA_ARGS__ }; \
501 static const struct nand_ecc_step_info __name##_stepinfo = { \
502 .stepsize = __step, \
503 .strengths = __name##_strengths, \
504 .nstrengths = ARRAY_SIZE(__name##_strengths), \
505 }; \
506 static const struct nand_ecc_caps __name = { \
507 .stepinfos = &__name##_stepinfo, \
508 .nstepinfos = 1, \
509 .calc_ecc_bytes = __calc, \
510 }
511
512 /**
513 * struct nand_ecc_ctrl - Control structure for ECC
514 * @mode: ECC mode
515 * @algo: ECC algorithm
516 * @steps: number of ECC steps per page
517 * @size: data bytes per ECC step
518 * @bytes: ECC bytes per step
519 * @strength: max number of correctible bits per ECC step
520 * @total: total number of ECC bytes per page
521 * @prepad: padding information for syndrome based ECC generators
522 * @postpad: padding information for syndrome based ECC generators
523 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
524 * @priv: pointer to private ECC control data
525 * @hwctl: function to control hardware ECC generator. Must only
526 * be provided if an hardware ECC is available
527 * @calculate: function for ECC calculation or readback from ECC hardware
528 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
529 * Should return a positive number representing the number of
530 * corrected bitflips, -EBADMSG if the number of bitflips exceed
531 * ECC strength, or any other error code if the error is not
532 * directly related to correction.
533 * If -EBADMSG is returned the input buffers should be left
534 * untouched.
535 * @read_page_raw: function to read a raw page without ECC. This function
536 * should hide the specific layout used by the ECC
537 * controller and always return contiguous in-band and
538 * out-of-band data even if they're not stored
539 * contiguously on the NAND chip (e.g.
540 * NAND_ECC_HW_SYNDROME interleaves in-band and
541 * out-of-band data).
542 * @write_page_raw: function to write a raw page without ECC. This function
543 * should hide the specific layout used by the ECC
544 * controller and consider the passed data as contiguous
545 * in-band and out-of-band data. ECC controller is
546 * responsible for doing the appropriate transformations
547 * to adapt to its specific layout (e.g.
548 * NAND_ECC_HW_SYNDROME interleaves in-band and
549 * out-of-band data).
550 * @read_page: function to read a page according to the ECC generator
551 * requirements; returns maximum number of bitflips corrected in
552 * any single ECC step, -EIO hw error
553 * @read_subpage: function to read parts of the page covered by ECC;
554 * returns same as read_page()
555 * @write_subpage: function to write parts of the page covered by ECC.
556 * @write_page: function to write a page according to the ECC generator
557 * requirements.
558 * @write_oob_raw: function to write chip OOB data without ECC
559 * @read_oob_raw: function to read chip OOB data without ECC
560 * @read_oob: function to read chip OOB data
561 * @write_oob: function to write chip OOB data
562 */
563 struct nand_ecc_ctrl {
564 nand_ecc_modes_t mode;
565 enum nand_ecc_algo algo;
566 int steps;
567 int size;
568 int bytes;
569 int total;
570 int strength;
571 int prepad;
572 int postpad;
573 unsigned int options;
574 void *priv;
575 void (*hwctl)(struct mtd_info *mtd, int mode);
576 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
577 uint8_t *ecc_code);
578 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
579 uint8_t *calc_ecc);
580 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
581 uint8_t *buf, int oob_required, int page);
582 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
583 const uint8_t *buf, int oob_required, int page);
584 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
585 uint8_t *buf, int oob_required, int page);
586 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
587 uint32_t offs, uint32_t len, uint8_t *buf, int page);
588 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
589 uint32_t offset, uint32_t data_len,
590 const uint8_t *data_buf, int oob_required, int page);
591 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
592 const uint8_t *buf, int oob_required, int page);
593 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
594 int page);
595 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
596 int page);
597 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
598 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
599 int page);
600 };
601
nand_standard_page_accessors(struct nand_ecc_ctrl * ecc)602 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
603 {
604 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
605 }
606
607 /**
608 * struct nand_buffers - buffer structure for read/write
609 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
610 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
611 * @databuf: buffer pointer for data, size is (page size + oobsize).
612 *
613 * Do not change the order of buffers. databuf and oobrbuf must be in
614 * consecutive order.
615 */
616 struct nand_buffers {
617 uint8_t *ecccalc;
618 uint8_t *ecccode;
619 uint8_t *databuf;
620 };
621
622 /**
623 * struct nand_sdr_timings - SDR NAND chip timings
624 *
625 * This struct defines the timing requirements of a SDR NAND chip.
626 * These information can be found in every NAND datasheets and the timings
627 * meaning are described in the ONFI specifications:
628 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
629 * Parameters)
630 *
631 * All these timings are expressed in picoseconds.
632 *
633 * @tBERS_max: Block erase time
634 * @tCCS_min: Change column setup time
635 * @tPROG_max: Page program time
636 * @tR_max: Page read time
637 * @tALH_min: ALE hold time
638 * @tADL_min: ALE to data loading time
639 * @tALS_min: ALE setup time
640 * @tAR_min: ALE to RE# delay
641 * @tCEA_max: CE# access time
642 * @tCEH_min: CE# high hold time
643 * @tCH_min: CE# hold time
644 * @tCHZ_max: CE# high to output hi-Z
645 * @tCLH_min: CLE hold time
646 * @tCLR_min: CLE to RE# delay
647 * @tCLS_min: CLE setup time
648 * @tCOH_min: CE# high to output hold
649 * @tCS_min: CE# setup time
650 * @tDH_min: Data hold time
651 * @tDS_min: Data setup time
652 * @tFEAT_max: Busy time for Set Features and Get Features
653 * @tIR_min: Output hi-Z to RE# low
654 * @tITC_max: Interface and Timing Mode Change time
655 * @tRC_min: RE# cycle time
656 * @tREA_max: RE# access time
657 * @tREH_min: RE# high hold time
658 * @tRHOH_min: RE# high to output hold
659 * @tRHW_min: RE# high to WE# low
660 * @tRHZ_max: RE# high to output hi-Z
661 * @tRLOH_min: RE# low to output hold
662 * @tRP_min: RE# pulse width
663 * @tRR_min: Ready to RE# low (data only)
664 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
665 * rising edge of R/B#.
666 * @tWB_max: WE# high to SR[6] low
667 * @tWC_min: WE# cycle time
668 * @tWH_min: WE# high hold time
669 * @tWHR_min: WE# high to RE# low
670 * @tWP_min: WE# pulse width
671 * @tWW_min: WP# transition to WE# low
672 */
673 struct nand_sdr_timings {
674 u64 tBERS_max;
675 u32 tCCS_min;
676 u64 tPROG_max;
677 u64 tR_max;
678 u32 tALH_min;
679 u32 tADL_min;
680 u32 tALS_min;
681 u32 tAR_min;
682 u32 tCEA_max;
683 u32 tCEH_min;
684 u32 tCH_min;
685 u32 tCHZ_max;
686 u32 tCLH_min;
687 u32 tCLR_min;
688 u32 tCLS_min;
689 u32 tCOH_min;
690 u32 tCS_min;
691 u32 tDH_min;
692 u32 tDS_min;
693 u32 tFEAT_max;
694 u32 tIR_min;
695 u32 tITC_max;
696 u32 tRC_min;
697 u32 tREA_max;
698 u32 tREH_min;
699 u32 tRHOH_min;
700 u32 tRHW_min;
701 u32 tRHZ_max;
702 u32 tRLOH_min;
703 u32 tRP_min;
704 u32 tRR_min;
705 u64 tRST_max;
706 u32 tWB_max;
707 u32 tWC_min;
708 u32 tWH_min;
709 u32 tWHR_min;
710 u32 tWP_min;
711 u32 tWW_min;
712 };
713
714 /**
715 * enum nand_data_interface_type - NAND interface timing type
716 * @NAND_SDR_IFACE: Single Data Rate interface
717 */
718 enum nand_data_interface_type {
719 NAND_SDR_IFACE,
720 };
721
722 /**
723 * struct nand_data_interface - NAND interface timing
724 * @type: type of the timing
725 * @timings: The timing, type according to @type
726 */
727 struct nand_data_interface {
728 enum nand_data_interface_type type;
729 union {
730 struct nand_sdr_timings sdr;
731 } timings;
732 };
733
734 /**
735 * nand_get_sdr_timings - get SDR timing from data interface
736 * @conf: The data interface
737 */
738 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)739 nand_get_sdr_timings(const struct nand_data_interface *conf)
740 {
741 if (conf->type != NAND_SDR_IFACE)
742 return ERR_PTR(-EINVAL);
743
744 return &conf->timings.sdr;
745 }
746
747 /**
748 * struct nand_manufacturer_ops - NAND Manufacturer operations
749 * @detect: detect the NAND memory organization and capabilities
750 * @init: initialize all vendor specific fields (like the ->read_retry()
751 * implementation) if any.
752 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
753 * is here to let vendor specific code release those resources.
754 */
755 struct nand_manufacturer_ops {
756 void (*detect)(struct nand_chip *chip);
757 int (*init)(struct nand_chip *chip);
758 void (*cleanup)(struct nand_chip *chip);
759 };
760
761 /**
762 * struct nand_chip - NAND Private Flash Chip Data
763 * @mtd: MTD device registered to the MTD framework
764 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
765 * flash device
766 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
767 * flash device.
768 * @read_byte: [REPLACEABLE] read one byte from the chip
769 * @read_word: [REPLACEABLE] read one word from the chip
770 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
771 * low 8 I/O lines
772 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
773 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
774 * @select_chip: [REPLACEABLE] select chip nr
775 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
776 * @block_markbad: [REPLACEABLE] mark a block bad
777 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
778 * ALE/CLE/nCE. Also used to write command and address
779 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
780 * device ready/busy line. If set to NULL no access to
781 * ready/busy is available and the ready/busy information
782 * is read from the chip status register.
783 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
784 * commands to the chip.
785 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
786 * ready.
787 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
788 * setting the read-retry mode. Mostly needed for MLC NAND.
789 * @ecc: [BOARDSPECIFIC] ECC control structure
790 * @buffers: buffer structure for read/write
791 * @buf_align: minimum buffer alignment required by a platform
792 * @hwcontrol: platform-specific hardware control structure
793 * @erase: [REPLACEABLE] erase function
794 * @scan_bbt: [REPLACEABLE] function to scan bad block table
795 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
796 * data from array to read regs (tR).
797 * @state: [INTERN] the current state of the NAND device
798 * @oob_poi: "poison value buffer," used for laying out OOB data
799 * before writing
800 * @page_shift: [INTERN] number of address bits in a page (column
801 * address bits).
802 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
803 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
804 * @chip_shift: [INTERN] number of address bits in one chip
805 * @options: [BOARDSPECIFIC] various chip options. They can partly
806 * be set to inform nand_scan about special functionality.
807 * See the defines for further explanation.
808 * @bbt_options: [INTERN] bad block specific options. All options used
809 * here must come from bbm.h. By default, these options
810 * will be copied to the appropriate nand_bbt_descr's.
811 * @badblockpos: [INTERN] position of the bad block marker in the oob
812 * area.
813 * @badblockbits: [INTERN] minimum number of set bits in a good block's
814 * bad block marker position; i.e., BBM == 11110111b is
815 * not bad when badblockbits == 7
816 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
817 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
818 * Minimum amount of bit errors per @ecc_step_ds guaranteed
819 * to be correctable. If unknown, set to zero.
820 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
821 * also from the datasheet. It is the recommended ECC step
822 * size, if known; if unknown, set to zero.
823 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
824 * set to the actually used ONFI mode if the chip is
825 * ONFI compliant or deduced from the datasheet if
826 * the NAND chip is not ONFI compliant.
827 * @numchips: [INTERN] number of physical chips
828 * @chipsize: [INTERN] the size of one chip for multichip arrays
829 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
830 * @pagebuf: [INTERN] holds the pagenumber which is currently in
831 * data_buf.
832 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
833 * currently in data_buf.
834 * @subpagesize: [INTERN] holds the subpagesize
835 * @id: [INTERN] holds NAND ID
836 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
837 * non 0 if ONFI supported.
838 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
839 * non 0 if JEDEC supported.
840 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
841 * supported, 0 otherwise.
842 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
843 * supported, 0 otherwise.
844 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
845 * this nand device will encounter their life times.
846 * @blocks_per_die: [INTERN] The number of PEBs in a die
847 * @data_interface: [INTERN] NAND interface timing information
848 * @read_retries: [INTERN] the number of read retry modes supported
849 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
850 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
851 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
852 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
853 * means the configuration should not be applied but
854 * only checked.
855 * @bbt: [INTERN] bad block table pointer
856 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
857 * lookup.
858 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
859 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
860 * bad block scan.
861 * @controller: [REPLACEABLE] a pointer to a hardware controller
862 * structure which is shared among multiple independent
863 * devices.
864 * @priv: [OPTIONAL] pointer to private chip data
865 * @manufacturer: [INTERN] Contains manufacturer information
866 */
867
868 struct nand_chip {
869 struct mtd_info mtd;
870 void __iomem *IO_ADDR_R;
871 void __iomem *IO_ADDR_W;
872
873 uint8_t (*read_byte)(struct mtd_info *mtd);
874 u16 (*read_word)(struct mtd_info *mtd);
875 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
876 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
877 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
878 void (*select_chip)(struct mtd_info *mtd, int chip);
879 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
880 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
881 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
882 int (*dev_ready)(struct mtd_info *mtd);
883 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
884 int page_addr);
885 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
886 int (*erase)(struct mtd_info *mtd, int page);
887 int (*scan_bbt)(struct mtd_info *mtd);
888 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
889 int feature_addr, uint8_t *subfeature_para);
890 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
891 int feature_addr, uint8_t *subfeature_para);
892 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
893 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
894 const struct nand_data_interface *conf);
895
896
897 int chip_delay;
898 unsigned int options;
899 unsigned int bbt_options;
900
901 int page_shift;
902 int phys_erase_shift;
903 int bbt_erase_shift;
904 int chip_shift;
905 int numchips;
906 uint64_t chipsize;
907 int pagemask;
908 int pagebuf;
909 unsigned int pagebuf_bitflips;
910 int subpagesize;
911 uint8_t bits_per_cell;
912 uint16_t ecc_strength_ds;
913 uint16_t ecc_step_ds;
914 int onfi_timing_mode_default;
915 int badblockpos;
916 int badblockbits;
917
918 struct nand_id id;
919 int onfi_version;
920 int jedec_version;
921 union {
922 struct nand_onfi_params onfi_params;
923 struct nand_jedec_params jedec_params;
924 };
925 u16 max_bb_per_die;
926 u32 blocks_per_die;
927
928 struct nand_data_interface *data_interface;
929
930 int read_retries;
931
932 flstate_t state;
933
934 uint8_t *oob_poi;
935 struct nand_hw_control *controller;
936
937 struct nand_ecc_ctrl ecc;
938 struct nand_buffers *buffers;
939 unsigned long buf_align;
940 struct nand_hw_control hwcontrol;
941
942 uint8_t *bbt;
943 struct nand_bbt_descr *bbt_td;
944 struct nand_bbt_descr *bbt_md;
945
946 struct nand_bbt_descr *badblock_pattern;
947
948 void *priv;
949
950 struct {
951 const struct nand_manufacturer *desc;
952 void *priv;
953 } manufacturer;
954 };
955
956 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
957 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
958
nand_set_flash_node(struct nand_chip * chip,struct device_node * np)959 static inline void nand_set_flash_node(struct nand_chip *chip,
960 struct device_node *np)
961 {
962 mtd_set_of_node(&chip->mtd, np);
963 }
964
nand_get_flash_node(struct nand_chip * chip)965 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
966 {
967 return mtd_get_of_node(&chip->mtd);
968 }
969
mtd_to_nand(struct mtd_info * mtd)970 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
971 {
972 return container_of(mtd, struct nand_chip, mtd);
973 }
974
nand_to_mtd(struct nand_chip * chip)975 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
976 {
977 return &chip->mtd;
978 }
979
nand_get_controller_data(struct nand_chip * chip)980 static inline void *nand_get_controller_data(struct nand_chip *chip)
981 {
982 return chip->priv;
983 }
984
nand_set_controller_data(struct nand_chip * chip,void * priv)985 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
986 {
987 chip->priv = priv;
988 }
989
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)990 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
991 void *priv)
992 {
993 chip->manufacturer.priv = priv;
994 }
995
nand_get_manufacturer_data(struct nand_chip * chip)996 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
997 {
998 return chip->manufacturer.priv;
999 }
1000
1001 /*
1002 * NAND Flash Manufacturer ID Codes
1003 */
1004 #define NAND_MFR_TOSHIBA 0x98
1005 #define NAND_MFR_ESMT 0xc8
1006 #define NAND_MFR_SAMSUNG 0xec
1007 #define NAND_MFR_FUJITSU 0x04
1008 #define NAND_MFR_NATIONAL 0x8f
1009 #define NAND_MFR_RENESAS 0x07
1010 #define NAND_MFR_STMICRO 0x20
1011 #define NAND_MFR_HYNIX 0xad
1012 #define NAND_MFR_MICRON 0x2c
1013 #define NAND_MFR_AMD 0x01
1014 #define NAND_MFR_MACRONIX 0xc2
1015 #define NAND_MFR_EON 0x92
1016 #define NAND_MFR_SANDISK 0x45
1017 #define NAND_MFR_INTEL 0x89
1018 #define NAND_MFR_ATO 0x9b
1019 #define NAND_MFR_WINBOND 0xef
1020
1021
1022 /*
1023 * A helper for defining older NAND chips where the second ID byte fully
1024 * defined the chip, including the geometry (chip size, eraseblock size, page
1025 * size). All these chips have 512 bytes NAND page size.
1026 */
1027 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1028 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1029 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1030
1031 /*
1032 * A helper for defining newer chips which report their page size and
1033 * eraseblock size via the extended ID bytes.
1034 *
1035 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1036 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1037 * device ID now only represented a particular total chip size (and voltage,
1038 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1039 * using the same device ID.
1040 */
1041 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1042 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1043 .options = (opts) }
1044
1045 #define NAND_ECC_INFO(_strength, _step) \
1046 { .strength_ds = (_strength), .step_ds = (_step) }
1047 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1048 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1049
1050 /**
1051 * struct nand_flash_dev - NAND Flash Device ID Structure
1052 * @name: a human-readable name of the NAND chip
1053 * @dev_id: the device ID (the second byte of the full chip ID array)
1054 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1055 * memory address as @id[0])
1056 * @dev_id: device ID part of the full chip ID array (refers the same memory
1057 * address as @id[1])
1058 * @id: full device ID array
1059 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1060 * well as the eraseblock size) is determined from the extended NAND
1061 * chip ID array)
1062 * @chipsize: total chip size in MiB
1063 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1064 * @options: stores various chip bit options
1065 * @id_len: The valid length of the @id.
1066 * @oobsize: OOB size
1067 * @ecc: ECC correctability and step information from the datasheet.
1068 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1069 * @ecc_strength_ds in nand_chip{}.
1070 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1071 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1072 * For example, the "4bit ECC for each 512Byte" can be set with
1073 * NAND_ECC_INFO(4, 512).
1074 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1075 * reset. Should be deduced from timings described
1076 * in the datasheet.
1077 *
1078 */
1079 struct nand_flash_dev {
1080 char *name;
1081 union {
1082 struct {
1083 uint8_t mfr_id;
1084 uint8_t dev_id;
1085 };
1086 uint8_t id[NAND_MAX_ID_LEN];
1087 };
1088 unsigned int pagesize;
1089 unsigned int chipsize;
1090 unsigned int erasesize;
1091 unsigned int options;
1092 uint16_t id_len;
1093 uint16_t oobsize;
1094 struct {
1095 uint16_t strength_ds;
1096 uint16_t step_ds;
1097 } ecc;
1098 int onfi_timing_mode_default;
1099 };
1100
1101 /**
1102 * struct nand_manufacturer - NAND Flash Manufacturer structure
1103 * @name: Manufacturer name
1104 * @id: manufacturer ID code of device.
1105 * @ops: manufacturer operations
1106 */
1107 struct nand_manufacturer {
1108 int id;
1109 char *name;
1110 const struct nand_manufacturer_ops *ops;
1111 };
1112
1113 const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1114
1115 static inline const char *
nand_manufacturer_name(const struct nand_manufacturer * manufacturer)1116 nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1117 {
1118 return manufacturer ? manufacturer->name : "Unknown";
1119 }
1120
1121 extern struct nand_flash_dev nand_flash_ids[];
1122
1123 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1124 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1125 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1126 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1127 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1128 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1129
1130 int nand_default_bbt(struct mtd_info *mtd);
1131 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1132 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1133 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1134 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1135 int allowbbt);
1136 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1137 size_t *retlen, uint8_t *buf);
1138
1139 /**
1140 * struct platform_nand_chip - chip level device structure
1141 * @nr_chips: max. number of chips to scan for
1142 * @chip_offset: chip number offset
1143 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1144 * @partitions: mtd partition list
1145 * @chip_delay: R/B delay value in us
1146 * @options: Option flags, e.g. 16bit buswidth
1147 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1148 * @part_probe_types: NULL-terminated array of probe types
1149 */
1150 struct platform_nand_chip {
1151 int nr_chips;
1152 int chip_offset;
1153 int nr_partitions;
1154 struct mtd_partition *partitions;
1155 int chip_delay;
1156 unsigned int options;
1157 unsigned int bbt_options;
1158 const char **part_probe_types;
1159 };
1160
1161 /* Keep gcc happy */
1162 struct platform_device;
1163
1164 /**
1165 * struct platform_nand_ctrl - controller level device structure
1166 * @probe: platform specific function to probe/setup hardware
1167 * @remove: platform specific function to remove/teardown hardware
1168 * @hwcontrol: platform specific hardware control structure
1169 * @dev_ready: platform specific function to read ready/busy pin
1170 * @select_chip: platform specific chip select function
1171 * @cmd_ctrl: platform specific function for controlling
1172 * ALE/CLE/nCE. Also used to write command and address
1173 * @write_buf: platform specific function for write buffer
1174 * @read_buf: platform specific function for read buffer
1175 * @read_byte: platform specific function to read one byte from chip
1176 * @priv: private data to transport driver specific settings
1177 *
1178 * All fields are optional and depend on the hardware driver requirements
1179 */
1180 struct platform_nand_ctrl {
1181 int (*probe)(struct platform_device *pdev);
1182 void (*remove)(struct platform_device *pdev);
1183 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1184 int (*dev_ready)(struct mtd_info *mtd);
1185 void (*select_chip)(struct mtd_info *mtd, int chip);
1186 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1187 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1188 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1189 unsigned char (*read_byte)(struct mtd_info *mtd);
1190 void *priv;
1191 };
1192
1193 /**
1194 * struct platform_nand_data - container structure for platform-specific data
1195 * @chip: chip level chip structure
1196 * @ctrl: controller level device structure
1197 */
1198 struct platform_nand_data {
1199 struct platform_nand_chip chip;
1200 struct platform_nand_ctrl ctrl;
1201 };
1202
1203 /* return the supported features. */
onfi_feature(struct nand_chip * chip)1204 static inline int onfi_feature(struct nand_chip *chip)
1205 {
1206 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1207 }
1208
1209 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1210 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1211 {
1212 if (!chip->onfi_version)
1213 return ONFI_TIMING_MODE_UNKNOWN;
1214 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1215 }
1216
1217 /* return the supported synchronous timing mode. */
onfi_get_sync_timing_mode(struct nand_chip * chip)1218 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1219 {
1220 if (!chip->onfi_version)
1221 return ONFI_TIMING_MODE_UNKNOWN;
1222 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1223 }
1224
1225 int onfi_init_data_interface(struct nand_chip *chip,
1226 struct nand_data_interface *iface,
1227 enum nand_data_interface_type type,
1228 int timing_mode);
1229
1230 /*
1231 * Check if it is a SLC nand.
1232 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1233 * We do not distinguish the MLC and TLC now.
1234 */
nand_is_slc(struct nand_chip * chip)1235 static inline bool nand_is_slc(struct nand_chip *chip)
1236 {
1237 WARN(chip->bits_per_cell == 0,
1238 "chip->bits_per_cell is used uninitialized\n");
1239 return chip->bits_per_cell == 1;
1240 }
1241
1242 /**
1243 * Check if the opcode's address should be sent only on the lower 8 bits
1244 * @command: opcode to check
1245 */
nand_opcode_8bits(unsigned int command)1246 static inline int nand_opcode_8bits(unsigned int command)
1247 {
1248 switch (command) {
1249 case NAND_CMD_READID:
1250 case NAND_CMD_PARAM:
1251 case NAND_CMD_GET_FEATURES:
1252 case NAND_CMD_SET_FEATURES:
1253 return 1;
1254 default:
1255 break;
1256 }
1257 return 0;
1258 }
1259
1260 /* return the supported JEDEC features. */
jedec_feature(struct nand_chip * chip)1261 static inline int jedec_feature(struct nand_chip *chip)
1262 {
1263 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1264 : 0;
1265 }
1266
1267 /* get timing characteristics from ONFI timing mode. */
1268 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1269 /* get data interface from ONFI timing mode 0, used after reset. */
1270 const struct nand_data_interface *nand_get_default_data_interface(void);
1271
1272 int nand_check_erased_ecc_chunk(void *data, int datalen,
1273 void *ecc, int ecclen,
1274 void *extraoob, int extraooblen,
1275 int threshold);
1276
1277 int nand_check_ecc_caps(struct nand_chip *chip,
1278 const struct nand_ecc_caps *caps, int oobavail);
1279
1280 int nand_match_ecc_req(struct nand_chip *chip,
1281 const struct nand_ecc_caps *caps, int oobavail);
1282
1283 int nand_maximize_ecc(struct nand_chip *chip,
1284 const struct nand_ecc_caps *caps, int oobavail);
1285
1286 /* Default write_oob implementation */
1287 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1288
1289 /* Default write_oob syndrome implementation */
1290 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1291 int page);
1292
1293 /* Default read_oob implementation */
1294 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1295
1296 /* Default read_oob syndrome implementation */
1297 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1298 int page);
1299
1300 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1301 int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd,
1302 struct nand_chip *chip, int addr,
1303 u8 *subfeature_param);
1304
1305 /* Default read_page_raw implementation */
1306 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1307 uint8_t *buf, int oob_required, int page);
1308
1309 /* Default write_page_raw implementation */
1310 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1311 const uint8_t *buf, int oob_required, int page);
1312
1313 /* Reset and initialize a NAND device */
1314 int nand_reset(struct nand_chip *chip, int chipnr);
1315
1316 /* Free resources held by the NAND device */
1317 void nand_cleanup(struct nand_chip *chip);
1318
1319 /* Default extended ID decoding function */
1320 void nand_decode_ext_id(struct nand_chip *chip);
1321 #endif /* __LINUX_MTD_RAWNAND_H */
1322