1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __NVKM_FALCON_H__
3 #define __NVKM_FALCON_H__
4 #define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine)
5 #include <core/engine.h>
6 struct nvkm_fifo_chan;
7
8 enum nvkm_falcon_dmaidx {
9 FALCON_DMAIDX_UCODE = 0,
10 FALCON_DMAIDX_VIRT = 1,
11 FALCON_DMAIDX_PHYS_VID = 2,
12 FALCON_DMAIDX_PHYS_SYS_COH = 3,
13 FALCON_DMAIDX_PHYS_SYS_NCOH = 4,
14 FALCON_SEC2_DMAIDX_UCODE = 6,
15 };
16
17 struct nvkm_falcon {
18 const struct nvkm_falcon_func *func;
19 const struct nvkm_subdev *owner;
20 const char *name;
21 u32 addr;
22
23 struct mutex mutex;
24 struct mutex dmem_mutex;
25 const struct nvkm_subdev *user;
26
27 u8 version;
28 u8 secret;
29 bool debug;
30 bool has_emem;
31
32 struct nvkm_memory *core;
33 bool external;
34
35 struct {
36 u32 limit;
37 u32 *data;
38 u32 size;
39 u8 ports;
40 } code;
41
42 struct {
43 u32 limit;
44 u32 *data;
45 u32 size;
46 u8 ports;
47 } data;
48
49 struct nvkm_engine engine;
50 };
51
52 /* This constructor must be called from the owner's oneinit() hook and
53 * *not* its constructor. This is to ensure that DEVINIT has been
54 * completed, and that the device is correctly enabled before we touch
55 * falcon registers.
56 */
57 int nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr,
58 struct nvkm_falcon **);
59
60 void nvkm_falcon_del(struct nvkm_falcon **);
61 int nvkm_falcon_get(struct nvkm_falcon *, const struct nvkm_subdev *);
62 void nvkm_falcon_put(struct nvkm_falcon *, const struct nvkm_subdev *);
63
64 int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
65 int index, bool enable, u32 addr, struct nvkm_engine **);
66
67 struct nvkm_falcon_func {
68 struct {
69 u32 *data;
70 u32 size;
71 } code;
72 struct {
73 u32 *data;
74 u32 size;
75 } data;
76 void (*init)(struct nvkm_falcon *);
77 void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *);
78 void (*load_imem)(struct nvkm_falcon *, void *, u32, u32, u16, u8, bool);
79 void (*load_dmem)(struct nvkm_falcon *, void *, u32, u32, u8);
80 void (*read_dmem)(struct nvkm_falcon *, u32, u32, u8, void *);
81 void (*bind_context)(struct nvkm_falcon *, struct nvkm_gpuobj *);
82 int (*wait_for_halt)(struct nvkm_falcon *, u32);
83 int (*clear_interrupt)(struct nvkm_falcon *, u32);
84 void (*set_start_addr)(struct nvkm_falcon *, u32 start_addr);
85 void (*start)(struct nvkm_falcon *);
86 int (*enable)(struct nvkm_falcon *falcon);
87 void (*disable)(struct nvkm_falcon *falcon);
88
89 struct nvkm_sclass sclass[];
90 };
91
92 static inline u32
nvkm_falcon_rd32(struct nvkm_falcon * falcon,u32 addr)93 nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr)
94 {
95 return nvkm_rd32(falcon->owner->device, falcon->addr + addr);
96 }
97
98 static inline void
nvkm_falcon_wr32(struct nvkm_falcon * falcon,u32 addr,u32 data)99 nvkm_falcon_wr32(struct nvkm_falcon *falcon, u32 addr, u32 data)
100 {
101 nvkm_wr32(falcon->owner->device, falcon->addr + addr, data);
102 }
103
104 static inline u32
nvkm_falcon_mask(struct nvkm_falcon * falcon,u32 addr,u32 mask,u32 val)105 nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val)
106 {
107 struct nvkm_device *device = falcon->owner->device;
108
109 return nvkm_mask(device, falcon->addr + addr, mask, val);
110 }
111
112 void nvkm_falcon_load_imem(struct nvkm_falcon *, void *, u32, u32, u16, u8,
113 bool);
114 void nvkm_falcon_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8);
115 void nvkm_falcon_read_dmem(struct nvkm_falcon *, u32, u32, u8, void *);
116 void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_gpuobj *);
117 void nvkm_falcon_set_start_addr(struct nvkm_falcon *, u32);
118 void nvkm_falcon_start(struct nvkm_falcon *);
119 int nvkm_falcon_wait_for_halt(struct nvkm_falcon *, u32);
120 int nvkm_falcon_clear_interrupt(struct nvkm_falcon *, u32);
121 int nvkm_falcon_enable(struct nvkm_falcon *);
122 void nvkm_falcon_disable(struct nvkm_falcon *);
123 int nvkm_falcon_reset(struct nvkm_falcon *);
124
125 #endif
126