1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/alpha/kernel/pci.c
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 */
9
10 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
11
12 /*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup
15 */
16 #include <linux/string.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <linux/module.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <asm/machvec.h>
26
27 #include "proto.h"
28 #include "pci_impl.h"
29
30
31 /*
32 * Some string constants used by the various core logics.
33 */
34
35 const char *const pci_io_names[] = {
36 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
37 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
38 };
39
40 const char *const pci_mem_names[] = {
41 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
42 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
43 };
44
45 const char pci_hae0_name[] = "HAE0";
46
47 /*
48 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
49 * assignments.
50 */
51
52 /*
53 * The PCI controller list.
54 */
55
56 struct pci_controller *hose_head, **hose_tail = &hose_head;
57 struct pci_controller *pci_isa_hose;
58
59 /*
60 * Quirks.
61 */
62
quirk_isa_bridge(struct pci_dev * dev)63 static void quirk_isa_bridge(struct pci_dev *dev)
64 {
65 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
66 }
67 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
68
quirk_cypress(struct pci_dev * dev)69 static void quirk_cypress(struct pci_dev *dev)
70 {
71 /* The Notorious Cy82C693 chip. */
72
73 /* The generic legacy mode IDE fixup in drivers/pci/probe.c
74 doesn't work correctly with the Cypress IDE controller as
75 it has non-standard register layout. Fix that. */
76 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
77 dev->resource[2].start = dev->resource[3].start = 0;
78 dev->resource[2].end = dev->resource[3].end = 0;
79 dev->resource[2].flags = dev->resource[3].flags = 0;
80 if (PCI_FUNC(dev->devfn) == 2) {
81 dev->resource[0].start = 0x170;
82 dev->resource[0].end = 0x177;
83 dev->resource[1].start = 0x376;
84 dev->resource[1].end = 0x376;
85 }
86 }
87
88 /* The Cypress bridge responds on the PCI bus in the address range
89 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
90 way to turn this off. The bridge also supports several extended
91 BIOS ranges (disabled after power-up), and some consoles do turn
92 them on. So if we use a large direct-map window, or a large SG
93 window, we must avoid the entire 0xfff00000-0xffffffff region. */
94 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
95 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
96 __direct_map_size = 0xfff00000UL - __direct_map_base;
97 else {
98 struct pci_controller *hose = dev->sysdata;
99 struct pci_iommu_arena *pci = hose->sg_pci;
100 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
101 pci->size = 0xfff00000UL - pci->dma_base;
102 }
103 }
104 }
105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
106
107 /* Called for each device after PCI setup is done. */
pcibios_fixup_final(struct pci_dev * dev)108 static void pcibios_fixup_final(struct pci_dev *dev)
109 {
110 unsigned int class = dev->class >> 8;
111
112 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
113 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
114 isa_bridge = dev;
115 }
116 }
117 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
118
119 /* Just declaring that the power-of-ten prefixes are actually the
120 power-of-two ones doesn't make it true :) */
121 #define KB 1024
122 #define MB (1024*KB)
123 #define GB (1024*MB)
124
125 resource_size_t
pcibios_align_resource(void * data,const struct resource * res,resource_size_t size,resource_size_t align)126 pcibios_align_resource(void *data, const struct resource *res,
127 resource_size_t size, resource_size_t align)
128 {
129 struct pci_dev *dev = data;
130 struct pci_controller *hose = dev->sysdata;
131 unsigned long alignto;
132 resource_size_t start = res->start;
133
134 if (res->flags & IORESOURCE_IO) {
135 /* Make sure we start at our min on all hoses */
136 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
137 start = PCIBIOS_MIN_IO + hose->io_space->start;
138
139 /*
140 * Put everything into 0x00-0xff region modulo 0x400
141 */
142 if (start & 0x300)
143 start = (start + 0x3ff) & ~0x3ff;
144 }
145 else if (res->flags & IORESOURCE_MEM) {
146 /* Make sure we start at our min on all hoses */
147 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
148 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
149
150 /*
151 * The following holds at least for the Low Cost
152 * Alpha implementation of the PCI interface:
153 *
154 * In sparse memory address space, the first
155 * octant (16MB) of every 128MB segment is
156 * aliased to the very first 16 MB of the
157 * address space (i.e., it aliases the ISA
158 * memory address space). Thus, we try to
159 * avoid allocating PCI devices in that range.
160 * Can be allocated in 2nd-7th octant only.
161 * Devices that need more than 112MB of
162 * address space must be accessed through
163 * dense memory space only!
164 */
165
166 /* Align to multiple of size of minimum base. */
167 alignto = max_t(resource_size_t, 0x1000, align);
168 start = ALIGN(start, alignto);
169 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
170 if (((start / (16*MB)) & 0x7) == 0) {
171 start &= ~(128*MB - 1);
172 start += 16*MB;
173 start = ALIGN(start, alignto);
174 }
175 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
176 start &= ~(128*MB - 1);
177 start += (128 + 16)*MB;
178 start = ALIGN(start, alignto);
179 }
180 }
181 }
182
183 return start;
184 }
185 #undef KB
186 #undef MB
187 #undef GB
188
189 static int __init
pcibios_init(void)190 pcibios_init(void)
191 {
192 if (alpha_mv.init_pci)
193 alpha_mv.init_pci();
194 return 0;
195 }
196
197 subsys_initcall(pcibios_init);
198
199 #ifdef ALPHA_RESTORE_SRM_SETUP
200 static struct pdev_srm_saved_conf *srm_saved_configs;
201
pdev_save_srm_config(struct pci_dev * dev)202 void pdev_save_srm_config(struct pci_dev *dev)
203 {
204 struct pdev_srm_saved_conf *tmp;
205 static int printed = 0;
206
207 if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
208 return;
209
210 if (!printed) {
211 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
212 printed = 1;
213 }
214
215 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
216 if (!tmp) {
217 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
218 return;
219 }
220 tmp->next = srm_saved_configs;
221 tmp->dev = dev;
222
223 pci_save_state(dev);
224
225 srm_saved_configs = tmp;
226 }
227
228 void
pci_restore_srm_config(void)229 pci_restore_srm_config(void)
230 {
231 struct pdev_srm_saved_conf *tmp;
232
233 /* No need to restore if probed only. */
234 if (pci_has_flag(PCI_PROBE_ONLY))
235 return;
236
237 /* Restore SRM config. */
238 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
239 pci_restore_state(tmp->dev);
240 }
241 }
242 #endif
243
pcibios_fixup_bus(struct pci_bus * bus)244 void pcibios_fixup_bus(struct pci_bus *bus)
245 {
246 struct pci_dev *dev = bus->self;
247
248 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
249 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
250 pci_read_bridge_bases(bus);
251 }
252
253 list_for_each_entry(dev, &bus->devices, bus_list) {
254 pdev_save_srm_config(dev);
255 }
256 }
257
258 /*
259 * If we set up a device for bus mastering, we need to check the latency
260 * timer as certain firmware forgets to set it properly, as seen
261 * on SX164 and LX164 with SRM.
262 */
263 void
pcibios_set_master(struct pci_dev * dev)264 pcibios_set_master(struct pci_dev *dev)
265 {
266 u8 lat;
267 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
268 if (lat >= 16) return;
269 printk("PCI: Setting latency timer of device %s to 64\n",
270 pci_name(dev));
271 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
272 }
273
274 void __init
pcibios_claim_one_bus(struct pci_bus * b)275 pcibios_claim_one_bus(struct pci_bus *b)
276 {
277 struct pci_dev *dev;
278 struct pci_bus *child_bus;
279
280 list_for_each_entry(dev, &b->devices, bus_list) {
281 int i;
282
283 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
284 struct resource *r = &dev->resource[i];
285
286 if (r->parent || !r->start || !r->flags)
287 continue;
288 if (pci_has_flag(PCI_PROBE_ONLY) ||
289 (r->flags & IORESOURCE_PCI_FIXED)) {
290 if (pci_claim_resource(dev, i) == 0)
291 continue;
292
293 pci_claim_bridge_resource(dev, i);
294 }
295 }
296 }
297
298 list_for_each_entry(child_bus, &b->children, node)
299 pcibios_claim_one_bus(child_bus);
300 }
301
302 static void __init
pcibios_claim_console_setup(void)303 pcibios_claim_console_setup(void)
304 {
305 struct pci_bus *b;
306
307 list_for_each_entry(b, &pci_root_buses, node)
308 pcibios_claim_one_bus(b);
309 }
310
311 void __init
common_init_pci(void)312 common_init_pci(void)
313 {
314 struct pci_controller *hose;
315 struct list_head resources;
316 struct pci_host_bridge *bridge;
317 struct pci_bus *bus;
318 int ret, next_busno;
319 int need_domain_info = 0;
320 u32 pci_mem_end;
321 u32 sg_base;
322 unsigned long end;
323
324 /* Scan all of the recorded PCI controllers. */
325 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
326 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
327
328 /* Adjust hose mem_space limit to prevent PCI allocations
329 in the iommu windows. */
330 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
331 end = hose->mem_space->start + pci_mem_end;
332 if (hose->mem_space->end > end)
333 hose->mem_space->end = end;
334
335 INIT_LIST_HEAD(&resources);
336 pci_add_resource_offset(&resources, hose->io_space,
337 hose->io_space->start);
338 pci_add_resource_offset(&resources, hose->mem_space,
339 hose->mem_space->start);
340
341 bridge = pci_alloc_host_bridge(0);
342 if (!bridge)
343 continue;
344
345 list_splice_init(&resources, &bridge->windows);
346 bridge->dev.parent = NULL;
347 bridge->sysdata = hose;
348 bridge->busnr = next_busno;
349 bridge->ops = alpha_mv.pci_ops;
350 bridge->swizzle_irq = alpha_mv.pci_swizzle;
351 bridge->map_irq = alpha_mv.pci_map_irq;
352
353 ret = pci_scan_root_bus_bridge(bridge);
354 if (ret) {
355 pci_free_host_bridge(bridge);
356 continue;
357 }
358
359 bus = hose->bus = bridge->bus;
360 hose->need_domain_info = need_domain_info;
361 next_busno = bus->busn_res.end + 1;
362 /* Don't allow 8-bit bus number overflow inside the hose -
363 reserve some space for bridges. */
364 if (next_busno > 224) {
365 next_busno = 0;
366 need_domain_info = 1;
367 }
368 }
369
370 pcibios_claim_console_setup();
371
372 pci_assign_unassigned_resources();
373 for (hose = hose_head; hose; hose = hose->next) {
374 bus = hose->bus;
375 if (bus)
376 pci_bus_add_devices(bus);
377 }
378 }
379
380 struct pci_controller * __init
alloc_pci_controller(void)381 alloc_pci_controller(void)
382 {
383 struct pci_controller *hose;
384
385 hose = alloc_bootmem(sizeof(*hose));
386
387 *hose_tail = hose;
388 hose_tail = &hose->next;
389
390 return hose;
391 }
392
393 struct resource * __init
alloc_resource(void)394 alloc_resource(void)
395 {
396 return alloc_bootmem(sizeof(struct resource));
397 }
398
399
400 /* Provide information on locations of various I/O regions in physical
401 memory. Do this on a per-card basis so that we choose the right hose. */
402
403 asmlinkage long
sys_pciconfig_iobase(long which,unsigned long bus,unsigned long dfn)404 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
405 {
406 struct pci_controller *hose;
407 struct pci_dev *dev;
408
409 /* from hose or from bus.devfn */
410 if (which & IOBASE_FROM_HOSE) {
411 for(hose = hose_head; hose; hose = hose->next)
412 if (hose->index == bus) break;
413 if (!hose) return -ENODEV;
414 } else {
415 /* Special hook for ISA access. */
416 if (bus == 0 && dfn == 0) {
417 hose = pci_isa_hose;
418 } else {
419 dev = pci_get_bus_and_slot(bus, dfn);
420 if (!dev)
421 return -ENODEV;
422 hose = dev->sysdata;
423 pci_dev_put(dev);
424 }
425 }
426
427 switch (which & ~IOBASE_FROM_HOSE) {
428 case IOBASE_HOSE:
429 return hose->index;
430 case IOBASE_SPARSE_MEM:
431 return hose->sparse_mem_base;
432 case IOBASE_DENSE_MEM:
433 return hose->dense_mem_base;
434 case IOBASE_SPARSE_IO:
435 return hose->sparse_io_base;
436 case IOBASE_DENSE_IO:
437 return hose->dense_io_base;
438 case IOBASE_ROOT_BUS:
439 return hose->bus->number;
440 }
441
442 return -EOPNOTSUPP;
443 }
444
445 /* Destroy an __iomem token. Not copied from lib/iomap.c. */
446
pci_iounmap(struct pci_dev * dev,void __iomem * addr)447 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
448 {
449 if (__is_mmio(addr))
450 iounmap(addr);
451 }
452
453 EXPORT_SYMBOL(pci_iounmap);
454
455 /* FIXME: Some boxes have multiple ISA bridges! */
456 struct pci_dev *isa_bridge;
457 EXPORT_SYMBOL(isa_bridge);
458