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Searched defs:pll (Results 1 – 15 of 15) sorted by relevance

/arch/c6x/platforms/
Dplldata.c172 struct pll_data *pll = &c6x_soc_pll1; in c6455_setup_clocks() local
210 struct pll_data *pll = &c6x_soc_pll1; in c6457_setup_clocks() local
260 struct pll_data *pll = &c6x_soc_pll1; in c6472_setup_clocks() local
309 struct pll_data *pll = &c6x_soc_pll1; in c6474_setup_clocks() local
358 struct pll_data *pll = &c6x_soc_pll1; in c6678_setup_clocks() local
423 struct pll_data *pll = &c6x_soc_pll1; in c64x_setup_clocks() local
Dpll.c204 static u32 pll_read(struct pll_data *pll, int reg) in pll_read()
212 struct pll_data *pll; in clk_sysclk_recalc() local
273 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc() local
/arch/arm/mach-davinci/
Dclock.c318 struct pll_data *pll; in clk_sysclk_recalc() local
356 struct pll_data *pll; in davinci_set_sysclk_rate() local
444 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc() local
511 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, in davinci_set_pllrate()
635 struct pll_data *pll = clk->pll_data; in davinci_clk_init() local
Dda850.c1205 struct pll_data *pll = clk->pll_data; in da850_set_pll0rate() local
/arch/mips/boot/dts/qca/
Dar9331.dtsi90 pll: pll-controller@18050000 { label
Dar9132.dtsi89 pll: pll-controller@18050000 { label
/arch/mips/ath79/
Dclock.c63 u32 pll; in ar71xx_clocks_init() local
106 u32 pll; in ar724x_clk_init() local
248 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
364 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca955x_clocks_init() local
/arch/m68k/q40/
Dconfig.c302 static int q40_get_rtc_pll(struct rtc_pll_info *pll) in q40_get_rtc_pll()
318 static int q40_set_rtc_pll(struct rtc_pll_info *pll) in q40_set_rtc_pll()
/arch/m68k/kernel/
Dtime.c106 struct rtc_pll_info pll; in rtc_ioctl() local
/arch/cris/include/arch-v32/arch/hwregs/
Dconfig_defs.h93 unsigned int pll : 1; member
101 unsigned int pll : 1; member
/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dconfig_defs.h93 unsigned int pll : 1; member
101 unsigned int pll : 1; member
/arch/mips/ar7/
Dclock.c62 u32 pll; member
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock() local
/arch/arm/plat-samsung/include/plat/
Dcpu-freq-core.h123 struct cpufreq_frequency_table pll; member
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dclkgen_defs.h96 unsigned int pll : 1; member
/arch/alpha/include/asm/
Dcore_marvel.h269 #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) argument
270 #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7) argument