1 /*
2 *
3 * Common boot and setup code.
4 *
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #define DEBUG
14
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/memory.h>
39 #include <linux/nmi.h>
40
41 #include <asm/debugfs.h>
42 #include <asm/io.h>
43 #include <asm/kdump.h>
44 #include <asm/prom.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
47 #include <asm/smp.h>
48 #include <asm/elf.h>
49 #include <asm/machdep.h>
50 #include <asm/paca.h>
51 #include <asm/time.h>
52 #include <asm/cputable.h>
53 #include <asm/dt_cpu_ftrs.h>
54 #include <asm/sections.h>
55 #include <asm/btext.h>
56 #include <asm/nvram.h>
57 #include <asm/setup.h>
58 #include <asm/rtas.h>
59 #include <asm/iommu.h>
60 #include <asm/serial.h>
61 #include <asm/cache.h>
62 #include <asm/page.h>
63 #include <asm/mmu.h>
64 #include <asm/firmware.h>
65 #include <asm/xmon.h>
66 #include <asm/udbg.h>
67 #include <asm/kexec.h>
68 #include <asm/code-patching.h>
69 #include <asm/livepatch.h>
70 #include <asm/opal.h>
71 #include <asm/cputhreads.h>
72
73 #ifdef DEBUG
74 #define DBG(fmt...) udbg_printf(fmt)
75 #else
76 #define DBG(fmt...)
77 #endif
78
79 int spinning_secondaries;
80 u64 ppc64_pft_size;
81
82 struct ppc64_caches ppc64_caches = {
83 .l1d = {
84 .block_size = 0x40,
85 .log_block_size = 6,
86 },
87 .l1i = {
88 .block_size = 0x40,
89 .log_block_size = 6
90 },
91 };
92 EXPORT_SYMBOL_GPL(ppc64_caches);
93
94 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
setup_tlb_core_data(void)95 void __init setup_tlb_core_data(void)
96 {
97 int cpu;
98
99 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
100
101 for_each_possible_cpu(cpu) {
102 int first = cpu_first_thread_sibling(cpu);
103
104 /*
105 * If we boot via kdump on a non-primary thread,
106 * make sure we point at the thread that actually
107 * set up this TLB.
108 */
109 if (cpu_first_thread_sibling(boot_cpuid) == first)
110 first = boot_cpuid;
111
112 paca[cpu].tcd_ptr = &paca[first].tcd;
113
114 /*
115 * If we have threads, we need either tlbsrx.
116 * or e6500 tablewalk mode, or else TLB handlers
117 * will be racy and could produce duplicate entries.
118 * Should we panic instead?
119 */
120 WARN_ONCE(smt_enabled_at_boot >= 2 &&
121 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
122 book3e_htw_mode != PPC_HTW_E6500,
123 "%s: unsupported MMU configuration\n", __func__);
124 }
125 }
126 #endif
127
128 #ifdef CONFIG_SMP
129
130 static char *smt_enabled_cmdline;
131
132 /* Look for ibm,smt-enabled OF option */
check_smt_enabled(void)133 void __init check_smt_enabled(void)
134 {
135 struct device_node *dn;
136 const char *smt_option;
137
138 /* Default to enabling all threads */
139 smt_enabled_at_boot = threads_per_core;
140
141 /* Allow the command line to overrule the OF option */
142 if (smt_enabled_cmdline) {
143 if (!strcmp(smt_enabled_cmdline, "on"))
144 smt_enabled_at_boot = threads_per_core;
145 else if (!strcmp(smt_enabled_cmdline, "off"))
146 smt_enabled_at_boot = 0;
147 else {
148 int smt;
149 int rc;
150
151 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
152 if (!rc)
153 smt_enabled_at_boot =
154 min(threads_per_core, smt);
155 }
156 } else {
157 dn = of_find_node_by_path("/options");
158 if (dn) {
159 smt_option = of_get_property(dn, "ibm,smt-enabled",
160 NULL);
161
162 if (smt_option) {
163 if (!strcmp(smt_option, "on"))
164 smt_enabled_at_boot = threads_per_core;
165 else if (!strcmp(smt_option, "off"))
166 smt_enabled_at_boot = 0;
167 }
168
169 of_node_put(dn);
170 }
171 }
172 }
173
174 /* Look for smt-enabled= cmdline option */
early_smt_enabled(char * p)175 static int __init early_smt_enabled(char *p)
176 {
177 smt_enabled_cmdline = p;
178 return 0;
179 }
180 early_param("smt-enabled", early_smt_enabled);
181
182 #endif /* CONFIG_SMP */
183
184 /** Fix up paca fields required for the boot cpu */
fixup_boot_paca(void)185 static void __init fixup_boot_paca(void)
186 {
187 /* The boot cpu is started */
188 get_paca()->cpu_start = 1;
189 /* Allow percpu accesses to work until we setup percpu data */
190 get_paca()->data_offset = 0;
191 }
192
configure_exceptions(void)193 static void __init configure_exceptions(void)
194 {
195 /*
196 * Setup the trampolines from the lowmem exception vectors
197 * to the kdump kernel when not using a relocatable kernel.
198 */
199 setup_kdump_trampoline();
200
201 /* Under a PAPR hypervisor, we need hypercalls */
202 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
203 /* Enable AIL if possible */
204 pseries_enable_reloc_on_exc();
205
206 /*
207 * Tell the hypervisor that we want our exceptions to
208 * be taken in little endian mode.
209 *
210 * We don't call this for big endian as our calling convention
211 * makes us always enter in BE, and the call may fail under
212 * some circumstances with kdump.
213 */
214 #ifdef __LITTLE_ENDIAN__
215 pseries_little_endian_exceptions();
216 #endif
217 } else {
218 /* Set endian mode using OPAL */
219 if (firmware_has_feature(FW_FEATURE_OPAL))
220 opal_configure_cores();
221
222 /* AIL on native is done in cpu_ready_for_interrupts() */
223 }
224 }
225
cpu_ready_for_interrupts(void)226 static void cpu_ready_for_interrupts(void)
227 {
228 /*
229 * Enable AIL if supported, and we are in hypervisor mode. This
230 * is called once for every processor.
231 *
232 * If we are not in hypervisor mode the job is done once for
233 * the whole partition in configure_exceptions().
234 */
235 if (cpu_has_feature(CPU_FTR_HVMODE) &&
236 cpu_has_feature(CPU_FTR_ARCH_207S)) {
237 unsigned long lpcr = mfspr(SPRN_LPCR);
238 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
239 }
240
241 /*
242 * Fixup HFSCR:TM based on CPU features. The bit is set by our
243 * early asm init because at that point we haven't updated our
244 * CPU features from firmware and device-tree. Here we have,
245 * so let's do it.
246 */
247 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
248 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
249
250 /* Set IR and DR in PACA MSR */
251 get_paca()->kernel_msr = MSR_KERNEL;
252 }
253
254 /*
255 * Early initialization entry point. This is called by head.S
256 * with MMU translation disabled. We rely on the "feature" of
257 * the CPU that ignores the top 2 bits of the address in real
258 * mode so we can access kernel globals normally provided we
259 * only toy with things in the RMO region. From here, we do
260 * some early parsing of the device-tree to setup out MEMBLOCK
261 * data structures, and allocate & initialize the hash table
262 * and segment tables so we can start running with translation
263 * enabled.
264 *
265 * It is this function which will call the probe() callback of
266 * the various platform types and copy the matching one to the
267 * global ppc_md structure. Your platform can eventually do
268 * some very early initializations from the probe() routine, but
269 * this is not recommended, be very careful as, for example, the
270 * device-tree is not accessible via normal means at this point.
271 */
272
early_setup(unsigned long dt_ptr)273 void __init early_setup(unsigned long dt_ptr)
274 {
275 static __initdata struct paca_struct boot_paca;
276
277 /* -------- printk is _NOT_ safe to use here ! ------- */
278
279 /* Try new device tree based feature discovery ... */
280 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
281 /* Otherwise use the old style CPU table */
282 identify_cpu(0, mfspr(SPRN_PVR));
283
284 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
285 initialise_paca(&boot_paca, 0);
286 setup_paca(&boot_paca);
287 fixup_boot_paca();
288
289 /* -------- printk is now safe to use ------- */
290
291 /* Enable early debugging if any specified (see udbg.h) */
292 udbg_early_init();
293
294 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
295
296 /*
297 * Do early initialization using the flattened device
298 * tree, such as retrieving the physical memory map or
299 * calculating/retrieving the hash table size.
300 */
301 early_init_devtree(__va(dt_ptr));
302
303 /* Now we know the logical id of our boot cpu, setup the paca. */
304 setup_paca(&paca[boot_cpuid]);
305 fixup_boot_paca();
306
307 /*
308 * Configure exception handlers. This include setting up trampolines
309 * if needed, setting exception endian mode, etc...
310 */
311 configure_exceptions();
312
313 /* Apply all the dynamic patching */
314 apply_feature_fixups();
315 setup_feature_keys();
316
317 /* Initialize the hash table or TLB handling */
318 early_init_mmu();
319
320 /*
321 * At this point, we can let interrupts switch to virtual mode
322 * (the MMU has been setup), so adjust the MSR in the PACA to
323 * have IR and DR set and enable AIL if it exists
324 */
325 cpu_ready_for_interrupts();
326
327 DBG(" <- early_setup()\n");
328
329 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
330 /*
331 * This needs to be done *last* (after the above DBG() even)
332 *
333 * Right after we return from this function, we turn on the MMU
334 * which means the real-mode access trick that btext does will
335 * no longer work, it needs to switch to using a real MMU
336 * mapping. This call will ensure that it does
337 */
338 btext_map();
339 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
340 }
341
342 #ifdef CONFIG_SMP
early_setup_secondary(void)343 void early_setup_secondary(void)
344 {
345 /* Mark interrupts disabled in PACA */
346 get_paca()->soft_enabled = 0;
347
348 /* Initialize the hash table or TLB handling */
349 early_init_mmu_secondary();
350
351 /*
352 * At this point, we can let interrupts switch to virtual mode
353 * (the MMU has been setup), so adjust the MSR in the PACA to
354 * have IR and DR set.
355 */
356 cpu_ready_for_interrupts();
357 }
358
359 #endif /* CONFIG_SMP */
360
361 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
use_spinloop(void)362 static bool use_spinloop(void)
363 {
364 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
365 return true;
366
367 /*
368 * When book3e boots from kexec, the ePAPR spin table does
369 * not get used.
370 */
371 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
372 }
373
smp_release_cpus(void)374 void smp_release_cpus(void)
375 {
376 unsigned long *ptr;
377 int i;
378
379 if (!use_spinloop())
380 return;
381
382 DBG(" -> smp_release_cpus()\n");
383
384 /* All secondary cpus are spinning on a common spinloop, release them
385 * all now so they can start to spin on their individual paca
386 * spinloops. For non SMP kernels, the secondary cpus never get out
387 * of the common spinloop.
388 */
389
390 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
391 - PHYSICAL_START);
392 *ptr = ppc_function_entry(generic_secondary_smp_init);
393
394 /* And wait a bit for them to catch up */
395 for (i = 0; i < 100000; i++) {
396 mb();
397 HMT_low();
398 if (spinning_secondaries == 0)
399 break;
400 udelay(1);
401 }
402 DBG("spinning_secondaries = %d\n", spinning_secondaries);
403
404 DBG(" <- smp_release_cpus()\n");
405 }
406 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
407
408 /*
409 * Initialize some remaining members of the ppc64_caches and systemcfg
410 * structures
411 * (at least until we get rid of them completely). This is mostly some
412 * cache informations about the CPU that will be used by cache flush
413 * routines and/or provided to userland
414 */
415
init_cache_info(struct ppc_cache_info * info,u32 size,u32 lsize,u32 bsize,u32 sets)416 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
417 u32 bsize, u32 sets)
418 {
419 info->size = size;
420 info->sets = sets;
421 info->line_size = lsize;
422 info->block_size = bsize;
423 info->log_block_size = __ilog2(bsize);
424 if (bsize)
425 info->blocks_per_page = PAGE_SIZE / bsize;
426 else
427 info->blocks_per_page = 0;
428
429 if (sets == 0)
430 info->assoc = 0xffff;
431 else
432 info->assoc = size / (sets * lsize);
433 }
434
parse_cache_info(struct device_node * np,bool icache,struct ppc_cache_info * info)435 static bool __init parse_cache_info(struct device_node *np,
436 bool icache,
437 struct ppc_cache_info *info)
438 {
439 static const char *ipropnames[] __initdata = {
440 "i-cache-size",
441 "i-cache-sets",
442 "i-cache-block-size",
443 "i-cache-line-size",
444 };
445 static const char *dpropnames[] __initdata = {
446 "d-cache-size",
447 "d-cache-sets",
448 "d-cache-block-size",
449 "d-cache-line-size",
450 };
451 const char **propnames = icache ? ipropnames : dpropnames;
452 const __be32 *sizep, *lsizep, *bsizep, *setsp;
453 u32 size, lsize, bsize, sets;
454 bool success = true;
455
456 size = 0;
457 sets = -1u;
458 lsize = bsize = cur_cpu_spec->dcache_bsize;
459 sizep = of_get_property(np, propnames[0], NULL);
460 if (sizep != NULL)
461 size = be32_to_cpu(*sizep);
462 setsp = of_get_property(np, propnames[1], NULL);
463 if (setsp != NULL)
464 sets = be32_to_cpu(*setsp);
465 bsizep = of_get_property(np, propnames[2], NULL);
466 lsizep = of_get_property(np, propnames[3], NULL);
467 if (bsizep == NULL)
468 bsizep = lsizep;
469 if (lsizep != NULL)
470 lsize = be32_to_cpu(*lsizep);
471 if (bsizep != NULL)
472 bsize = be32_to_cpu(*bsizep);
473 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
474 success = false;
475
476 /*
477 * OF is weird .. it represents fully associative caches
478 * as "1 way" which doesn't make much sense and doesn't
479 * leave room for direct mapped. We'll assume that 0
480 * in OF means direct mapped for that reason.
481 */
482 if (sets == 1)
483 sets = 0;
484 else if (sets == 0)
485 sets = 1;
486
487 init_cache_info(info, size, lsize, bsize, sets);
488
489 return success;
490 }
491
initialize_cache_info(void)492 void __init initialize_cache_info(void)
493 {
494 struct device_node *cpu = NULL, *l2, *l3 = NULL;
495 u32 pvr;
496
497 DBG(" -> initialize_cache_info()\n");
498
499 /*
500 * All shipping POWER8 machines have a firmware bug that
501 * puts incorrect information in the device-tree. This will
502 * be (hopefully) fixed for future chips but for now hard
503 * code the values if we are running on one of these
504 */
505 pvr = PVR_VER(mfspr(SPRN_PVR));
506 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
507 pvr == PVR_POWER8NVL) {
508 /* size lsize blk sets */
509 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
510 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
511 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
512 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
513 } else
514 cpu = of_find_node_by_type(NULL, "cpu");
515
516 /*
517 * We're assuming *all* of the CPUs have the same
518 * d-cache and i-cache sizes... -Peter
519 */
520 if (cpu) {
521 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
522 DBG("Argh, can't find dcache properties !\n");
523
524 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
525 DBG("Argh, can't find icache properties !\n");
526
527 /*
528 * Try to find the L2 and L3 if any. Assume they are
529 * unified and use the D-side properties.
530 */
531 l2 = of_find_next_cache_node(cpu);
532 of_node_put(cpu);
533 if (l2) {
534 parse_cache_info(l2, false, &ppc64_caches.l2);
535 l3 = of_find_next_cache_node(l2);
536 of_node_put(l2);
537 }
538 if (l3) {
539 parse_cache_info(l3, false, &ppc64_caches.l3);
540 of_node_put(l3);
541 }
542 }
543
544 /* For use by binfmt_elf */
545 dcache_bsize = ppc64_caches.l1d.block_size;
546 icache_bsize = ppc64_caches.l1i.block_size;
547
548 cur_cpu_spec->dcache_bsize = dcache_bsize;
549 cur_cpu_spec->icache_bsize = icache_bsize;
550
551 DBG(" <- initialize_cache_info()\n");
552 }
553
554 /* This returns the limit below which memory accesses to the linear
555 * mapping are guarnateed not to cause a TLB or SLB miss. This is
556 * used to allocate interrupt or emergency stacks for which our
557 * exception entry path doesn't deal with being interrupted.
558 */
safe_stack_limit(void)559 static __init u64 safe_stack_limit(void)
560 {
561 #ifdef CONFIG_PPC_BOOK3E
562 /* Freescale BookE bolts the entire linear mapping */
563 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
564 return linear_map_top;
565 /* Other BookE, we assume the first GB is bolted */
566 return 1ul << 30;
567 #else
568 if (early_radix_enabled())
569 return ULONG_MAX;
570
571 /* BookS, the first segment is bolted */
572 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
573 return 1UL << SID_SHIFT_1T;
574 return 1UL << SID_SHIFT;
575 #endif
576 }
577
irqstack_early_init(void)578 void __init irqstack_early_init(void)
579 {
580 u64 limit = safe_stack_limit();
581 unsigned int i;
582
583 /*
584 * Interrupt stacks must be in the first segment since we
585 * cannot afford to take SLB misses on them. They are not
586 * accessed in realmode.
587 */
588 for_each_possible_cpu(i) {
589 softirq_ctx[i] = (struct thread_info *)
590 __va(memblock_alloc_base(THREAD_SIZE,
591 THREAD_SIZE, limit));
592 hardirq_ctx[i] = (struct thread_info *)
593 __va(memblock_alloc_base(THREAD_SIZE,
594 THREAD_SIZE, limit));
595 }
596 }
597
598 #ifdef CONFIG_PPC_BOOK3E
exc_lvl_early_init(void)599 void __init exc_lvl_early_init(void)
600 {
601 unsigned int i;
602 unsigned long sp;
603
604 for_each_possible_cpu(i) {
605 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
606 critirq_ctx[i] = (struct thread_info *)__va(sp);
607 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
608
609 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
610 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
611 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
612
613 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
614 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
615 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
616 }
617
618 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
619 patch_exception(0x040, exc_debug_debug_book3e);
620 }
621 #endif
622
623 /*
624 * Emergency stacks are used for a range of things, from asynchronous
625 * NMIs (system reset, machine check) to synchronous, process context.
626 * We set preempt_count to zero, even though that isn't necessarily correct. To
627 * get the right value we'd need to copy it from the previous thread_info, but
628 * doing that might fault causing more problems.
629 * TODO: what to do with accounting?
630 */
emerg_stack_init_thread_info(struct thread_info * ti,int cpu)631 static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
632 {
633 ti->task = NULL;
634 ti->cpu = cpu;
635 ti->preempt_count = 0;
636 ti->local_flags = 0;
637 ti->flags = 0;
638 klp_init_thread_info(ti);
639 }
640
641 /*
642 * Stack space used when we detect a bad kernel stack pointer, and
643 * early in SMP boots before relocation is enabled. Exclusive emergency
644 * stack for machine checks.
645 */
emergency_stack_init(void)646 void __init emergency_stack_init(void)
647 {
648 u64 limit;
649 unsigned int i;
650
651 /*
652 * Emergency stacks must be under 256MB, we cannot afford to take
653 * SLB misses on them. The ABI also requires them to be 128-byte
654 * aligned.
655 *
656 * Since we use these as temporary stacks during secondary CPU
657 * bringup, machine check, system reset, and HMI, we need to get
658 * at them in real mode. This means they must also be within the RMO
659 * region.
660 *
661 * The IRQ stacks allocated elsewhere in this file are zeroed and
662 * initialized in kernel/irq.c. These are initialized here in order
663 * to have emergency stacks available as early as possible.
664 */
665 limit = min(safe_stack_limit(), ppc64_rma_size);
666
667 for_each_possible_cpu(i) {
668 struct thread_info *ti;
669 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
670 memset(ti, 0, THREAD_SIZE);
671 emerg_stack_init_thread_info(ti, i);
672 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
673
674 #ifdef CONFIG_PPC_BOOK3S_64
675 /* emergency stack for NMI exception handling. */
676 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
677 memset(ti, 0, THREAD_SIZE);
678 emerg_stack_init_thread_info(ti, i);
679 paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE;
680
681 /* emergency stack for machine check exception handling. */
682 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
683 memset(ti, 0, THREAD_SIZE);
684 emerg_stack_init_thread_info(ti, i);
685 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
686 #endif
687 }
688 }
689
690 #ifdef CONFIG_SMP
691 #define PCPU_DYN_SIZE ()
692
pcpu_fc_alloc(unsigned int cpu,size_t size,size_t align)693 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
694 {
695 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
696 __pa(MAX_DMA_ADDRESS));
697 }
698
pcpu_fc_free(void * ptr,size_t size)699 static void __init pcpu_fc_free(void *ptr, size_t size)
700 {
701 free_bootmem(__pa(ptr), size);
702 }
703
pcpu_cpu_distance(unsigned int from,unsigned int to)704 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
705 {
706 if (early_cpu_to_node(from) == early_cpu_to_node(to))
707 return LOCAL_DISTANCE;
708 else
709 return REMOTE_DISTANCE;
710 }
711
712 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
713 EXPORT_SYMBOL(__per_cpu_offset);
714
setup_per_cpu_areas(void)715 void __init setup_per_cpu_areas(void)
716 {
717 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
718 size_t atom_size;
719 unsigned long delta;
720 unsigned int cpu;
721 int rc;
722
723 /*
724 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
725 * to group units. For larger mappings, use 1M atom which
726 * should be large enough to contain a number of units.
727 */
728 if (mmu_linear_psize == MMU_PAGE_4K)
729 atom_size = PAGE_SIZE;
730 else
731 atom_size = 1 << 20;
732
733 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
734 pcpu_fc_alloc, pcpu_fc_free);
735 if (rc < 0)
736 panic("cannot initialize percpu area (err=%d)", rc);
737
738 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
739 for_each_possible_cpu(cpu) {
740 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
741 paca[cpu].data_offset = __per_cpu_offset[cpu];
742 }
743 }
744 #endif
745
746 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
memory_block_size_bytes(void)747 unsigned long memory_block_size_bytes(void)
748 {
749 if (ppc_md.memory_block_size)
750 return ppc_md.memory_block_size();
751
752 return MIN_MEMORY_BLOCK_SIZE;
753 }
754 #endif
755
756 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
757 struct ppc_pci_io ppc_pci_io;
758 EXPORT_SYMBOL(ppc_pci_io);
759 #endif
760
761 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
hw_nmi_get_sample_period(int watchdog_thresh)762 u64 hw_nmi_get_sample_period(int watchdog_thresh)
763 {
764 return ppc_proc_freq * watchdog_thresh;
765 }
766 #endif
767
768 /*
769 * The perf based hardlockup detector breaks PMU event based branches, so
770 * disable it by default. Book3S has a soft-nmi hardlockup detector based
771 * on the decrementer interrupt, so it does not suffer from this problem.
772 *
773 * It is likely to get false positives in VM guests, so disable it there
774 * by default too.
775 */
disable_hardlockup_detector(void)776 static int __init disable_hardlockup_detector(void)
777 {
778 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
779 hardlockup_detector_disable();
780 #else
781 if (firmware_has_feature(FW_FEATURE_LPAR))
782 hardlockup_detector_disable();
783 #endif
784
785 return 0;
786 }
787 early_initcall(disable_hardlockup_detector);
788
789 #ifdef CONFIG_PPC_BOOK3S_64
790 static enum l1d_flush_type enabled_flush_types;
791 static void *l1d_flush_fallback_area;
792 static bool no_rfi_flush;
793 bool rfi_flush;
794
handle_no_rfi_flush(char * p)795 static int __init handle_no_rfi_flush(char *p)
796 {
797 pr_info("rfi-flush: disabled on command line.");
798 no_rfi_flush = true;
799 return 0;
800 }
801 early_param("no_rfi_flush", handle_no_rfi_flush);
802
803 /*
804 * The RFI flush is not KPTI, but because users will see doco that says to use
805 * nopti we hijack that option here to also disable the RFI flush.
806 */
handle_no_pti(char * p)807 static int __init handle_no_pti(char *p)
808 {
809 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
810 handle_no_rfi_flush(NULL);
811 return 0;
812 }
813 early_param("nopti", handle_no_pti);
814
do_nothing(void * unused)815 static void do_nothing(void *unused)
816 {
817 /*
818 * We don't need to do the flush explicitly, just enter+exit kernel is
819 * sufficient, the RFI exit handlers will do the right thing.
820 */
821 }
822
rfi_flush_enable(bool enable)823 void rfi_flush_enable(bool enable)
824 {
825 if (enable) {
826 do_rfi_flush_fixups(enabled_flush_types);
827 on_each_cpu(do_nothing, NULL, 1);
828 } else
829 do_rfi_flush_fixups(L1D_FLUSH_NONE);
830
831 rfi_flush = enable;
832 }
833
init_fallback_flush(void)834 static void __ref init_fallback_flush(void)
835 {
836 u64 l1d_size, limit;
837 int cpu;
838
839 /* Only allocate the fallback flush area once (at boot time). */
840 if (l1d_flush_fallback_area)
841 return;
842
843 l1d_size = ppc64_caches.l1d.size;
844 limit = min(safe_stack_limit(), ppc64_rma_size);
845
846 /*
847 * Align to L1d size, and size it at 2x L1d size, to catch possible
848 * hardware prefetch runoff. We don't have a recipe for load patterns to
849 * reliably avoid the prefetcher.
850 */
851 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
852 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
853
854 for_each_possible_cpu(cpu) {
855 paca[cpu].rfi_flush_fallback_area = l1d_flush_fallback_area;
856 paca[cpu].l1d_flush_size = l1d_size;
857 }
858 }
859
setup_rfi_flush(enum l1d_flush_type types,bool enable)860 void setup_rfi_flush(enum l1d_flush_type types, bool enable)
861 {
862 if (types & L1D_FLUSH_FALLBACK) {
863 pr_info("rfi-flush: fallback displacement flush available\n");
864 init_fallback_flush();
865 }
866
867 if (types & L1D_FLUSH_ORI)
868 pr_info("rfi-flush: ori type flush available\n");
869
870 if (types & L1D_FLUSH_MTTRIG)
871 pr_info("rfi-flush: mttrig type flush available\n");
872
873 enabled_flush_types = types;
874
875 if (!no_rfi_flush && !cpu_mitigations_off())
876 rfi_flush_enable(enable);
877 }
878
879 #ifdef CONFIG_DEBUG_FS
rfi_flush_set(void * data,u64 val)880 static int rfi_flush_set(void *data, u64 val)
881 {
882 bool enable;
883
884 if (val == 1)
885 enable = true;
886 else if (val == 0)
887 enable = false;
888 else
889 return -EINVAL;
890
891 /* Only do anything if we're changing state */
892 if (enable != rfi_flush)
893 rfi_flush_enable(enable);
894
895 return 0;
896 }
897
rfi_flush_get(void * data,u64 * val)898 static int rfi_flush_get(void *data, u64 *val)
899 {
900 *val = rfi_flush ? 1 : 0;
901 return 0;
902 }
903
904 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
905
rfi_flush_debugfs_init(void)906 static __init int rfi_flush_debugfs_init(void)
907 {
908 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
909 return 0;
910 }
911 device_initcall(rfi_flush_debugfs_init);
912 #endif
913 #endif /* CONFIG_PPC_BOOK3S_64 */
914