1 /*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14 /*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/extable.h>
30 #include <linux/module.h> /* print_modules */
31 #include <linux/prctl.h>
32 #include <linux/delay.h>
33 #include <linux/kprobes.h>
34 #include <linux/kexec.h>
35 #include <linux/backlight.h>
36 #include <linux/bug.h>
37 #include <linux/kdebug.h>
38 #include <linux/ratelimit.h>
39 #include <linux/context_tracking.h>
40
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
45 #include <asm/io.h>
46 #include <asm/machdep.h>
47 #include <asm/rtas.h>
48 #include <asm/pmc.h>
49 #include <asm/reg.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
52 #endif
53 #ifdef CONFIG_PPC64
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
56 #include <asm/tm.h>
57 #endif
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
60 #include <asm/rio.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
63 #include <asm/tm.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
66 #include <asm/hmi.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
69
70 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
71 int (*__debugger)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
78
79 EXPORT_SYMBOL(__debugger);
80 EXPORT_SYMBOL(__debugger_ipi);
81 EXPORT_SYMBOL(__debugger_bpt);
82 EXPORT_SYMBOL(__debugger_sstep);
83 EXPORT_SYMBOL(__debugger_iabr_match);
84 EXPORT_SYMBOL(__debugger_break_match);
85 EXPORT_SYMBOL(__debugger_fault_handler);
86 #endif
87
88 /* Transactional Memory trap debug */
89 #ifdef TM_DEBUG_SW
90 #define TM_DEBUG(x...) printk(KERN_INFO x)
91 #else
92 #define TM_DEBUG(x...) do { } while(0)
93 #endif
94
95 /*
96 * Trap & Exception support
97 */
98
99 #ifdef CONFIG_PMAC_BACKLIGHT
pmac_backlight_unblank(void)100 static void pmac_backlight_unblank(void)
101 {
102 mutex_lock(&pmac_backlight_mutex);
103 if (pmac_backlight) {
104 struct backlight_properties *props;
105
106 props = &pmac_backlight->props;
107 props->brightness = props->max_brightness;
108 props->power = FB_BLANK_UNBLANK;
109 backlight_update_status(pmac_backlight);
110 }
111 mutex_unlock(&pmac_backlight_mutex);
112 }
113 #else
pmac_backlight_unblank(void)114 static inline void pmac_backlight_unblank(void) { }
115 #endif
116
117 /*
118 * If oops/die is expected to crash the machine, return true here.
119 *
120 * This should not be expected to be 100% accurate, there may be
121 * notifiers registered or other unexpected conditions that may bring
122 * down the kernel. Or if the current process in the kernel is holding
123 * locks or has other critical state, the kernel may become effectively
124 * unusable anyway.
125 */
die_will_crash(void)126 bool die_will_crash(void)
127 {
128 if (should_fadump_crash())
129 return true;
130 if (kexec_should_crash(current))
131 return true;
132 if (in_interrupt() || panic_on_oops ||
133 !current->pid || is_global_init(current))
134 return true;
135
136 return false;
137 }
138
139 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
140 static int die_owner = -1;
141 static unsigned int die_nest_count;
142 static int die_counter;
143
oops_begin(struct pt_regs * regs)144 static unsigned long oops_begin(struct pt_regs *regs)
145 {
146 int cpu;
147 unsigned long flags;
148
149 oops_enter();
150
151 /* racy, but better than risking deadlock. */
152 raw_local_irq_save(flags);
153 cpu = smp_processor_id();
154 if (!arch_spin_trylock(&die_lock)) {
155 if (cpu == die_owner)
156 /* nested oops. should stop eventually */;
157 else
158 arch_spin_lock(&die_lock);
159 }
160 die_nest_count++;
161 die_owner = cpu;
162 console_verbose();
163 bust_spinlocks(1);
164 if (machine_is(powermac))
165 pmac_backlight_unblank();
166 return flags;
167 }
168 NOKPROBE_SYMBOL(oops_begin);
169
oops_end(unsigned long flags,struct pt_regs * regs,int signr)170 static void oops_end(unsigned long flags, struct pt_regs *regs,
171 int signr)
172 {
173 bust_spinlocks(0);
174 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
175 die_nest_count--;
176 oops_exit();
177 printk("\n");
178 if (!die_nest_count) {
179 /* Nest count reaches zero, release the lock. */
180 die_owner = -1;
181 arch_spin_unlock(&die_lock);
182 }
183 raw_local_irq_restore(flags);
184
185 /*
186 * system_reset_excption handles debugger, crash dump, panic, for 0x100
187 */
188 if (TRAP(regs) == 0x100)
189 return;
190
191 crash_fadump(regs, "die oops");
192
193 if (kexec_should_crash(current))
194 crash_kexec(regs);
195
196 if (!signr)
197 return;
198
199 /*
200 * While our oops output is serialised by a spinlock, output
201 * from panic() called below can race and corrupt it. If we
202 * know we are going to panic, delay for 1 second so we have a
203 * chance to get clean backtraces from all CPUs that are oopsing.
204 */
205 if (in_interrupt() || panic_on_oops || !current->pid ||
206 is_global_init(current)) {
207 mdelay(MSEC_PER_SEC);
208 }
209
210 if (in_interrupt())
211 panic("Fatal exception in interrupt");
212 if (panic_on_oops)
213 panic("Fatal exception");
214 do_exit(signr);
215 }
216 NOKPROBE_SYMBOL(oops_end);
217
__die(const char * str,struct pt_regs * regs,long err)218 static int __die(const char *str, struct pt_regs *regs, long err)
219 {
220 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
221
222 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
223 printk("LE ");
224 else
225 printk("BE ");
226
227 if (IS_ENABLED(CONFIG_PREEMPT))
228 pr_cont("PREEMPT ");
229
230 if (IS_ENABLED(CONFIG_SMP))
231 pr_cont("SMP NR_CPUS=%d ", NR_CPUS);
232
233 if (debug_pagealloc_enabled())
234 pr_cont("DEBUG_PAGEALLOC ");
235
236 if (IS_ENABLED(CONFIG_NUMA))
237 pr_cont("NUMA ");
238
239 pr_cont("%s\n", ppc_md.name ? ppc_md.name : "");
240
241 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
242 return 1;
243
244 print_modules();
245 show_regs(regs);
246
247 return 0;
248 }
249 NOKPROBE_SYMBOL(__die);
250
die(const char * str,struct pt_regs * regs,long err)251 void die(const char *str, struct pt_regs *regs, long err)
252 {
253 unsigned long flags;
254
255 /*
256 * system_reset_excption handles debugger, crash dump, panic, for 0x100
257 */
258 if (TRAP(regs) != 0x100) {
259 if (debugger(regs))
260 return;
261 }
262
263 flags = oops_begin(regs);
264 if (__die(str, regs, err))
265 err = 0;
266 oops_end(flags, regs, err);
267 }
268 NOKPROBE_SYMBOL(die);
269
user_single_step_siginfo(struct task_struct * tsk,struct pt_regs * regs,siginfo_t * info)270 void user_single_step_siginfo(struct task_struct *tsk,
271 struct pt_regs *regs, siginfo_t *info)
272 {
273 memset(info, 0, sizeof(*info));
274 info->si_signo = SIGTRAP;
275 info->si_code = TRAP_TRACE;
276 info->si_addr = (void __user *)regs->nip;
277 }
278
_exception(int signr,struct pt_regs * regs,int code,unsigned long addr)279 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
280 {
281 siginfo_t info;
282 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
283 "at %08lx nip %08lx lr %08lx code %x\n";
284 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
285 "at %016lx nip %016lx lr %016lx code %x\n";
286
287 if (!user_mode(regs)) {
288 die("Exception in kernel mode", regs, signr);
289 return;
290 }
291
292 if (show_unhandled_signals && unhandled_signal(current, signr)) {
293 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
294 current->comm, current->pid, signr,
295 addr, regs->nip, regs->link, code);
296 }
297
298 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
299 local_irq_enable();
300
301 current->thread.trap_nr = code;
302 memset(&info, 0, sizeof(info));
303 info.si_signo = signr;
304 info.si_code = code;
305 info.si_addr = (void __user *) addr;
306 force_sig_info(signr, &info, current);
307 }
308
system_reset_exception(struct pt_regs * regs)309 void system_reset_exception(struct pt_regs *regs)
310 {
311 /*
312 * Avoid crashes in case of nested NMI exceptions. Recoverability
313 * is determined by RI and in_nmi
314 */
315 bool nested = in_nmi();
316 if (!nested)
317 nmi_enter();
318
319 __this_cpu_inc(irq_stat.sreset_irqs);
320
321 /* See if any machine dependent calls */
322 if (ppc_md.system_reset_exception) {
323 if (ppc_md.system_reset_exception(regs))
324 goto out;
325 }
326
327 if (debugger(regs))
328 goto out;
329
330 /*
331 * A system reset is a request to dump, so we always send
332 * it through the crashdump code (if fadump or kdump are
333 * registered).
334 */
335 crash_fadump(regs, "System Reset");
336
337 crash_kexec(regs);
338
339 /*
340 * We aren't the primary crash CPU. We need to send it
341 * to a holding pattern to avoid it ending up in the panic
342 * code.
343 */
344 crash_kexec_secondary(regs);
345
346 /*
347 * No debugger or crash dump registered, print logs then
348 * panic.
349 */
350 die("System Reset", regs, SIGABRT);
351
352 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
353 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
354 nmi_panic(regs, "System Reset");
355
356 out:
357 #ifdef CONFIG_PPC_BOOK3S_64
358 BUG_ON(get_paca()->in_nmi == 0);
359 if (get_paca()->in_nmi > 1)
360 nmi_panic(regs, "Unrecoverable nested System Reset");
361 #endif
362 /* Must die if the interrupt is not recoverable */
363 if (!(regs->msr & MSR_RI))
364 nmi_panic(regs, "Unrecoverable System Reset");
365
366 if (!nested)
367 nmi_exit();
368
369 /* What should we do here? We could issue a shutdown or hard reset. */
370 }
371
372 /*
373 * I/O accesses can cause machine checks on powermacs.
374 * Check if the NIP corresponds to the address of a sync
375 * instruction for which there is an entry in the exception
376 * table.
377 * Note that the 601 only takes a machine check on TEA
378 * (transfer error ack) signal assertion, and does not
379 * set any of the top 16 bits of SRR1.
380 * -- paulus.
381 */
check_io_access(struct pt_regs * regs)382 static inline int check_io_access(struct pt_regs *regs)
383 {
384 #ifdef CONFIG_PPC32
385 unsigned long msr = regs->msr;
386 const struct exception_table_entry *entry;
387 unsigned int *nip = (unsigned int *)regs->nip;
388
389 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
390 && (entry = search_exception_tables(regs->nip)) != NULL) {
391 /*
392 * Check that it's a sync instruction, or somewhere
393 * in the twi; isync; nop sequence that inb/inw/inl uses.
394 * As the address is in the exception table
395 * we should be able to read the instr there.
396 * For the debug message, we look at the preceding
397 * load or store.
398 */
399 if (*nip == PPC_INST_NOP)
400 nip -= 2;
401 else if (*nip == PPC_INST_ISYNC)
402 --nip;
403 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
404 unsigned int rb;
405
406 --nip;
407 rb = (*nip >> 11) & 0x1f;
408 printk(KERN_DEBUG "%s bad port %lx at %p\n",
409 (*nip & 0x100)? "OUT to": "IN from",
410 regs->gpr[rb] - _IO_BASE, nip);
411 regs->msr |= MSR_RI;
412 regs->nip = extable_fixup(entry);
413 return 1;
414 }
415 }
416 #endif /* CONFIG_PPC32 */
417 return 0;
418 }
419
420 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
421 /* On 4xx, the reason for the machine check or program exception
422 is in the ESR. */
423 #define get_reason(regs) ((regs)->dsisr)
424 #define REASON_FP ESR_FP
425 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
426 #define REASON_PRIVILEGED ESR_PPR
427 #define REASON_TRAP ESR_PTR
428
429 /* single-step stuff */
430 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
431 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
432
433 #else
434 /* On non-4xx, the reason for the machine check or program
435 exception is in the MSR. */
436 #define get_reason(regs) ((regs)->msr)
437 #define REASON_TM SRR1_PROGTM
438 #define REASON_FP SRR1_PROGFPE
439 #define REASON_ILLEGAL SRR1_PROGILL
440 #define REASON_PRIVILEGED SRR1_PROGPRIV
441 #define REASON_TRAP SRR1_PROGTRAP
442
443 #define single_stepping(regs) ((regs)->msr & MSR_SE)
444 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
445 #endif
446
447 #if defined(CONFIG_E500)
machine_check_e500mc(struct pt_regs * regs)448 int machine_check_e500mc(struct pt_regs *regs)
449 {
450 unsigned long mcsr = mfspr(SPRN_MCSR);
451 unsigned long pvr = mfspr(SPRN_PVR);
452 unsigned long reason = mcsr;
453 int recoverable = 1;
454
455 if (reason & MCSR_LD) {
456 recoverable = fsl_rio_mcheck_exception(regs);
457 if (recoverable == 1)
458 goto silent_out;
459 }
460
461 printk("Machine check in kernel mode.\n");
462 printk("Caused by (from MCSR=%lx): ", reason);
463
464 if (reason & MCSR_MCP)
465 printk("Machine Check Signal\n");
466
467 if (reason & MCSR_ICPERR) {
468 printk("Instruction Cache Parity Error\n");
469
470 /*
471 * This is recoverable by invalidating the i-cache.
472 */
473 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
474 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
475 ;
476
477 /*
478 * This will generally be accompanied by an instruction
479 * fetch error report -- only treat MCSR_IF as fatal
480 * if it wasn't due to an L1 parity error.
481 */
482 reason &= ~MCSR_IF;
483 }
484
485 if (reason & MCSR_DCPERR_MC) {
486 printk("Data Cache Parity Error\n");
487
488 /*
489 * In write shadow mode we auto-recover from the error, but it
490 * may still get logged and cause a machine check. We should
491 * only treat the non-write shadow case as non-recoverable.
492 */
493 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
494 * is not implemented but L1 data cache always runs in write
495 * shadow mode. Hence on data cache parity errors HW will
496 * automatically invalidate the L1 Data Cache.
497 */
498 if (PVR_VER(pvr) != PVR_VER_E6500) {
499 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
500 recoverable = 0;
501 }
502 }
503
504 if (reason & MCSR_L2MMU_MHIT) {
505 printk("Hit on multiple TLB entries\n");
506 recoverable = 0;
507 }
508
509 if (reason & MCSR_NMI)
510 printk("Non-maskable interrupt\n");
511
512 if (reason & MCSR_IF) {
513 printk("Instruction Fetch Error Report\n");
514 recoverable = 0;
515 }
516
517 if (reason & MCSR_LD) {
518 printk("Load Error Report\n");
519 recoverable = 0;
520 }
521
522 if (reason & MCSR_ST) {
523 printk("Store Error Report\n");
524 recoverable = 0;
525 }
526
527 if (reason & MCSR_LDG) {
528 printk("Guarded Load Error Report\n");
529 recoverable = 0;
530 }
531
532 if (reason & MCSR_TLBSYNC)
533 printk("Simultaneous tlbsync operations\n");
534
535 if (reason & MCSR_BSL2_ERR) {
536 printk("Level 2 Cache Error\n");
537 recoverable = 0;
538 }
539
540 if (reason & MCSR_MAV) {
541 u64 addr;
542
543 addr = mfspr(SPRN_MCAR);
544 addr |= (u64)mfspr(SPRN_MCARU) << 32;
545
546 printk("Machine Check %s Address: %#llx\n",
547 reason & MCSR_MEA ? "Effective" : "Physical", addr);
548 }
549
550 silent_out:
551 mtspr(SPRN_MCSR, mcsr);
552 return mfspr(SPRN_MCSR) == 0 && recoverable;
553 }
554
machine_check_e500(struct pt_regs * regs)555 int machine_check_e500(struct pt_regs *regs)
556 {
557 unsigned long reason = mfspr(SPRN_MCSR);
558
559 if (reason & MCSR_BUS_RBERR) {
560 if (fsl_rio_mcheck_exception(regs))
561 return 1;
562 if (fsl_pci_mcheck_exception(regs))
563 return 1;
564 }
565
566 printk("Machine check in kernel mode.\n");
567 printk("Caused by (from MCSR=%lx): ", reason);
568
569 if (reason & MCSR_MCP)
570 printk("Machine Check Signal\n");
571 if (reason & MCSR_ICPERR)
572 printk("Instruction Cache Parity Error\n");
573 if (reason & MCSR_DCP_PERR)
574 printk("Data Cache Push Parity Error\n");
575 if (reason & MCSR_DCPERR)
576 printk("Data Cache Parity Error\n");
577 if (reason & MCSR_BUS_IAERR)
578 printk("Bus - Instruction Address Error\n");
579 if (reason & MCSR_BUS_RAERR)
580 printk("Bus - Read Address Error\n");
581 if (reason & MCSR_BUS_WAERR)
582 printk("Bus - Write Address Error\n");
583 if (reason & MCSR_BUS_IBERR)
584 printk("Bus - Instruction Data Error\n");
585 if (reason & MCSR_BUS_RBERR)
586 printk("Bus - Read Data Bus Error\n");
587 if (reason & MCSR_BUS_WBERR)
588 printk("Bus - Write Data Bus Error\n");
589 if (reason & MCSR_BUS_IPERR)
590 printk("Bus - Instruction Parity Error\n");
591 if (reason & MCSR_BUS_RPERR)
592 printk("Bus - Read Parity Error\n");
593
594 return 0;
595 }
596
machine_check_generic(struct pt_regs * regs)597 int machine_check_generic(struct pt_regs *regs)
598 {
599 return 0;
600 }
601 #elif defined(CONFIG_E200)
machine_check_e200(struct pt_regs * regs)602 int machine_check_e200(struct pt_regs *regs)
603 {
604 unsigned long reason = mfspr(SPRN_MCSR);
605
606 printk("Machine check in kernel mode.\n");
607 printk("Caused by (from MCSR=%lx): ", reason);
608
609 if (reason & MCSR_MCP)
610 printk("Machine Check Signal\n");
611 if (reason & MCSR_CP_PERR)
612 printk("Cache Push Parity Error\n");
613 if (reason & MCSR_CPERR)
614 printk("Cache Parity Error\n");
615 if (reason & MCSR_EXCP_ERR)
616 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
617 if (reason & MCSR_BUS_IRERR)
618 printk("Bus - Read Bus Error on instruction fetch\n");
619 if (reason & MCSR_BUS_DRERR)
620 printk("Bus - Read Bus Error on data load\n");
621 if (reason & MCSR_BUS_WRERR)
622 printk("Bus - Write Bus Error on buffered store or cache line push\n");
623
624 return 0;
625 }
626 #elif defined(CONFIG_PPC32)
machine_check_generic(struct pt_regs * regs)627 int machine_check_generic(struct pt_regs *regs)
628 {
629 unsigned long reason = regs->msr;
630
631 printk("Machine check in kernel mode.\n");
632 printk("Caused by (from SRR1=%lx): ", reason);
633 switch (reason & 0x601F0000) {
634 case 0x80000:
635 printk("Machine check signal\n");
636 break;
637 case 0: /* for 601 */
638 case 0x40000:
639 case 0x140000: /* 7450 MSS error and TEA */
640 printk("Transfer error ack signal\n");
641 break;
642 case 0x20000:
643 printk("Data parity error signal\n");
644 break;
645 case 0x10000:
646 printk("Address parity error signal\n");
647 break;
648 case 0x20000000:
649 printk("L1 Data Cache error\n");
650 break;
651 case 0x40000000:
652 printk("L1 Instruction Cache error\n");
653 break;
654 case 0x00100000:
655 printk("L2 data cache parity error\n");
656 break;
657 default:
658 printk("Unknown values in msr\n");
659 }
660 return 0;
661 }
662 #endif /* everything else */
663
machine_check_exception(struct pt_regs * regs)664 void machine_check_exception(struct pt_regs *regs)
665 {
666 int recover = 0;
667 bool nested = in_nmi();
668 if (!nested)
669 nmi_enter();
670
671 /* 64s accounts the mce in machine_check_early when in HVMODE */
672 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
673 __this_cpu_inc(irq_stat.mce_exceptions);
674
675 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
676
677 /* See if any machine dependent calls. In theory, we would want
678 * to call the CPU first, and call the ppc_md. one if the CPU
679 * one returns a positive number. However there is existing code
680 * that assumes the board gets a first chance, so let's keep it
681 * that way for now and fix things later. --BenH.
682 */
683 if (ppc_md.machine_check_exception)
684 recover = ppc_md.machine_check_exception(regs);
685 else if (cur_cpu_spec->machine_check)
686 recover = cur_cpu_spec->machine_check(regs);
687
688 if (recover > 0)
689 goto bail;
690
691 if (debugger_fault_handler(regs))
692 goto bail;
693
694 if (check_io_access(regs))
695 goto bail;
696
697 if (!nested)
698 nmi_exit();
699
700 die("Machine check", regs, SIGBUS);
701
702 /* Must die if the interrupt is not recoverable */
703 if (!(regs->msr & MSR_RI))
704 nmi_panic(regs, "Unrecoverable Machine check");
705
706 return;
707
708 bail:
709 if (!nested)
710 nmi_exit();
711 }
712
SMIException(struct pt_regs * regs)713 void SMIException(struct pt_regs *regs)
714 {
715 die("System Management Interrupt", regs, SIGABRT);
716 }
717
handle_hmi_exception(struct pt_regs * regs)718 void handle_hmi_exception(struct pt_regs *regs)
719 {
720 struct pt_regs *old_regs;
721
722 old_regs = set_irq_regs(regs);
723 irq_enter();
724
725 if (ppc_md.handle_hmi_exception)
726 ppc_md.handle_hmi_exception(regs);
727
728 irq_exit();
729 set_irq_regs(old_regs);
730 }
731
unknown_exception(struct pt_regs * regs)732 void unknown_exception(struct pt_regs *regs)
733 {
734 enum ctx_state prev_state = exception_enter();
735
736 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
737 regs->nip, regs->msr, regs->trap);
738
739 _exception(SIGTRAP, regs, 0, 0);
740
741 exception_exit(prev_state);
742 }
743
instruction_breakpoint_exception(struct pt_regs * regs)744 void instruction_breakpoint_exception(struct pt_regs *regs)
745 {
746 enum ctx_state prev_state = exception_enter();
747
748 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
749 5, SIGTRAP) == NOTIFY_STOP)
750 goto bail;
751 if (debugger_iabr_match(regs))
752 goto bail;
753 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
754
755 bail:
756 exception_exit(prev_state);
757 }
758
RunModeException(struct pt_regs * regs)759 void RunModeException(struct pt_regs *regs)
760 {
761 _exception(SIGTRAP, regs, 0, 0);
762 }
763
single_step_exception(struct pt_regs * regs)764 void single_step_exception(struct pt_regs *regs)
765 {
766 enum ctx_state prev_state = exception_enter();
767
768 clear_single_step(regs);
769
770 if (kprobe_post_handler(regs))
771 return;
772
773 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
774 5, SIGTRAP) == NOTIFY_STOP)
775 goto bail;
776 if (debugger_sstep(regs))
777 goto bail;
778
779 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
780
781 bail:
782 exception_exit(prev_state);
783 }
784 NOKPROBE_SYMBOL(single_step_exception);
785
786 /*
787 * After we have successfully emulated an instruction, we have to
788 * check if the instruction was being single-stepped, and if so,
789 * pretend we got a single-step exception. This was pointed out
790 * by Kumar Gala. -- paulus
791 */
emulate_single_step(struct pt_regs * regs)792 static void emulate_single_step(struct pt_regs *regs)
793 {
794 if (single_stepping(regs))
795 single_step_exception(regs);
796 }
797
__parse_fpscr(unsigned long fpscr)798 static inline int __parse_fpscr(unsigned long fpscr)
799 {
800 int ret = 0;
801
802 /* Invalid operation */
803 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
804 ret = FPE_FLTINV;
805
806 /* Overflow */
807 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
808 ret = FPE_FLTOVF;
809
810 /* Underflow */
811 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
812 ret = FPE_FLTUND;
813
814 /* Divide by zero */
815 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
816 ret = FPE_FLTDIV;
817
818 /* Inexact result */
819 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
820 ret = FPE_FLTRES;
821
822 return ret;
823 }
824
parse_fpe(struct pt_regs * regs)825 static void parse_fpe(struct pt_regs *regs)
826 {
827 int code = 0;
828
829 flush_fp_to_thread(current);
830
831 code = __parse_fpscr(current->thread.fp_state.fpscr);
832
833 _exception(SIGFPE, regs, code, regs->nip);
834 }
835
836 /*
837 * Illegal instruction emulation support. Originally written to
838 * provide the PVR to user applications using the mfspr rd, PVR.
839 * Return non-zero if we can't emulate, or -EFAULT if the associated
840 * memory access caused an access fault. Return zero on success.
841 *
842 * There are a couple of ways to do this, either "decode" the instruction
843 * or directly match lots of bits. In this case, matching lots of
844 * bits is faster and easier.
845 *
846 */
emulate_string_inst(struct pt_regs * regs,u32 instword)847 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
848 {
849 u8 rT = (instword >> 21) & 0x1f;
850 u8 rA = (instword >> 16) & 0x1f;
851 u8 NB_RB = (instword >> 11) & 0x1f;
852 u32 num_bytes;
853 unsigned long EA;
854 int pos = 0;
855
856 /* Early out if we are an invalid form of lswx */
857 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
858 if ((rT == rA) || (rT == NB_RB))
859 return -EINVAL;
860
861 EA = (rA == 0) ? 0 : regs->gpr[rA];
862
863 switch (instword & PPC_INST_STRING_MASK) {
864 case PPC_INST_LSWX:
865 case PPC_INST_STSWX:
866 EA += NB_RB;
867 num_bytes = regs->xer & 0x7f;
868 break;
869 case PPC_INST_LSWI:
870 case PPC_INST_STSWI:
871 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
872 break;
873 default:
874 return -EINVAL;
875 }
876
877 while (num_bytes != 0)
878 {
879 u8 val;
880 u32 shift = 8 * (3 - (pos & 0x3));
881
882 /* if process is 32-bit, clear upper 32 bits of EA */
883 if ((regs->msr & MSR_64BIT) == 0)
884 EA &= 0xFFFFFFFF;
885
886 switch ((instword & PPC_INST_STRING_MASK)) {
887 case PPC_INST_LSWX:
888 case PPC_INST_LSWI:
889 if (get_user(val, (u8 __user *)EA))
890 return -EFAULT;
891 /* first time updating this reg,
892 * zero it out */
893 if (pos == 0)
894 regs->gpr[rT] = 0;
895 regs->gpr[rT] |= val << shift;
896 break;
897 case PPC_INST_STSWI:
898 case PPC_INST_STSWX:
899 val = regs->gpr[rT] >> shift;
900 if (put_user(val, (u8 __user *)EA))
901 return -EFAULT;
902 break;
903 }
904 /* move EA to next address */
905 EA += 1;
906 num_bytes--;
907
908 /* manage our position within the register */
909 if (++pos == 4) {
910 pos = 0;
911 if (++rT == 32)
912 rT = 0;
913 }
914 }
915
916 return 0;
917 }
918
emulate_popcntb_inst(struct pt_regs * regs,u32 instword)919 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
920 {
921 u32 ra,rs;
922 unsigned long tmp;
923
924 ra = (instword >> 16) & 0x1f;
925 rs = (instword >> 21) & 0x1f;
926
927 tmp = regs->gpr[rs];
928 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
929 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
930 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
931 regs->gpr[ra] = tmp;
932
933 return 0;
934 }
935
emulate_isel(struct pt_regs * regs,u32 instword)936 static int emulate_isel(struct pt_regs *regs, u32 instword)
937 {
938 u8 rT = (instword >> 21) & 0x1f;
939 u8 rA = (instword >> 16) & 0x1f;
940 u8 rB = (instword >> 11) & 0x1f;
941 u8 BC = (instword >> 6) & 0x1f;
942 u8 bit;
943 unsigned long tmp;
944
945 tmp = (rA == 0) ? 0 : regs->gpr[rA];
946 bit = (regs->ccr >> (31 - BC)) & 0x1;
947
948 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
949
950 return 0;
951 }
952
953 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
tm_abort_check(struct pt_regs * regs,int cause)954 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
955 {
956 /* If we're emulating a load/store in an active transaction, we cannot
957 * emulate it as the kernel operates in transaction suspended context.
958 * We need to abort the transaction. This creates a persistent TM
959 * abort so tell the user what caused it with a new code.
960 */
961 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
962 tm_enable();
963 tm_abort(cause);
964 return true;
965 }
966 return false;
967 }
968 #else
tm_abort_check(struct pt_regs * regs,int reason)969 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
970 {
971 return false;
972 }
973 #endif
974
emulate_instruction(struct pt_regs * regs)975 static int emulate_instruction(struct pt_regs *regs)
976 {
977 u32 instword;
978 u32 rd;
979
980 if (!user_mode(regs))
981 return -EINVAL;
982 CHECK_FULL_REGS(regs);
983
984 if (get_user(instword, (u32 __user *)(regs->nip)))
985 return -EFAULT;
986
987 /* Emulate the mfspr rD, PVR. */
988 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
989 PPC_WARN_EMULATED(mfpvr, regs);
990 rd = (instword >> 21) & 0x1f;
991 regs->gpr[rd] = mfspr(SPRN_PVR);
992 return 0;
993 }
994
995 /* Emulating the dcba insn is just a no-op. */
996 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
997 PPC_WARN_EMULATED(dcba, regs);
998 return 0;
999 }
1000
1001 /* Emulate the mcrxr insn. */
1002 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1003 int shift = (instword >> 21) & 0x1c;
1004 unsigned long msk = 0xf0000000UL >> shift;
1005
1006 PPC_WARN_EMULATED(mcrxr, regs);
1007 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1008 regs->xer &= ~0xf0000000UL;
1009 return 0;
1010 }
1011
1012 /* Emulate load/store string insn. */
1013 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1014 if (tm_abort_check(regs,
1015 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1016 return -EINVAL;
1017 PPC_WARN_EMULATED(string, regs);
1018 return emulate_string_inst(regs, instword);
1019 }
1020
1021 /* Emulate the popcntb (Population Count Bytes) instruction. */
1022 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1023 PPC_WARN_EMULATED(popcntb, regs);
1024 return emulate_popcntb_inst(regs, instword);
1025 }
1026
1027 /* Emulate isel (Integer Select) instruction */
1028 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1029 PPC_WARN_EMULATED(isel, regs);
1030 return emulate_isel(regs, instword);
1031 }
1032
1033 /* Emulate sync instruction variants */
1034 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1035 PPC_WARN_EMULATED(sync, regs);
1036 asm volatile("sync");
1037 return 0;
1038 }
1039
1040 #ifdef CONFIG_PPC64
1041 /* Emulate the mfspr rD, DSCR. */
1042 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1043 PPC_INST_MFSPR_DSCR_USER) ||
1044 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1045 PPC_INST_MFSPR_DSCR)) &&
1046 cpu_has_feature(CPU_FTR_DSCR)) {
1047 PPC_WARN_EMULATED(mfdscr, regs);
1048 rd = (instword >> 21) & 0x1f;
1049 regs->gpr[rd] = mfspr(SPRN_DSCR);
1050 return 0;
1051 }
1052 /* Emulate the mtspr DSCR, rD. */
1053 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1054 PPC_INST_MTSPR_DSCR_USER) ||
1055 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1056 PPC_INST_MTSPR_DSCR)) &&
1057 cpu_has_feature(CPU_FTR_DSCR)) {
1058 PPC_WARN_EMULATED(mtdscr, regs);
1059 rd = (instword >> 21) & 0x1f;
1060 current->thread.dscr = regs->gpr[rd];
1061 current->thread.dscr_inherit = 1;
1062 mtspr(SPRN_DSCR, current->thread.dscr);
1063 return 0;
1064 }
1065 #endif
1066
1067 return -EINVAL;
1068 }
1069
is_valid_bugaddr(unsigned long addr)1070 int is_valid_bugaddr(unsigned long addr)
1071 {
1072 return is_kernel_addr(addr);
1073 }
1074
1075 #ifdef CONFIG_MATH_EMULATION
emulate_math(struct pt_regs * regs)1076 static int emulate_math(struct pt_regs *regs)
1077 {
1078 int ret;
1079 extern int do_mathemu(struct pt_regs *regs);
1080
1081 ret = do_mathemu(regs);
1082 if (ret >= 0)
1083 PPC_WARN_EMULATED(math, regs);
1084
1085 switch (ret) {
1086 case 0:
1087 emulate_single_step(regs);
1088 return 0;
1089 case 1: {
1090 int code = 0;
1091 code = __parse_fpscr(current->thread.fp_state.fpscr);
1092 _exception(SIGFPE, regs, code, regs->nip);
1093 return 0;
1094 }
1095 case -EFAULT:
1096 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1097 return 0;
1098 }
1099
1100 return -1;
1101 }
1102 #else
emulate_math(struct pt_regs * regs)1103 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1104 #endif
1105
program_check_exception(struct pt_regs * regs)1106 void program_check_exception(struct pt_regs *regs)
1107 {
1108 enum ctx_state prev_state = exception_enter();
1109 unsigned int reason = get_reason(regs);
1110
1111 /* We can now get here via a FP Unavailable exception if the core
1112 * has no FPU, in that case the reason flags will be 0 */
1113
1114 if (reason & REASON_FP) {
1115 /* IEEE FP exception */
1116 parse_fpe(regs);
1117 goto bail;
1118 }
1119 if (reason & REASON_TRAP) {
1120 unsigned long bugaddr;
1121 /* Debugger is first in line to stop recursive faults in
1122 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1123 if (debugger_bpt(regs))
1124 goto bail;
1125
1126 if (kprobe_handler(regs))
1127 goto bail;
1128
1129 /* trap exception */
1130 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1131 == NOTIFY_STOP)
1132 goto bail;
1133
1134 bugaddr = regs->nip;
1135 /*
1136 * Fixup bugaddr for BUG_ON() in real mode
1137 */
1138 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1139 bugaddr += PAGE_OFFSET;
1140
1141 if (!(regs->msr & MSR_PR) && /* not user-mode */
1142 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1143 regs->nip += 4;
1144 goto bail;
1145 }
1146 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1147 goto bail;
1148 }
1149 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1150 if (reason & REASON_TM) {
1151 /* This is a TM "Bad Thing Exception" program check.
1152 * This occurs when:
1153 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1154 * transition in TM states.
1155 * - A trechkpt is attempted when transactional.
1156 * - A treclaim is attempted when non transactional.
1157 * - A tend is illegally attempted.
1158 * - writing a TM SPR when transactional.
1159 */
1160 if (!user_mode(regs) &&
1161 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1162 regs->nip += 4;
1163 goto bail;
1164 }
1165 /* If usermode caused this, it's done something illegal and
1166 * gets a SIGILL slap on the wrist. We call it an illegal
1167 * operand to distinguish from the instruction just being bad
1168 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1169 * illegal /placement/ of a valid instruction.
1170 */
1171 if (user_mode(regs)) {
1172 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1173 goto bail;
1174 } else {
1175 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1176 "at %lx (msr 0x%x)\n", regs->nip, reason);
1177 die("Unrecoverable exception", regs, SIGABRT);
1178 }
1179 }
1180 #endif
1181
1182 /*
1183 * If we took the program check in the kernel skip down to sending a
1184 * SIGILL. The subsequent cases all relate to emulating instructions
1185 * which we should only do for userspace. We also do not want to enable
1186 * interrupts for kernel faults because that might lead to further
1187 * faults, and loose the context of the original exception.
1188 */
1189 if (!user_mode(regs))
1190 goto sigill;
1191
1192 /* We restore the interrupt state now */
1193 if (!arch_irq_disabled_regs(regs))
1194 local_irq_enable();
1195
1196 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1197 * but there seems to be a hardware bug on the 405GP (RevD)
1198 * that means ESR is sometimes set incorrectly - either to
1199 * ESR_DST (!?) or 0. In the process of chasing this with the
1200 * hardware people - not sure if it can happen on any illegal
1201 * instruction or only on FP instructions, whether there is a
1202 * pattern to occurrences etc. -dgibson 31/Mar/2003
1203 */
1204 if (!emulate_math(regs))
1205 goto bail;
1206
1207 /* Try to emulate it if we should. */
1208 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1209 switch (emulate_instruction(regs)) {
1210 case 0:
1211 regs->nip += 4;
1212 emulate_single_step(regs);
1213 goto bail;
1214 case -EFAULT:
1215 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1216 goto bail;
1217 }
1218 }
1219
1220 sigill:
1221 if (reason & REASON_PRIVILEGED)
1222 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1223 else
1224 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1225
1226 bail:
1227 exception_exit(prev_state);
1228 }
1229 NOKPROBE_SYMBOL(program_check_exception);
1230
1231 /*
1232 * This occurs when running in hypervisor mode on POWER6 or later
1233 * and an illegal instruction is encountered.
1234 */
emulation_assist_interrupt(struct pt_regs * regs)1235 void emulation_assist_interrupt(struct pt_regs *regs)
1236 {
1237 regs->msr |= REASON_ILLEGAL;
1238 program_check_exception(regs);
1239 }
1240 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1241
alignment_exception(struct pt_regs * regs)1242 void alignment_exception(struct pt_regs *regs)
1243 {
1244 enum ctx_state prev_state = exception_enter();
1245 int sig, code, fixed = 0;
1246
1247 /* We restore the interrupt state now */
1248 if (!arch_irq_disabled_regs(regs))
1249 local_irq_enable();
1250
1251 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1252 goto bail;
1253
1254 /* we don't implement logging of alignment exceptions */
1255 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1256 fixed = fix_alignment(regs);
1257
1258 if (fixed == 1) {
1259 regs->nip += 4; /* skip over emulated instruction */
1260 emulate_single_step(regs);
1261 goto bail;
1262 }
1263
1264 /* Operand address was bad */
1265 if (fixed == -EFAULT) {
1266 sig = SIGSEGV;
1267 code = SEGV_ACCERR;
1268 } else {
1269 sig = SIGBUS;
1270 code = BUS_ADRALN;
1271 }
1272 if (user_mode(regs))
1273 _exception(sig, regs, code, regs->dar);
1274 else
1275 bad_page_fault(regs, regs->dar, sig);
1276
1277 bail:
1278 exception_exit(prev_state);
1279 }
1280
slb_miss_bad_addr(struct pt_regs * regs)1281 void slb_miss_bad_addr(struct pt_regs *regs)
1282 {
1283 enum ctx_state prev_state = exception_enter();
1284
1285 if (user_mode(regs))
1286 _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar);
1287 else
1288 bad_page_fault(regs, regs->dar, SIGSEGV);
1289
1290 exception_exit(prev_state);
1291 }
1292
StackOverflow(struct pt_regs * regs)1293 void StackOverflow(struct pt_regs *regs)
1294 {
1295 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1296 current->comm, task_pid_nr(current), regs->gpr[1]);
1297 debugger(regs);
1298 show_regs(regs);
1299 panic("kernel stack overflow");
1300 }
1301
nonrecoverable_exception(struct pt_regs * regs)1302 void nonrecoverable_exception(struct pt_regs *regs)
1303 {
1304 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1305 regs->nip, regs->msr);
1306 debugger(regs);
1307 die("nonrecoverable exception", regs, SIGKILL);
1308 }
1309
kernel_fp_unavailable_exception(struct pt_regs * regs)1310 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1311 {
1312 enum ctx_state prev_state = exception_enter();
1313
1314 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1315 "%lx at %lx\n", regs->trap, regs->nip);
1316 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1317
1318 exception_exit(prev_state);
1319 }
1320
altivec_unavailable_exception(struct pt_regs * regs)1321 void altivec_unavailable_exception(struct pt_regs *regs)
1322 {
1323 enum ctx_state prev_state = exception_enter();
1324
1325 if (user_mode(regs)) {
1326 /* A user program has executed an altivec instruction,
1327 but this kernel doesn't support altivec. */
1328 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1329 goto bail;
1330 }
1331
1332 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1333 "%lx at %lx\n", regs->trap, regs->nip);
1334 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1335
1336 bail:
1337 exception_exit(prev_state);
1338 }
1339
vsx_unavailable_exception(struct pt_regs * regs)1340 void vsx_unavailable_exception(struct pt_regs *regs)
1341 {
1342 if (user_mode(regs)) {
1343 /* A user program has executed an vsx instruction,
1344 but this kernel doesn't support vsx. */
1345 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1346 return;
1347 }
1348
1349 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1350 "%lx at %lx\n", regs->trap, regs->nip);
1351 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1352 }
1353
1354 #ifdef CONFIG_PPC64
tm_unavailable(struct pt_regs * regs)1355 static void tm_unavailable(struct pt_regs *regs)
1356 {
1357 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1358 if (user_mode(regs)) {
1359 current->thread.load_tm++;
1360 regs->msr |= MSR_TM;
1361 tm_enable();
1362 tm_restore_sprs(¤t->thread);
1363 return;
1364 }
1365 #endif
1366 pr_emerg("Unrecoverable TM Unavailable Exception "
1367 "%lx at %lx\n", regs->trap, regs->nip);
1368 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1369 }
1370
facility_unavailable_exception(struct pt_regs * regs)1371 void facility_unavailable_exception(struct pt_regs *regs)
1372 {
1373 static char *facility_strings[] = {
1374 [FSCR_FP_LG] = "FPU",
1375 [FSCR_VECVSX_LG] = "VMX/VSX",
1376 [FSCR_DSCR_LG] = "DSCR",
1377 [FSCR_PM_LG] = "PMU SPRs",
1378 [FSCR_BHRB_LG] = "BHRB",
1379 [FSCR_TM_LG] = "TM",
1380 [FSCR_EBB_LG] = "EBB",
1381 [FSCR_TAR_LG] = "TAR",
1382 [FSCR_MSGP_LG] = "MSGP",
1383 [FSCR_SCV_LG] = "SCV",
1384 };
1385 char *facility = "unknown";
1386 u64 value;
1387 u32 instword, rd;
1388 u8 status;
1389 bool hv;
1390
1391 hv = (regs->trap == 0xf80);
1392 if (hv)
1393 value = mfspr(SPRN_HFSCR);
1394 else
1395 value = mfspr(SPRN_FSCR);
1396
1397 status = value >> 56;
1398 if ((hv || status >= 2) &&
1399 (status < ARRAY_SIZE(facility_strings)) &&
1400 facility_strings[status])
1401 facility = facility_strings[status];
1402
1403 /* We should not have taken this interrupt in kernel */
1404 if (!user_mode(regs)) {
1405 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1406 facility, status, regs->nip);
1407 die("Unexpected facility unavailable exception", regs, SIGABRT);
1408 }
1409
1410 /* We restore the interrupt state now */
1411 if (!arch_irq_disabled_regs(regs))
1412 local_irq_enable();
1413
1414 if (status == FSCR_DSCR_LG) {
1415 /*
1416 * User is accessing the DSCR register using the problem
1417 * state only SPR number (0x03) either through a mfspr or
1418 * a mtspr instruction. If it is a write attempt through
1419 * a mtspr, then we set the inherit bit. This also allows
1420 * the user to write or read the register directly in the
1421 * future by setting via the FSCR DSCR bit. But in case it
1422 * is a read DSCR attempt through a mfspr instruction, we
1423 * just emulate the instruction instead. This code path will
1424 * always emulate all the mfspr instructions till the user
1425 * has attempted at least one mtspr instruction. This way it
1426 * preserves the same behaviour when the user is accessing
1427 * the DSCR through privilege level only SPR number (0x11)
1428 * which is emulated through illegal instruction exception.
1429 * We always leave HFSCR DSCR set.
1430 */
1431 if (get_user(instword, (u32 __user *)(regs->nip))) {
1432 pr_err("Failed to fetch the user instruction\n");
1433 return;
1434 }
1435
1436 /* Write into DSCR (mtspr 0x03, RS) */
1437 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1438 == PPC_INST_MTSPR_DSCR_USER) {
1439 rd = (instword >> 21) & 0x1f;
1440 current->thread.dscr = regs->gpr[rd];
1441 current->thread.dscr_inherit = 1;
1442 current->thread.fscr |= FSCR_DSCR;
1443 mtspr(SPRN_FSCR, current->thread.fscr);
1444 }
1445
1446 /* Read from DSCR (mfspr RT, 0x03) */
1447 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1448 == PPC_INST_MFSPR_DSCR_USER) {
1449 if (emulate_instruction(regs)) {
1450 pr_err("DSCR based mfspr emulation failed\n");
1451 return;
1452 }
1453 regs->nip += 4;
1454 emulate_single_step(regs);
1455 }
1456 return;
1457 }
1458
1459 if (status == FSCR_TM_LG) {
1460 /*
1461 * If we're here then the hardware is TM aware because it
1462 * generated an exception with FSRM_TM set.
1463 *
1464 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1465 * told us not to do TM, or the kernel is not built with TM
1466 * support.
1467 *
1468 * If both of those things are true, then userspace can spam the
1469 * console by triggering the printk() below just by continually
1470 * doing tbegin (or any TM instruction). So in that case just
1471 * send the process a SIGILL immediately.
1472 */
1473 if (!cpu_has_feature(CPU_FTR_TM))
1474 goto out;
1475
1476 tm_unavailable(regs);
1477 return;
1478 }
1479
1480 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1481 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1482
1483 out:
1484 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1485 }
1486 #endif
1487
1488 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1489
fp_unavailable_tm(struct pt_regs * regs)1490 void fp_unavailable_tm(struct pt_regs *regs)
1491 {
1492 /* Note: This does not handle any kind of FP laziness. */
1493
1494 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1495 regs->nip, regs->msr);
1496
1497 /* We can only have got here if the task started using FP after
1498 * beginning the transaction. So, the transactional regs are just a
1499 * copy of the checkpointed ones. But, we still need to recheckpoint
1500 * as we're enabling FP for the process; it will return, abort the
1501 * transaction, and probably retry but now with FP enabled. So the
1502 * checkpointed FP registers need to be loaded.
1503 */
1504 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1505 /* Reclaim didn't save out any FPRs to transact_fprs. */
1506
1507 /* Enable FP for the task: */
1508 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1509
1510 /* This loads and recheckpoints the FP registers from
1511 * thread.fpr[]. They will remain in registers after the
1512 * checkpoint so we don't need to reload them after.
1513 * If VMX is in use, the VRs now hold checkpointed values,
1514 * so we don't want to load the VRs from the thread_struct.
1515 */
1516 tm_recheckpoint(¤t->thread, MSR_FP);
1517
1518 /* If VMX is in use, get the transactional values back */
1519 if (regs->msr & MSR_VEC) {
1520 msr_check_and_set(MSR_VEC);
1521 load_vr_state(¤t->thread.vr_state);
1522 /* At this point all the VSX state is loaded, so enable it */
1523 regs->msr |= MSR_VSX;
1524 }
1525 }
1526
altivec_unavailable_tm(struct pt_regs * regs)1527 void altivec_unavailable_tm(struct pt_regs *regs)
1528 {
1529 /* See the comments in fp_unavailable_tm(). This function operates
1530 * the same way.
1531 */
1532
1533 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1534 "MSR=%lx\n",
1535 regs->nip, regs->msr);
1536 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1537 regs->msr |= MSR_VEC;
1538 tm_recheckpoint(¤t->thread, MSR_VEC);
1539 current->thread.used_vr = 1;
1540
1541 if (regs->msr & MSR_FP) {
1542 msr_check_and_set(MSR_FP);
1543 load_fp_state(¤t->thread.fp_state);
1544 regs->msr |= MSR_VSX;
1545 }
1546 }
1547
vsx_unavailable_tm(struct pt_regs * regs)1548 void vsx_unavailable_tm(struct pt_regs *regs)
1549 {
1550 unsigned long orig_msr = regs->msr;
1551
1552 /* See the comments in fp_unavailable_tm(). This works similarly,
1553 * though we're loading both FP and VEC registers in here.
1554 *
1555 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1556 * regs. Either way, set MSR_VSX.
1557 */
1558
1559 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1560 "MSR=%lx\n",
1561 regs->nip, regs->msr);
1562
1563 current->thread.used_vsr = 1;
1564
1565 /* If FP and VMX are already loaded, we have all the state we need */
1566 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
1567 regs->msr |= MSR_VSX;
1568 return;
1569 }
1570
1571 /* This reclaims FP and/or VR regs if they're already enabled */
1572 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1573
1574 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1575 MSR_VSX;
1576
1577 /* This loads & recheckpoints FP and VRs; but we have
1578 * to be sure not to overwrite previously-valid state.
1579 */
1580 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr);
1581
1582 msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC));
1583
1584 if (orig_msr & MSR_FP)
1585 load_fp_state(¤t->thread.fp_state);
1586 if (orig_msr & MSR_VEC)
1587 load_vr_state(¤t->thread.vr_state);
1588 }
1589 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1590
performance_monitor_exception(struct pt_regs * regs)1591 void performance_monitor_exception(struct pt_regs *regs)
1592 {
1593 __this_cpu_inc(irq_stat.pmu_irqs);
1594
1595 perf_irq(regs);
1596 }
1597
1598 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
handle_debug(struct pt_regs * regs,unsigned long debug_status)1599 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1600 {
1601 int changed = 0;
1602 /*
1603 * Determine the cause of the debug event, clear the
1604 * event flags and send a trap to the handler. Torez
1605 */
1606 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1607 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1608 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1609 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1610 #endif
1611 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1612 5);
1613 changed |= 0x01;
1614 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1615 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1616 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1617 6);
1618 changed |= 0x01;
1619 } else if (debug_status & DBSR_IAC1) {
1620 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1621 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1622 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1623 1);
1624 changed |= 0x01;
1625 } else if (debug_status & DBSR_IAC2) {
1626 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1627 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1628 2);
1629 changed |= 0x01;
1630 } else if (debug_status & DBSR_IAC3) {
1631 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1632 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1633 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1634 3);
1635 changed |= 0x01;
1636 } else if (debug_status & DBSR_IAC4) {
1637 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1638 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1639 4);
1640 changed |= 0x01;
1641 }
1642 /*
1643 * At the point this routine was called, the MSR(DE) was turned off.
1644 * Check all other debug flags and see if that bit needs to be turned
1645 * back on or not.
1646 */
1647 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1648 current->thread.debug.dbcr1))
1649 regs->msr |= MSR_DE;
1650 else
1651 /* Make sure the IDM flag is off */
1652 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1653
1654 if (changed & 0x01)
1655 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1656 }
1657
DebugException(struct pt_regs * regs,unsigned long debug_status)1658 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1659 {
1660 current->thread.debug.dbsr = debug_status;
1661
1662 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1663 * on server, it stops on the target of the branch. In order to simulate
1664 * the server behaviour, we thus restart right away with a single step
1665 * instead of stopping here when hitting a BT
1666 */
1667 if (debug_status & DBSR_BT) {
1668 regs->msr &= ~MSR_DE;
1669
1670 /* Disable BT */
1671 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1672 /* Clear the BT event */
1673 mtspr(SPRN_DBSR, DBSR_BT);
1674
1675 /* Do the single step trick only when coming from userspace */
1676 if (user_mode(regs)) {
1677 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1678 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1679 regs->msr |= MSR_DE;
1680 return;
1681 }
1682
1683 if (kprobe_post_handler(regs))
1684 return;
1685
1686 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1687 5, SIGTRAP) == NOTIFY_STOP) {
1688 return;
1689 }
1690 if (debugger_sstep(regs))
1691 return;
1692 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1693 regs->msr &= ~MSR_DE;
1694
1695 /* Disable instruction completion */
1696 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1697 /* Clear the instruction completion event */
1698 mtspr(SPRN_DBSR, DBSR_IC);
1699
1700 if (kprobe_post_handler(regs))
1701 return;
1702
1703 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1704 5, SIGTRAP) == NOTIFY_STOP) {
1705 return;
1706 }
1707
1708 if (debugger_sstep(regs))
1709 return;
1710
1711 if (user_mode(regs)) {
1712 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1713 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1714 current->thread.debug.dbcr1))
1715 regs->msr |= MSR_DE;
1716 else
1717 /* Make sure the IDM bit is off */
1718 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1719 }
1720
1721 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1722 } else
1723 handle_debug(regs, debug_status);
1724 }
1725 NOKPROBE_SYMBOL(DebugException);
1726 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1727
1728 #if !defined(CONFIG_TAU_INT)
TAUException(struct pt_regs * regs)1729 void TAUException(struct pt_regs *regs)
1730 {
1731 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1732 regs->nip, regs->msr, regs->trap, print_tainted());
1733 }
1734 #endif /* CONFIG_INT_TAU */
1735
1736 #ifdef CONFIG_ALTIVEC
altivec_assist_exception(struct pt_regs * regs)1737 void altivec_assist_exception(struct pt_regs *regs)
1738 {
1739 int err;
1740
1741 if (!user_mode(regs)) {
1742 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1743 " at %lx\n", regs->nip);
1744 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1745 }
1746
1747 flush_altivec_to_thread(current);
1748
1749 PPC_WARN_EMULATED(altivec, regs);
1750 err = emulate_altivec(regs);
1751 if (err == 0) {
1752 regs->nip += 4; /* skip emulated instruction */
1753 emulate_single_step(regs);
1754 return;
1755 }
1756
1757 if (err == -EFAULT) {
1758 /* got an error reading the instruction */
1759 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1760 } else {
1761 /* didn't recognize the instruction */
1762 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1763 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1764 "in %s at %lx\n", current->comm, regs->nip);
1765 current->thread.vr_state.vscr.u[3] |= 0x10000;
1766 }
1767 }
1768 #endif /* CONFIG_ALTIVEC */
1769
1770 #ifdef CONFIG_FSL_BOOKE
CacheLockingException(struct pt_regs * regs,unsigned long address,unsigned long error_code)1771 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1772 unsigned long error_code)
1773 {
1774 /* We treat cache locking instructions from the user
1775 * as priv ops, in the future we could try to do
1776 * something smarter
1777 */
1778 if (error_code & (ESR_DLK|ESR_ILK))
1779 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1780 return;
1781 }
1782 #endif /* CONFIG_FSL_BOOKE */
1783
1784 #ifdef CONFIG_SPE
SPEFloatingPointException(struct pt_regs * regs)1785 void SPEFloatingPointException(struct pt_regs *regs)
1786 {
1787 extern int do_spe_mathemu(struct pt_regs *regs);
1788 unsigned long spefscr;
1789 int fpexc_mode;
1790 int code = 0;
1791 int err;
1792
1793 flush_spe_to_thread(current);
1794
1795 spefscr = current->thread.spefscr;
1796 fpexc_mode = current->thread.fpexc_mode;
1797
1798 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1799 code = FPE_FLTOVF;
1800 }
1801 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1802 code = FPE_FLTUND;
1803 }
1804 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1805 code = FPE_FLTDIV;
1806 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1807 code = FPE_FLTINV;
1808 }
1809 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1810 code = FPE_FLTRES;
1811
1812 err = do_spe_mathemu(regs);
1813 if (err == 0) {
1814 regs->nip += 4; /* skip emulated instruction */
1815 emulate_single_step(regs);
1816 return;
1817 }
1818
1819 if (err == -EFAULT) {
1820 /* got an error reading the instruction */
1821 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1822 } else if (err == -EINVAL) {
1823 /* didn't recognize the instruction */
1824 printk(KERN_ERR "unrecognized spe instruction "
1825 "in %s at %lx\n", current->comm, regs->nip);
1826 } else {
1827 _exception(SIGFPE, regs, code, regs->nip);
1828 }
1829
1830 return;
1831 }
1832
SPEFloatingPointRoundException(struct pt_regs * regs)1833 void SPEFloatingPointRoundException(struct pt_regs *regs)
1834 {
1835 extern int speround_handler(struct pt_regs *regs);
1836 int err;
1837
1838 preempt_disable();
1839 if (regs->msr & MSR_SPE)
1840 giveup_spe(current);
1841 preempt_enable();
1842
1843 regs->nip -= 4;
1844 err = speround_handler(regs);
1845 if (err == 0) {
1846 regs->nip += 4; /* skip emulated instruction */
1847 emulate_single_step(regs);
1848 return;
1849 }
1850
1851 if (err == -EFAULT) {
1852 /* got an error reading the instruction */
1853 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1854 } else if (err == -EINVAL) {
1855 /* didn't recognize the instruction */
1856 printk(KERN_ERR "unrecognized spe instruction "
1857 "in %s at %lx\n", current->comm, regs->nip);
1858 } else {
1859 _exception(SIGFPE, regs, 0, regs->nip);
1860 return;
1861 }
1862 }
1863 #endif
1864
1865 /*
1866 * We enter here if we get an unrecoverable exception, that is, one
1867 * that happened at a point where the RI (recoverable interrupt) bit
1868 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1869 * we therefore lost state by taking this exception.
1870 */
unrecoverable_exception(struct pt_regs * regs)1871 void unrecoverable_exception(struct pt_regs *regs)
1872 {
1873 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1874 regs->trap, regs->nip);
1875 die("Unrecoverable exception", regs, SIGABRT);
1876 }
1877 NOKPROBE_SYMBOL(unrecoverable_exception);
1878
1879 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1880 /*
1881 * Default handler for a Watchdog exception,
1882 * spins until a reboot occurs
1883 */
WatchdogHandler(struct pt_regs * regs)1884 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1885 {
1886 /* Generic WatchdogHandler, implement your own */
1887 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1888 return;
1889 }
1890
WatchdogException(struct pt_regs * regs)1891 void WatchdogException(struct pt_regs *regs)
1892 {
1893 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1894 WatchdogHandler(regs);
1895 }
1896 #endif
1897
1898 /*
1899 * We enter here if we discover during exception entry that we are
1900 * running in supervisor mode with a userspace value in the stack pointer.
1901 */
kernel_bad_stack(struct pt_regs * regs)1902 void kernel_bad_stack(struct pt_regs *regs)
1903 {
1904 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1905 regs->gpr[1], regs->nip);
1906 die("Bad kernel stack pointer", regs, SIGABRT);
1907 }
1908 NOKPROBE_SYMBOL(kernel_bad_stack);
1909
trap_init(void)1910 void __init trap_init(void)
1911 {
1912 }
1913
1914
1915 #ifdef CONFIG_PPC_EMULATED_STATS
1916
1917 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1918
1919 struct ppc_emulated ppc_emulated = {
1920 #ifdef CONFIG_ALTIVEC
1921 WARN_EMULATED_SETUP(altivec),
1922 #endif
1923 WARN_EMULATED_SETUP(dcba),
1924 WARN_EMULATED_SETUP(dcbz),
1925 WARN_EMULATED_SETUP(fp_pair),
1926 WARN_EMULATED_SETUP(isel),
1927 WARN_EMULATED_SETUP(mcrxr),
1928 WARN_EMULATED_SETUP(mfpvr),
1929 WARN_EMULATED_SETUP(multiple),
1930 WARN_EMULATED_SETUP(popcntb),
1931 WARN_EMULATED_SETUP(spe),
1932 WARN_EMULATED_SETUP(string),
1933 WARN_EMULATED_SETUP(sync),
1934 WARN_EMULATED_SETUP(unaligned),
1935 #ifdef CONFIG_MATH_EMULATION
1936 WARN_EMULATED_SETUP(math),
1937 #endif
1938 #ifdef CONFIG_VSX
1939 WARN_EMULATED_SETUP(vsx),
1940 #endif
1941 #ifdef CONFIG_PPC64
1942 WARN_EMULATED_SETUP(mfdscr),
1943 WARN_EMULATED_SETUP(mtdscr),
1944 WARN_EMULATED_SETUP(lq_stq),
1945 #endif
1946 };
1947
1948 u32 ppc_warn_emulated;
1949
ppc_warn_emulated_print(const char * type)1950 void ppc_warn_emulated_print(const char *type)
1951 {
1952 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1953 type);
1954 }
1955
ppc_warn_emulated_init(void)1956 static int __init ppc_warn_emulated_init(void)
1957 {
1958 struct dentry *dir, *d;
1959 unsigned int i;
1960 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1961
1962 if (!powerpc_debugfs_root)
1963 return -ENODEV;
1964
1965 dir = debugfs_create_dir("emulated_instructions",
1966 powerpc_debugfs_root);
1967 if (!dir)
1968 return -ENOMEM;
1969
1970 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1971 &ppc_warn_emulated);
1972 if (!d)
1973 goto fail;
1974
1975 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1976 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1977 (u32 *)&entries[i].val.counter);
1978 if (!d)
1979 goto fail;
1980 }
1981
1982 return 0;
1983
1984 fail:
1985 debugfs_remove_recursive(dir);
1986 return -ENOMEM;
1987 }
1988
1989 device_initcall(ppc_warn_emulated_init);
1990
1991 #endif /* CONFIG_PPC_EMULATED_STATS */
1992