1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completely out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24 #include <linux/bug.h>
25 #include <linux/export.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/smp.h>
29 #include <linux/string.h>
30 #include <linux/cache.h>
31
32 #include <asm/cacheflush.h>
33 #include <asm/cpu-type.h>
34 #include <asm/pgtable.h>
35 #include <asm/war.h>
36 #include <asm/uasm.h>
37 #include <asm/setup.h>
38 #include <asm/tlbex.h>
39
40 static int mips_xpa_disabled;
41
xpa_disable(char * s)42 static int __init xpa_disable(char *s)
43 {
44 mips_xpa_disabled = 1;
45
46 return 1;
47 }
48
49 __setup("noxpa", xpa_disable);
50
51 /*
52 * TLB load/store/modify handlers.
53 *
54 * Only the fastpath gets synthesized at runtime, the slowpath for
55 * do_page_fault remains normal asm.
56 */
57 extern void tlb_do_page_fault_0(void);
58 extern void tlb_do_page_fault_1(void);
59
60 struct work_registers {
61 int r1;
62 int r2;
63 int r3;
64 };
65
66 struct tlb_reg_save {
67 unsigned long a;
68 unsigned long b;
69 } ____cacheline_aligned_in_smp;
70
71 static struct tlb_reg_save handler_reg_save[NR_CPUS];
72
r45k_bvahwbug(void)73 static inline int r45k_bvahwbug(void)
74 {
75 /* XXX: We should probe for the presence of this bug, but we don't. */
76 return 0;
77 }
78
r4k_250MHZhwbug(void)79 static inline int r4k_250MHZhwbug(void)
80 {
81 /* XXX: We should probe for the presence of this bug, but we don't. */
82 return 0;
83 }
84
bcm1250_m3_war(void)85 static inline int __maybe_unused bcm1250_m3_war(void)
86 {
87 return BCM1250_M3_WAR;
88 }
89
r10000_llsc_war(void)90 static inline int __maybe_unused r10000_llsc_war(void)
91 {
92 return R10000_LLSC_WAR;
93 }
94
use_bbit_insns(void)95 static int use_bbit_insns(void)
96 {
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON:
99 case CPU_CAVIUM_OCTEON_PLUS:
100 case CPU_CAVIUM_OCTEON2:
101 case CPU_CAVIUM_OCTEON3:
102 return 1;
103 default:
104 return 0;
105 }
106 }
107
use_lwx_insns(void)108 static int use_lwx_insns(void)
109 {
110 switch (current_cpu_type()) {
111 case CPU_CAVIUM_OCTEON2:
112 case CPU_CAVIUM_OCTEON3:
113 return 1;
114 default:
115 return 0;
116 }
117 }
118 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
119 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
scratchpad_available(void)120 static bool scratchpad_available(void)
121 {
122 return true;
123 }
scratchpad_offset(int i)124 static int scratchpad_offset(int i)
125 {
126 /*
127 * CVMSEG starts at address -32768 and extends for
128 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
129 */
130 i += 1; /* Kernel use starts at the top and works down. */
131 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
132 }
133 #else
scratchpad_available(void)134 static bool scratchpad_available(void)
135 {
136 return false;
137 }
scratchpad_offset(int i)138 static int scratchpad_offset(int i)
139 {
140 BUG();
141 /* Really unreachable, but evidently some GCC want this. */
142 return 0;
143 }
144 #endif
145 /*
146 * Found by experiment: At least some revisions of the 4kc throw under
147 * some circumstances a machine check exception, triggered by invalid
148 * values in the index register. Delaying the tlbp instruction until
149 * after the next branch, plus adding an additional nop in front of
150 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
151 * why; it's not an issue caused by the core RTL.
152 *
153 */
m4kc_tlbp_war(void)154 static int m4kc_tlbp_war(void)
155 {
156 return current_cpu_type() == CPU_4KC;
157 }
158
159 /* Handle labels (which must be positive integers). */
160 enum label_id {
161 label_second_part = 1,
162 label_leave,
163 label_vmalloc,
164 label_vmalloc_done,
165 label_tlbw_hazard_0,
166 label_split = label_tlbw_hazard_0 + 8,
167 label_tlbl_goaround1,
168 label_tlbl_goaround2,
169 label_nopage_tlbl,
170 label_nopage_tlbs,
171 label_nopage_tlbm,
172 label_smp_pgtable_change,
173 label_r3000_write_probe_fail,
174 label_large_segbits_fault,
175 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
176 label_tlb_huge_update,
177 #endif
178 };
179
180 UASM_L_LA(_second_part)
181 UASM_L_LA(_leave)
182 UASM_L_LA(_vmalloc)
183 UASM_L_LA(_vmalloc_done)
184 /* _tlbw_hazard_x is handled differently. */
185 UASM_L_LA(_split)
186 UASM_L_LA(_tlbl_goaround1)
187 UASM_L_LA(_tlbl_goaround2)
188 UASM_L_LA(_nopage_tlbl)
189 UASM_L_LA(_nopage_tlbs)
190 UASM_L_LA(_nopage_tlbm)
191 UASM_L_LA(_smp_pgtable_change)
192 UASM_L_LA(_r3000_write_probe_fail)
193 UASM_L_LA(_large_segbits_fault)
194 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
195 UASM_L_LA(_tlb_huge_update)
196 #endif
197
198 static int hazard_instance;
199
uasm_bgezl_hazard(u32 ** p,struct uasm_reloc ** r,int instance)200 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
201 {
202 switch (instance) {
203 case 0 ... 7:
204 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
205 return;
206 default:
207 BUG();
208 }
209 }
210
uasm_bgezl_label(struct uasm_label ** l,u32 ** p,int instance)211 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
212 {
213 switch (instance) {
214 case 0 ... 7:
215 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
216 break;
217 default:
218 BUG();
219 }
220 }
221
222 /*
223 * pgtable bits are assigned dynamically depending on processor feature
224 * and statically based on kernel configuration. This spits out the actual
225 * values the kernel is using. Required to make sense from disassembled
226 * TLB exception handlers.
227 */
output_pgtable_bits_defines(void)228 static void output_pgtable_bits_defines(void)
229 {
230 #define pr_define(fmt, ...) \
231 pr_debug("#define " fmt, ##__VA_ARGS__)
232
233 pr_debug("#include <asm/asm.h>\n");
234 pr_debug("#include <asm/regdef.h>\n");
235 pr_debug("\n");
236
237 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
238 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
239 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
240 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
241 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
242 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
243 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
244 #endif
245 #ifdef _PAGE_NO_EXEC_SHIFT
246 if (cpu_has_rixi)
247 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
248 #endif
249 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
250 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
251 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
252 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
253 pr_debug("\n");
254 }
255
dump_handler(const char * symbol,const u32 * handler,int count)256 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
257 {
258 int i;
259
260 pr_debug("LEAF(%s)\n", symbol);
261
262 pr_debug("\t.set push\n");
263 pr_debug("\t.set noreorder\n");
264
265 for (i = 0; i < count; i++)
266 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
267
268 pr_debug("\t.set\tpop\n");
269
270 pr_debug("\tEND(%s)\n", symbol);
271 }
272
273 /* The only general purpose registers allowed in TLB handlers. */
274 #define K0 26
275 #define K1 27
276
277 /* Some CP0 registers */
278 #define C0_INDEX 0, 0
279 #define C0_ENTRYLO0 2, 0
280 #define C0_TCBIND 2, 2
281 #define C0_ENTRYLO1 3, 0
282 #define C0_CONTEXT 4, 0
283 #define C0_PAGEMASK 5, 0
284 #define C0_PWBASE 5, 5
285 #define C0_PWFIELD 5, 6
286 #define C0_PWSIZE 5, 7
287 #define C0_PWCTL 6, 6
288 #define C0_BADVADDR 8, 0
289 #define C0_PGD 9, 7
290 #define C0_ENTRYHI 10, 0
291 #define C0_EPC 14, 0
292 #define C0_XCONTEXT 20, 0
293
294 #ifdef CONFIG_64BIT
295 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
296 #else
297 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
298 #endif
299
300 /* The worst case length of the handler is around 18 instructions for
301 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
302 * Maximum space available is 32 instructions for R3000 and 64
303 * instructions for R4000.
304 *
305 * We deliberately chose a buffer size of 128, so we won't scribble
306 * over anything important on overflow before we panic.
307 */
308 static u32 tlb_handler[128];
309
310 /* simply assume worst case size for labels and relocs */
311 static struct uasm_label labels[128];
312 static struct uasm_reloc relocs[128];
313
314 static int check_for_high_segbits;
315 static bool fill_includes_sw_bits;
316
317 static unsigned int kscratch_used_mask;
318
c0_kscratch(void)319 static inline int __maybe_unused c0_kscratch(void)
320 {
321 switch (current_cpu_type()) {
322 case CPU_XLP:
323 case CPU_XLR:
324 return 22;
325 default:
326 return 31;
327 }
328 }
329
allocate_kscratch(void)330 static int allocate_kscratch(void)
331 {
332 int r;
333 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
334
335 r = ffs(a);
336
337 if (r == 0)
338 return -1;
339
340 r--; /* make it zero based */
341
342 kscratch_used_mask |= (1 << r);
343
344 return r;
345 }
346
347 static int scratch_reg;
348 int pgd_reg;
349 EXPORT_SYMBOL_GPL(pgd_reg);
350 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
351
build_get_work_registers(u32 ** p)352 static struct work_registers build_get_work_registers(u32 **p)
353 {
354 struct work_registers r;
355
356 if (scratch_reg >= 0) {
357 /* Save in CPU local C0_KScratch? */
358 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
359 r.r1 = K0;
360 r.r2 = K1;
361 r.r3 = 1;
362 return r;
363 }
364
365 if (num_possible_cpus() > 1) {
366 /* Get smp_processor_id */
367 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
368 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
369
370 /* handler_reg_save index in K0 */
371 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
372
373 UASM_i_LA(p, K1, (long)&handler_reg_save);
374 UASM_i_ADDU(p, K0, K0, K1);
375 } else {
376 UASM_i_LA(p, K0, (long)&handler_reg_save);
377 }
378 /* K0 now points to save area, save $1 and $2 */
379 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
380 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
381
382 r.r1 = K1;
383 r.r2 = 1;
384 r.r3 = 2;
385 return r;
386 }
387
build_restore_work_registers(u32 ** p)388 static void build_restore_work_registers(u32 **p)
389 {
390 if (scratch_reg >= 0) {
391 uasm_i_ehb(p);
392 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
393 return;
394 }
395 /* K0 already points to save area, restore $1 and $2 */
396 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
397 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
398 }
399
400 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
401
402 /*
403 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
404 * we cannot do r3000 under these circumstances.
405 *
406 * Declare pgd_current here instead of including mmu_context.h to avoid type
407 * conflicts for tlbmiss_handler_setup_pgd
408 */
409 extern unsigned long pgd_current[];
410
411 /*
412 * The R3000 TLB handler is simple.
413 */
build_r3000_tlb_refill_handler(void)414 static void build_r3000_tlb_refill_handler(void)
415 {
416 long pgdc = (long)pgd_current;
417 u32 *p;
418
419 memset(tlb_handler, 0, sizeof(tlb_handler));
420 p = tlb_handler;
421
422 uasm_i_mfc0(&p, K0, C0_BADVADDR);
423 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
424 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
425 uasm_i_srl(&p, K0, K0, 22); /* load delay */
426 uasm_i_sll(&p, K0, K0, 2);
427 uasm_i_addu(&p, K1, K1, K0);
428 uasm_i_mfc0(&p, K0, C0_CONTEXT);
429 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
430 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
431 uasm_i_addu(&p, K1, K1, K0);
432 uasm_i_lw(&p, K0, 0, K1);
433 uasm_i_nop(&p); /* load delay */
434 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
435 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
436 uasm_i_tlbwr(&p); /* cp0 delay */
437 uasm_i_jr(&p, K1);
438 uasm_i_rfe(&p); /* branch delay */
439
440 if (p > tlb_handler + 32)
441 panic("TLB refill handler space exceeded");
442
443 pr_debug("Wrote TLB refill handler (%u instructions).\n",
444 (unsigned int)(p - tlb_handler));
445
446 memcpy((void *)ebase, tlb_handler, 0x80);
447 local_flush_icache_range(ebase, ebase + 0x80);
448
449 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
450 }
451 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
452
453 /*
454 * The R4000 TLB handler is much more complicated. We have two
455 * consecutive handler areas with 32 instructions space each.
456 * Since they aren't used at the same time, we can overflow in the
457 * other one.To keep things simple, we first assume linear space,
458 * then we relocate it to the final handler layout as needed.
459 */
460 static u32 final_handler[64];
461
462 /*
463 * Hazards
464 *
465 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
466 * 2. A timing hazard exists for the TLBP instruction.
467 *
468 * stalling_instruction
469 * TLBP
470 *
471 * The JTLB is being read for the TLBP throughout the stall generated by the
472 * previous instruction. This is not really correct as the stalling instruction
473 * can modify the address used to access the JTLB. The failure symptom is that
474 * the TLBP instruction will use an address created for the stalling instruction
475 * and not the address held in C0_ENHI and thus report the wrong results.
476 *
477 * The software work-around is to not allow the instruction preceding the TLBP
478 * to stall - make it an NOP or some other instruction guaranteed not to stall.
479 *
480 * Errata 2 will not be fixed. This errata is also on the R5000.
481 *
482 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
483 */
build_tlb_probe_entry(u32 ** p)484 static void __maybe_unused build_tlb_probe_entry(u32 **p)
485 {
486 switch (current_cpu_type()) {
487 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
488 case CPU_R4600:
489 case CPU_R4700:
490 case CPU_R5000:
491 case CPU_NEVADA:
492 uasm_i_nop(p);
493 uasm_i_tlbp(p);
494 break;
495
496 default:
497 uasm_i_tlbp(p);
498 break;
499 }
500 }
501
build_tlb_write_entry(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,enum tlb_write_entry wmode)502 void build_tlb_write_entry(u32 **p, struct uasm_label **l,
503 struct uasm_reloc **r,
504 enum tlb_write_entry wmode)
505 {
506 void(*tlbw)(u32 **) = NULL;
507
508 switch (wmode) {
509 case tlb_random: tlbw = uasm_i_tlbwr; break;
510 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
511 }
512
513 if (cpu_has_mips_r2_r6) {
514 if (cpu_has_mips_r2_exec_hazard)
515 uasm_i_ehb(p);
516 tlbw(p);
517 return;
518 }
519
520 switch (current_cpu_type()) {
521 case CPU_R4000PC:
522 case CPU_R4000SC:
523 case CPU_R4000MC:
524 case CPU_R4400PC:
525 case CPU_R4400SC:
526 case CPU_R4400MC:
527 /*
528 * This branch uses up a mtc0 hazard nop slot and saves
529 * two nops after the tlbw instruction.
530 */
531 uasm_bgezl_hazard(p, r, hazard_instance);
532 tlbw(p);
533 uasm_bgezl_label(l, p, hazard_instance);
534 hazard_instance++;
535 uasm_i_nop(p);
536 break;
537
538 case CPU_R4600:
539 case CPU_R4700:
540 uasm_i_nop(p);
541 tlbw(p);
542 uasm_i_nop(p);
543 break;
544
545 case CPU_R5000:
546 case CPU_NEVADA:
547 uasm_i_nop(p); /* QED specifies 2 nops hazard */
548 uasm_i_nop(p); /* QED specifies 2 nops hazard */
549 tlbw(p);
550 break;
551
552 case CPU_R4300:
553 case CPU_5KC:
554 case CPU_TX49XX:
555 case CPU_PR4450:
556 case CPU_XLR:
557 uasm_i_nop(p);
558 tlbw(p);
559 break;
560
561 case CPU_R10000:
562 case CPU_R12000:
563 case CPU_R14000:
564 case CPU_R16000:
565 case CPU_4KC:
566 case CPU_4KEC:
567 case CPU_M14KC:
568 case CPU_M14KEC:
569 case CPU_SB1:
570 case CPU_SB1A:
571 case CPU_4KSC:
572 case CPU_20KC:
573 case CPU_25KF:
574 case CPU_BMIPS32:
575 case CPU_BMIPS3300:
576 case CPU_BMIPS4350:
577 case CPU_BMIPS4380:
578 case CPU_BMIPS5000:
579 case CPU_LOONGSON2:
580 case CPU_LOONGSON3:
581 case CPU_R5500:
582 if (m4kc_tlbp_war())
583 uasm_i_nop(p);
584 case CPU_ALCHEMY:
585 tlbw(p);
586 break;
587
588 case CPU_RM7000:
589 uasm_i_nop(p);
590 uasm_i_nop(p);
591 uasm_i_nop(p);
592 uasm_i_nop(p);
593 tlbw(p);
594 break;
595
596 case CPU_VR4111:
597 case CPU_VR4121:
598 case CPU_VR4122:
599 case CPU_VR4181:
600 case CPU_VR4181A:
601 uasm_i_nop(p);
602 uasm_i_nop(p);
603 tlbw(p);
604 uasm_i_nop(p);
605 uasm_i_nop(p);
606 break;
607
608 case CPU_VR4131:
609 case CPU_VR4133:
610 case CPU_R5432:
611 uasm_i_nop(p);
612 uasm_i_nop(p);
613 tlbw(p);
614 break;
615
616 case CPU_JZRISC:
617 tlbw(p);
618 uasm_i_nop(p);
619 break;
620
621 default:
622 panic("No TLB refill handler yet (CPU type: %d)",
623 current_cpu_type());
624 break;
625 }
626 }
627 EXPORT_SYMBOL_GPL(build_tlb_write_entry);
628
build_convert_pte_to_entrylo(u32 ** p,unsigned int reg)629 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
630 unsigned int reg)
631 {
632 if (_PAGE_GLOBAL_SHIFT == 0) {
633 /* pte_t is already in EntryLo format */
634 return;
635 }
636
637 if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
638 if (fill_includes_sw_bits) {
639 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
640 } else {
641 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
642 UASM_i_ROTR(p, reg, reg,
643 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
644 }
645 } else {
646 #ifdef CONFIG_PHYS_ADDR_T_64BIT
647 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
648 #else
649 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
650 #endif
651 }
652 }
653
654 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
655
build_restore_pagemask(u32 ** p,struct uasm_reloc ** r,unsigned int tmp,enum label_id lid,int restore_scratch)656 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
657 unsigned int tmp, enum label_id lid,
658 int restore_scratch)
659 {
660 if (restore_scratch) {
661 /*
662 * Ensure the MFC0 below observes the value written to the
663 * KScratch register by the prior MTC0.
664 */
665 if (scratch_reg >= 0)
666 uasm_i_ehb(p);
667
668 /* Reset default page size */
669 if (PM_DEFAULT_MASK >> 16) {
670 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
671 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
672 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
673 uasm_il_b(p, r, lid);
674 } else if (PM_DEFAULT_MASK) {
675 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
676 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
677 uasm_il_b(p, r, lid);
678 } else {
679 uasm_i_mtc0(p, 0, C0_PAGEMASK);
680 uasm_il_b(p, r, lid);
681 }
682 if (scratch_reg >= 0)
683 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
684 else
685 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
686 } else {
687 /* Reset default page size */
688 if (PM_DEFAULT_MASK >> 16) {
689 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
690 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
691 uasm_il_b(p, r, lid);
692 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
693 } else if (PM_DEFAULT_MASK) {
694 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
695 uasm_il_b(p, r, lid);
696 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
697 } else {
698 uasm_il_b(p, r, lid);
699 uasm_i_mtc0(p, 0, C0_PAGEMASK);
700 }
701 }
702 }
703
build_huge_tlb_write_entry(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,enum tlb_write_entry wmode,int restore_scratch)704 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
705 struct uasm_reloc **r,
706 unsigned int tmp,
707 enum tlb_write_entry wmode,
708 int restore_scratch)
709 {
710 /* Set huge page tlb entry size */
711 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
712 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
713 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
714
715 build_tlb_write_entry(p, l, r, wmode);
716
717 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
718 }
719
720 /*
721 * Check if Huge PTE is present, if so then jump to LABEL.
722 */
723 static void
build_is_huge_pte(u32 ** p,struct uasm_reloc ** r,unsigned int tmp,unsigned int pmd,int lid)724 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
725 unsigned int pmd, int lid)
726 {
727 UASM_i_LW(p, tmp, 0, pmd);
728 if (use_bbit_insns()) {
729 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
730 } else {
731 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
732 uasm_il_bnez(p, r, tmp, lid);
733 }
734 }
735
build_huge_update_entries(u32 ** p,unsigned int pte,unsigned int tmp)736 static void build_huge_update_entries(u32 **p, unsigned int pte,
737 unsigned int tmp)
738 {
739 int small_sequence;
740
741 /*
742 * A huge PTE describes an area the size of the
743 * configured huge page size. This is twice the
744 * of the large TLB entry size we intend to use.
745 * A TLB entry half the size of the configured
746 * huge page size is configured into entrylo0
747 * and entrylo1 to cover the contiguous huge PTE
748 * address space.
749 */
750 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
751
752 /* We can clobber tmp. It isn't used after this.*/
753 if (!small_sequence)
754 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
755
756 build_convert_pte_to_entrylo(p, pte);
757 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
758 /* convert to entrylo1 */
759 if (small_sequence)
760 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
761 else
762 UASM_i_ADDU(p, pte, pte, tmp);
763
764 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
765 }
766
build_huge_handler_tail(u32 ** p,struct uasm_reloc ** r,struct uasm_label ** l,unsigned int pte,unsigned int ptr,unsigned int flush)767 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
768 struct uasm_label **l,
769 unsigned int pte,
770 unsigned int ptr,
771 unsigned int flush)
772 {
773 #ifdef CONFIG_SMP
774 UASM_i_SC(p, pte, 0, ptr);
775 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
776 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
777 #else
778 UASM_i_SW(p, pte, 0, ptr);
779 #endif
780 if (cpu_has_ftlb && flush) {
781 BUG_ON(!cpu_has_tlbinv);
782
783 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
784 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
785 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
786 build_tlb_write_entry(p, l, r, tlb_indexed);
787
788 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
789 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
790 build_huge_update_entries(p, pte, ptr);
791 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
792
793 return;
794 }
795
796 build_huge_update_entries(p, pte, ptr);
797 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
798 }
799 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
800
801 #ifdef CONFIG_64BIT
802 /*
803 * TMP and PTR are scratch.
804 * TMP will be clobbered, PTR will hold the pmd entry.
805 */
build_get_pmde64(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,unsigned int ptr)806 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
807 unsigned int tmp, unsigned int ptr)
808 {
809 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
810 long pgdc = (long)pgd_current;
811 #endif
812 /*
813 * The vmalloc handling is not in the hotpath.
814 */
815 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
816
817 if (check_for_high_segbits) {
818 /*
819 * The kernel currently implicitely assumes that the
820 * MIPS SEGBITS parameter for the processor is
821 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
822 * allocate virtual addresses outside the maximum
823 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
824 * that doesn't prevent user code from accessing the
825 * higher xuseg addresses. Here, we make sure that
826 * everything but the lower xuseg addresses goes down
827 * the module_alloc/vmalloc path.
828 */
829 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
830 uasm_il_bnez(p, r, ptr, label_vmalloc);
831 } else {
832 uasm_il_bltz(p, r, tmp, label_vmalloc);
833 }
834 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
835
836 if (pgd_reg != -1) {
837 /* pgd is in pgd_reg */
838 if (cpu_has_ldpte)
839 UASM_i_MFC0(p, ptr, C0_PWBASE);
840 else
841 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
842 } else {
843 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
844 /*
845 * &pgd << 11 stored in CONTEXT [23..63].
846 */
847 UASM_i_MFC0(p, ptr, C0_CONTEXT);
848
849 /* Clear lower 23 bits of context. */
850 uasm_i_dins(p, ptr, 0, 0, 23);
851
852 /* 1 0 1 0 1 << 6 xkphys cached */
853 uasm_i_ori(p, ptr, ptr, 0x540);
854 uasm_i_drotr(p, ptr, ptr, 11);
855 #elif defined(CONFIG_SMP)
856 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
857 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
858 UASM_i_LA_mostly(p, tmp, pgdc);
859 uasm_i_daddu(p, ptr, ptr, tmp);
860 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
861 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
862 #else
863 UASM_i_LA_mostly(p, ptr, pgdc);
864 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
865 #endif
866 }
867
868 uasm_l_vmalloc_done(l, *p);
869
870 /* get pgd offset in bytes */
871 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
872
873 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
874 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
875 #ifndef __PAGETABLE_PUD_FOLDED
876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
877 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
878 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
879 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
880 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
881 #endif
882 #ifndef __PAGETABLE_PMD_FOLDED
883 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
884 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
885 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
886 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
887 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
888 #endif
889 }
890 EXPORT_SYMBOL_GPL(build_get_pmde64);
891
892 /*
893 * BVADDR is the faulting address, PTR is scratch.
894 * PTR will hold the pgd for vmalloc.
895 */
896 static void
build_get_pgd_vmalloc64(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int bvaddr,unsigned int ptr,enum vmalloc64_mode mode)897 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
898 unsigned int bvaddr, unsigned int ptr,
899 enum vmalloc64_mode mode)
900 {
901 long swpd = (long)swapper_pg_dir;
902 int single_insn_swpd;
903 int did_vmalloc_branch = 0;
904
905 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
906
907 uasm_l_vmalloc(l, *p);
908
909 if (mode != not_refill && check_for_high_segbits) {
910 if (single_insn_swpd) {
911 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
912 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
913 did_vmalloc_branch = 1;
914 /* fall through */
915 } else {
916 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
917 }
918 }
919 if (!did_vmalloc_branch) {
920 if (single_insn_swpd) {
921 uasm_il_b(p, r, label_vmalloc_done);
922 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
923 } else {
924 UASM_i_LA_mostly(p, ptr, swpd);
925 uasm_il_b(p, r, label_vmalloc_done);
926 if (uasm_in_compat_space_p(swpd))
927 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
928 else
929 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
930 }
931 }
932 if (mode != not_refill && check_for_high_segbits) {
933 uasm_l_large_segbits_fault(l, *p);
934
935 if (mode == refill_scratch && scratch_reg >= 0)
936 uasm_i_ehb(p);
937
938 /*
939 * We get here if we are an xsseg address, or if we are
940 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
941 *
942 * Ignoring xsseg (assume disabled so would generate
943 * (address errors?), the only remaining possibility
944 * is the upper xuseg addresses. On processors with
945 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
946 * addresses would have taken an address error. We try
947 * to mimic that here by taking a load/istream page
948 * fault.
949 */
950 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
951 uasm_i_jr(p, ptr);
952
953 if (mode == refill_scratch) {
954 if (scratch_reg >= 0)
955 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
956 else
957 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
958 } else {
959 uasm_i_nop(p);
960 }
961 }
962 }
963
964 #else /* !CONFIG_64BIT */
965
966 /*
967 * TMP and PTR are scratch.
968 * TMP will be clobbered, PTR will hold the pgd entry.
969 */
build_get_pgde32(u32 ** p,unsigned int tmp,unsigned int ptr)970 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
971 {
972 if (pgd_reg != -1) {
973 /* pgd is in pgd_reg */
974 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
975 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
976 } else {
977 long pgdc = (long)pgd_current;
978
979 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
980 #ifdef CONFIG_SMP
981 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
982 UASM_i_LA_mostly(p, tmp, pgdc);
983 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
984 uasm_i_addu(p, ptr, tmp, ptr);
985 #else
986 UASM_i_LA_mostly(p, ptr, pgdc);
987 #endif
988 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
989 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
990 }
991 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
992 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
993 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
994 }
995 EXPORT_SYMBOL_GPL(build_get_pgde32);
996
997 #endif /* !CONFIG_64BIT */
998
build_adjust_context(u32 ** p,unsigned int ctx)999 static void build_adjust_context(u32 **p, unsigned int ctx)
1000 {
1001 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1002 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1003
1004 switch (current_cpu_type()) {
1005 case CPU_VR41XX:
1006 case CPU_VR4111:
1007 case CPU_VR4121:
1008 case CPU_VR4122:
1009 case CPU_VR4131:
1010 case CPU_VR4181:
1011 case CPU_VR4181A:
1012 case CPU_VR4133:
1013 shift += 2;
1014 break;
1015
1016 default:
1017 break;
1018 }
1019
1020 if (shift)
1021 UASM_i_SRL(p, ctx, ctx, shift);
1022 uasm_i_andi(p, ctx, ctx, mask);
1023 }
1024
build_get_ptep(u32 ** p,unsigned int tmp,unsigned int ptr)1025 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1026 {
1027 /*
1028 * Bug workaround for the Nevada. It seems as if under certain
1029 * circumstances the move from cp0_context might produce a
1030 * bogus result when the mfc0 instruction and its consumer are
1031 * in a different cacheline or a load instruction, probably any
1032 * memory reference, is between them.
1033 */
1034 switch (current_cpu_type()) {
1035 case CPU_NEVADA:
1036 UASM_i_LW(p, ptr, 0, ptr);
1037 GET_CONTEXT(p, tmp); /* get context reg */
1038 break;
1039
1040 default:
1041 GET_CONTEXT(p, tmp); /* get context reg */
1042 UASM_i_LW(p, ptr, 0, ptr);
1043 break;
1044 }
1045
1046 build_adjust_context(p, tmp);
1047 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1048 }
1049 EXPORT_SYMBOL_GPL(build_get_ptep);
1050
build_update_entries(u32 ** p,unsigned int tmp,unsigned int ptep)1051 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1052 {
1053 int pte_off_even = 0;
1054 int pte_off_odd = sizeof(pte_t);
1055
1056 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1057 /* The low 32 bits of EntryLo is stored in pte_high */
1058 pte_off_even += offsetof(pte_t, pte_high);
1059 pte_off_odd += offsetof(pte_t, pte_high);
1060 #endif
1061
1062 if (IS_ENABLED(CONFIG_XPA)) {
1063 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1064 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1065 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1066
1067 if (cpu_has_xpa && !mips_xpa_disabled) {
1068 uasm_i_lw(p, tmp, 0, ptep);
1069 uasm_i_ext(p, tmp, tmp, 0, 24);
1070 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1071 }
1072
1073 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1074 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1075 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1076
1077 if (cpu_has_xpa && !mips_xpa_disabled) {
1078 uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1079 uasm_i_ext(p, tmp, tmp, 0, 24);
1080 uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1081 }
1082 return;
1083 }
1084
1085 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1086 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1087 if (r45k_bvahwbug())
1088 build_tlb_probe_entry(p);
1089 build_convert_pte_to_entrylo(p, tmp);
1090 if (r4k_250MHZhwbug())
1091 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1092 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1093 build_convert_pte_to_entrylo(p, ptep);
1094 if (r45k_bvahwbug())
1095 uasm_i_mfc0(p, tmp, C0_INDEX);
1096 if (r4k_250MHZhwbug())
1097 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1098 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1099 }
1100 EXPORT_SYMBOL_GPL(build_update_entries);
1101
1102 struct mips_huge_tlb_info {
1103 int huge_pte;
1104 int restore_scratch;
1105 bool need_reload_pte;
1106 };
1107
1108 static struct mips_huge_tlb_info
build_fast_tlb_refill_handler(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,unsigned int ptr,int c0_scratch_reg)1109 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1110 struct uasm_reloc **r, unsigned int tmp,
1111 unsigned int ptr, int c0_scratch_reg)
1112 {
1113 struct mips_huge_tlb_info rv;
1114 unsigned int even, odd;
1115 int vmalloc_branch_delay_filled = 0;
1116 const int scratch = 1; /* Our extra working register */
1117
1118 rv.huge_pte = scratch;
1119 rv.restore_scratch = 0;
1120 rv.need_reload_pte = false;
1121
1122 if (check_for_high_segbits) {
1123 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1124
1125 if (pgd_reg != -1)
1126 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1127 else
1128 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1129
1130 if (c0_scratch_reg >= 0)
1131 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1132 else
1133 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1134
1135 uasm_i_dsrl_safe(p, scratch, tmp,
1136 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1137 uasm_il_bnez(p, r, scratch, label_vmalloc);
1138
1139 if (pgd_reg == -1) {
1140 vmalloc_branch_delay_filled = 1;
1141 /* Clear lower 23 bits of context. */
1142 uasm_i_dins(p, ptr, 0, 0, 23);
1143 }
1144 } else {
1145 if (pgd_reg != -1)
1146 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1147 else
1148 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1149
1150 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1151
1152 if (c0_scratch_reg >= 0)
1153 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1154 else
1155 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1156
1157 if (pgd_reg == -1)
1158 /* Clear lower 23 bits of context. */
1159 uasm_i_dins(p, ptr, 0, 0, 23);
1160
1161 uasm_il_bltz(p, r, tmp, label_vmalloc);
1162 }
1163
1164 if (pgd_reg == -1) {
1165 vmalloc_branch_delay_filled = 1;
1166 /* 1 0 1 0 1 << 6 xkphys cached */
1167 uasm_i_ori(p, ptr, ptr, 0x540);
1168 uasm_i_drotr(p, ptr, ptr, 11);
1169 }
1170
1171 #ifdef __PAGETABLE_PMD_FOLDED
1172 #define LOC_PTEP scratch
1173 #else
1174 #define LOC_PTEP ptr
1175 #endif
1176
1177 if (!vmalloc_branch_delay_filled)
1178 /* get pgd offset in bytes */
1179 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1180
1181 uasm_l_vmalloc_done(l, *p);
1182
1183 /*
1184 * tmp ptr
1185 * fall-through case = badvaddr *pgd_current
1186 * vmalloc case = badvaddr swapper_pg_dir
1187 */
1188
1189 if (vmalloc_branch_delay_filled)
1190 /* get pgd offset in bytes */
1191 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1192
1193 #ifdef __PAGETABLE_PMD_FOLDED
1194 GET_CONTEXT(p, tmp); /* get context reg */
1195 #endif
1196 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1197
1198 if (use_lwx_insns()) {
1199 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1200 } else {
1201 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1202 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1203 }
1204
1205 #ifndef __PAGETABLE_PUD_FOLDED
1206 /* get pud offset in bytes */
1207 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
1208 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
1209
1210 if (use_lwx_insns()) {
1211 UASM_i_LWX(p, ptr, scratch, ptr);
1212 } else {
1213 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1214 UASM_i_LW(p, ptr, 0, ptr);
1215 }
1216 /* ptr contains a pointer to PMD entry */
1217 /* tmp contains the address */
1218 #endif
1219
1220 #ifndef __PAGETABLE_PMD_FOLDED
1221 /* get pmd offset in bytes */
1222 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1223 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1224 GET_CONTEXT(p, tmp); /* get context reg */
1225
1226 if (use_lwx_insns()) {
1227 UASM_i_LWX(p, scratch, scratch, ptr);
1228 } else {
1229 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1230 UASM_i_LW(p, scratch, 0, ptr);
1231 }
1232 #endif
1233 /* Adjust the context during the load latency. */
1234 build_adjust_context(p, tmp);
1235
1236 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1237 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1238 /*
1239 * The in the LWX case we don't want to do the load in the
1240 * delay slot. It cannot issue in the same cycle and may be
1241 * speculative and unneeded.
1242 */
1243 if (use_lwx_insns())
1244 uasm_i_nop(p);
1245 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1246
1247
1248 /* build_update_entries */
1249 if (use_lwx_insns()) {
1250 even = ptr;
1251 odd = tmp;
1252 UASM_i_LWX(p, even, scratch, tmp);
1253 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1254 UASM_i_LWX(p, odd, scratch, tmp);
1255 } else {
1256 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1257 even = tmp;
1258 odd = ptr;
1259 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1260 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1261 }
1262 if (cpu_has_rixi) {
1263 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1264 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1265 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1266 } else {
1267 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1268 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1269 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1270 }
1271 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1272
1273 if (c0_scratch_reg >= 0) {
1274 uasm_i_ehb(p);
1275 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1276 build_tlb_write_entry(p, l, r, tlb_random);
1277 uasm_l_leave(l, *p);
1278 rv.restore_scratch = 1;
1279 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1280 build_tlb_write_entry(p, l, r, tlb_random);
1281 uasm_l_leave(l, *p);
1282 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1283 } else {
1284 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1285 build_tlb_write_entry(p, l, r, tlb_random);
1286 uasm_l_leave(l, *p);
1287 rv.restore_scratch = 1;
1288 }
1289
1290 uasm_i_eret(p); /* return from trap */
1291
1292 return rv;
1293 }
1294
1295 /*
1296 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1297 * because EXL == 0. If we wrap, we can also use the 32 instruction
1298 * slots before the XTLB refill exception handler which belong to the
1299 * unused TLB refill exception.
1300 */
1301 #define MIPS64_REFILL_INSNS 32
1302
build_r4000_tlb_refill_handler(void)1303 static void build_r4000_tlb_refill_handler(void)
1304 {
1305 u32 *p = tlb_handler;
1306 struct uasm_label *l = labels;
1307 struct uasm_reloc *r = relocs;
1308 u32 *f;
1309 unsigned int final_len;
1310 struct mips_huge_tlb_info htlb_info __maybe_unused;
1311 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1312
1313 memset(tlb_handler, 0, sizeof(tlb_handler));
1314 memset(labels, 0, sizeof(labels));
1315 memset(relocs, 0, sizeof(relocs));
1316 memset(final_handler, 0, sizeof(final_handler));
1317
1318 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1319 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1320 scratch_reg);
1321 vmalloc_mode = refill_scratch;
1322 } else {
1323 htlb_info.huge_pte = K0;
1324 htlb_info.restore_scratch = 0;
1325 htlb_info.need_reload_pte = true;
1326 vmalloc_mode = refill_noscratch;
1327 /*
1328 * create the plain linear handler
1329 */
1330 if (bcm1250_m3_war()) {
1331 unsigned int segbits = 44;
1332
1333 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1334 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1335 uasm_i_xor(&p, K0, K0, K1);
1336 uasm_i_dsrl_safe(&p, K1, K0, 62);
1337 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1338 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1339 uasm_i_or(&p, K0, K0, K1);
1340 uasm_il_bnez(&p, &r, K0, label_leave);
1341 /* No need for uasm_i_nop */
1342 }
1343
1344 #ifdef CONFIG_64BIT
1345 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1346 #else
1347 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1348 #endif
1349
1350 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1351 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1352 #endif
1353
1354 build_get_ptep(&p, K0, K1);
1355 build_update_entries(&p, K0, K1);
1356 build_tlb_write_entry(&p, &l, &r, tlb_random);
1357 uasm_l_leave(&l, p);
1358 uasm_i_eret(&p); /* return from trap */
1359 }
1360 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1361 uasm_l_tlb_huge_update(&l, p);
1362 if (htlb_info.need_reload_pte)
1363 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1364 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1365 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1366 htlb_info.restore_scratch);
1367 #endif
1368
1369 #ifdef CONFIG_64BIT
1370 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1371 #endif
1372
1373 /*
1374 * Overflow check: For the 64bit handler, we need at least one
1375 * free instruction slot for the wrap-around branch. In worst
1376 * case, if the intended insertion point is a delay slot, we
1377 * need three, with the second nop'ed and the third being
1378 * unused.
1379 */
1380 switch (boot_cpu_type()) {
1381 default:
1382 if (sizeof(long) == 4) {
1383 case CPU_LOONGSON2:
1384 /* Loongson2 ebase is different than r4k, we have more space */
1385 if ((p - tlb_handler) > 64)
1386 panic("TLB refill handler space exceeded");
1387 /*
1388 * Now fold the handler in the TLB refill handler space.
1389 */
1390 f = final_handler;
1391 /* Simplest case, just copy the handler. */
1392 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1393 final_len = p - tlb_handler;
1394 break;
1395 } else {
1396 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1397 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1398 && uasm_insn_has_bdelay(relocs,
1399 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1400 panic("TLB refill handler space exceeded");
1401 /*
1402 * Now fold the handler in the TLB refill handler space.
1403 */
1404 f = final_handler + MIPS64_REFILL_INSNS;
1405 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1406 /* Just copy the handler. */
1407 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1408 final_len = p - tlb_handler;
1409 } else {
1410 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1411 const enum label_id ls = label_tlb_huge_update;
1412 #else
1413 const enum label_id ls = label_vmalloc;
1414 #endif
1415 u32 *split;
1416 int ov = 0;
1417 int i;
1418
1419 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1420 ;
1421 BUG_ON(i == ARRAY_SIZE(labels));
1422 split = labels[i].addr;
1423
1424 /*
1425 * See if we have overflown one way or the other.
1426 */
1427 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1428 split < p - MIPS64_REFILL_INSNS)
1429 ov = 1;
1430
1431 if (ov) {
1432 /*
1433 * Split two instructions before the end. One
1434 * for the branch and one for the instruction
1435 * in the delay slot.
1436 */
1437 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1438
1439 /*
1440 * If the branch would fall in a delay slot,
1441 * we must back up an additional instruction
1442 * so that it is no longer in a delay slot.
1443 */
1444 if (uasm_insn_has_bdelay(relocs, split - 1))
1445 split--;
1446 }
1447 /* Copy first part of the handler. */
1448 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1449 f += split - tlb_handler;
1450
1451 if (ov) {
1452 /* Insert branch. */
1453 uasm_l_split(&l, final_handler);
1454 uasm_il_b(&f, &r, label_split);
1455 if (uasm_insn_has_bdelay(relocs, split))
1456 uasm_i_nop(&f);
1457 else {
1458 uasm_copy_handler(relocs, labels,
1459 split, split + 1, f);
1460 uasm_move_labels(labels, f, f + 1, -1);
1461 f++;
1462 split++;
1463 }
1464 }
1465
1466 /* Copy the rest of the handler. */
1467 uasm_copy_handler(relocs, labels, split, p, final_handler);
1468 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1469 (p - split);
1470 }
1471 }
1472 break;
1473 }
1474
1475 uasm_resolve_relocs(relocs, labels);
1476 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1477 final_len);
1478
1479 memcpy((void *)ebase, final_handler, 0x100);
1480 local_flush_icache_range(ebase, ebase + 0x100);
1481
1482 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1483 }
1484
setup_pw(void)1485 static void setup_pw(void)
1486 {
1487 unsigned long pgd_i, pgd_w;
1488 #ifndef __PAGETABLE_PMD_FOLDED
1489 unsigned long pmd_i, pmd_w;
1490 #endif
1491 unsigned long pt_i, pt_w;
1492 unsigned long pte_i, pte_w;
1493 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1494 unsigned long psn;
1495
1496 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
1497 #endif
1498 pgd_i = PGDIR_SHIFT; /* 1st level PGD */
1499 #ifndef __PAGETABLE_PMD_FOLDED
1500 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1501
1502 pmd_i = PMD_SHIFT; /* 2nd level PMD */
1503 pmd_w = PMD_SHIFT - PAGE_SHIFT;
1504 #else
1505 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1506 #endif
1507
1508 pt_i = PAGE_SHIFT; /* 3rd level PTE */
1509 pt_w = PAGE_SHIFT - 3;
1510
1511 pte_i = ilog2(_PAGE_GLOBAL);
1512 pte_w = 0;
1513
1514 #ifndef __PAGETABLE_PMD_FOLDED
1515 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1516 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1517 #else
1518 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1519 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1520 #endif
1521
1522 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1523 write_c0_pwctl(1 << 6 | psn);
1524 #endif
1525 write_c0_kpgd(swapper_pg_dir);
1526 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1527 }
1528
build_loongson3_tlb_refill_handler(void)1529 static void build_loongson3_tlb_refill_handler(void)
1530 {
1531 u32 *p = tlb_handler;
1532 struct uasm_label *l = labels;
1533 struct uasm_reloc *r = relocs;
1534
1535 memset(labels, 0, sizeof(labels));
1536 memset(relocs, 0, sizeof(relocs));
1537 memset(tlb_handler, 0, sizeof(tlb_handler));
1538
1539 if (check_for_high_segbits) {
1540 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1541 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1542 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1543 uasm_i_nop(&p);
1544
1545 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1546 uasm_i_nop(&p);
1547 uasm_l_vmalloc(&l, p);
1548 }
1549
1550 uasm_i_dmfc0(&p, K1, C0_PGD);
1551
1552 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
1553 #ifndef __PAGETABLE_PMD_FOLDED
1554 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
1555 #endif
1556 uasm_i_ldpte(&p, K1, 0); /* even */
1557 uasm_i_ldpte(&p, K1, 1); /* odd */
1558 uasm_i_tlbwr(&p);
1559
1560 /* restore page mask */
1561 if (PM_DEFAULT_MASK >> 16) {
1562 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1563 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1564 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1565 } else if (PM_DEFAULT_MASK) {
1566 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1567 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1568 } else {
1569 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1570 }
1571
1572 uasm_i_eret(&p);
1573
1574 if (check_for_high_segbits) {
1575 uasm_l_large_segbits_fault(&l, p);
1576 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1577 uasm_i_jr(&p, K1);
1578 uasm_i_nop(&p);
1579 }
1580
1581 uasm_resolve_relocs(relocs, labels);
1582 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1583 local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1584 dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32);
1585 }
1586
1587 extern u32 handle_tlbl[], handle_tlbl_end[];
1588 extern u32 handle_tlbs[], handle_tlbs_end[];
1589 extern u32 handle_tlbm[], handle_tlbm_end[];
1590 extern u32 tlbmiss_handler_setup_pgd_start[];
1591 extern u32 tlbmiss_handler_setup_pgd[];
1592 EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd);
1593 extern u32 tlbmiss_handler_setup_pgd_end[];
1594
build_setup_pgd(void)1595 static void build_setup_pgd(void)
1596 {
1597 const int a0 = 4;
1598 const int __maybe_unused a1 = 5;
1599 const int __maybe_unused a2 = 6;
1600 u32 *p = tlbmiss_handler_setup_pgd_start;
1601 const int tlbmiss_handler_setup_pgd_size =
1602 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1603 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1604 long pgdc = (long)pgd_current;
1605 #endif
1606
1607 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1608 sizeof(tlbmiss_handler_setup_pgd[0]));
1609 memset(labels, 0, sizeof(labels));
1610 memset(relocs, 0, sizeof(relocs));
1611 pgd_reg = allocate_kscratch();
1612 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1613 if (pgd_reg == -1) {
1614 struct uasm_label *l = labels;
1615 struct uasm_reloc *r = relocs;
1616
1617 /* PGD << 11 in c0_Context */
1618 /*
1619 * If it is a ckseg0 address, convert to a physical
1620 * address. Shifting right by 29 and adding 4 will
1621 * result in zero for these addresses.
1622 *
1623 */
1624 UASM_i_SRA(&p, a1, a0, 29);
1625 UASM_i_ADDIU(&p, a1, a1, 4);
1626 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1627 uasm_i_nop(&p);
1628 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1629 uasm_l_tlbl_goaround1(&l, p);
1630 UASM_i_SLL(&p, a0, a0, 11);
1631 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1632 uasm_i_jr(&p, 31);
1633 uasm_i_ehb(&p);
1634 } else {
1635 /* PGD in c0_KScratch */
1636 if (cpu_has_ldpte)
1637 UASM_i_MTC0(&p, a0, C0_PWBASE);
1638 else
1639 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1640 uasm_i_jr(&p, 31);
1641 uasm_i_ehb(&p);
1642 }
1643 #else
1644 #ifdef CONFIG_SMP
1645 /* Save PGD to pgd_current[smp_processor_id()] */
1646 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1647 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1648 UASM_i_LA_mostly(&p, a2, pgdc);
1649 UASM_i_ADDU(&p, a2, a2, a1);
1650 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1651 #else
1652 UASM_i_LA_mostly(&p, a2, pgdc);
1653 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1654 #endif /* SMP */
1655
1656 /* if pgd_reg is allocated, save PGD also to scratch register */
1657 if (pgd_reg != -1) {
1658 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1659 uasm_i_jr(&p, 31);
1660 uasm_i_ehb(&p);
1661 } else {
1662 uasm_i_jr(&p, 31);
1663 uasm_i_nop(&p);
1664 }
1665 #endif
1666 if (p >= tlbmiss_handler_setup_pgd_end)
1667 panic("tlbmiss_handler_setup_pgd space exceeded");
1668
1669 uasm_resolve_relocs(relocs, labels);
1670 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1671 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1672
1673 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1674 tlbmiss_handler_setup_pgd_size);
1675 }
1676
1677 static void
iPTE_LW(u32 ** p,unsigned int pte,unsigned int ptr)1678 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1679 {
1680 #ifdef CONFIG_SMP
1681 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1682 if (cpu_has_64bits)
1683 uasm_i_lld(p, pte, 0, ptr);
1684 else
1685 # endif
1686 UASM_i_LL(p, pte, 0, ptr);
1687 #else
1688 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1689 if (cpu_has_64bits)
1690 uasm_i_ld(p, pte, 0, ptr);
1691 else
1692 # endif
1693 UASM_i_LW(p, pte, 0, ptr);
1694 #endif
1695 }
1696
1697 static void
iPTE_SW(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,unsigned int mode,unsigned int scratch)1698 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1699 unsigned int mode, unsigned int scratch)
1700 {
1701 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1702 unsigned int swmode = mode & ~hwmode;
1703
1704 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
1705 uasm_i_lui(p, scratch, swmode >> 16);
1706 uasm_i_or(p, pte, pte, scratch);
1707 BUG_ON(swmode & 0xffff);
1708 } else {
1709 uasm_i_ori(p, pte, pte, mode);
1710 }
1711
1712 #ifdef CONFIG_SMP
1713 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1714 if (cpu_has_64bits)
1715 uasm_i_scd(p, pte, 0, ptr);
1716 else
1717 # endif
1718 UASM_i_SC(p, pte, 0, ptr);
1719
1720 if (r10000_llsc_war())
1721 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1722 else
1723 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1724
1725 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1726 if (!cpu_has_64bits) {
1727 /* no uasm_i_nop needed */
1728 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1729 uasm_i_ori(p, pte, pte, hwmode);
1730 BUG_ON(hwmode & ~0xffff);
1731 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1732 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1733 /* no uasm_i_nop needed */
1734 uasm_i_lw(p, pte, 0, ptr);
1735 } else
1736 uasm_i_nop(p);
1737 # else
1738 uasm_i_nop(p);
1739 # endif
1740 #else
1741 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1742 if (cpu_has_64bits)
1743 uasm_i_sd(p, pte, 0, ptr);
1744 else
1745 # endif
1746 UASM_i_SW(p, pte, 0, ptr);
1747
1748 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1749 if (!cpu_has_64bits) {
1750 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1751 uasm_i_ori(p, pte, pte, hwmode);
1752 BUG_ON(hwmode & ~0xffff);
1753 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1754 uasm_i_lw(p, pte, 0, ptr);
1755 }
1756 # endif
1757 #endif
1758 }
1759
1760 /*
1761 * Check if PTE is present, if not then jump to LABEL. PTR points to
1762 * the page table where this PTE is located, PTE will be re-loaded
1763 * with it's original value.
1764 */
1765 static void
build_pte_present(u32 ** p,struct uasm_reloc ** r,int pte,int ptr,int scratch,enum label_id lid)1766 build_pte_present(u32 **p, struct uasm_reloc **r,
1767 int pte, int ptr, int scratch, enum label_id lid)
1768 {
1769 int t = scratch >= 0 ? scratch : pte;
1770 int cur = pte;
1771
1772 if (cpu_has_rixi) {
1773 if (use_bbit_insns()) {
1774 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1775 uasm_i_nop(p);
1776 } else {
1777 if (_PAGE_PRESENT_SHIFT) {
1778 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1779 cur = t;
1780 }
1781 uasm_i_andi(p, t, cur, 1);
1782 uasm_il_beqz(p, r, t, lid);
1783 if (pte == t)
1784 /* You lose the SMP race :-(*/
1785 iPTE_LW(p, pte, ptr);
1786 }
1787 } else {
1788 if (_PAGE_PRESENT_SHIFT) {
1789 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1790 cur = t;
1791 }
1792 uasm_i_andi(p, t, cur,
1793 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1794 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
1795 uasm_il_bnez(p, r, t, lid);
1796 if (pte == t)
1797 /* You lose the SMP race :-(*/
1798 iPTE_LW(p, pte, ptr);
1799 }
1800 }
1801
1802 /* Make PTE valid, store result in PTR. */
1803 static void
build_make_valid(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,unsigned int scratch)1804 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1805 unsigned int ptr, unsigned int scratch)
1806 {
1807 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1808
1809 iPTE_SW(p, r, pte, ptr, mode, scratch);
1810 }
1811
1812 /*
1813 * Check if PTE can be written to, if not branch to LABEL. Regardless
1814 * restore PTE with value from PTR when done.
1815 */
1816 static void
build_pte_writable(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,int scratch,enum label_id lid)1817 build_pte_writable(u32 **p, struct uasm_reloc **r,
1818 unsigned int pte, unsigned int ptr, int scratch,
1819 enum label_id lid)
1820 {
1821 int t = scratch >= 0 ? scratch : pte;
1822 int cur = pte;
1823
1824 if (_PAGE_PRESENT_SHIFT) {
1825 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1826 cur = t;
1827 }
1828 uasm_i_andi(p, t, cur,
1829 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1830 uasm_i_xori(p, t, t,
1831 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1832 uasm_il_bnez(p, r, t, lid);
1833 if (pte == t)
1834 /* You lose the SMP race :-(*/
1835 iPTE_LW(p, pte, ptr);
1836 else
1837 uasm_i_nop(p);
1838 }
1839
1840 /* Make PTE writable, update software status bits as well, then store
1841 * at PTR.
1842 */
1843 static void
build_make_write(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,unsigned int scratch)1844 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1845 unsigned int ptr, unsigned int scratch)
1846 {
1847 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1848 | _PAGE_DIRTY);
1849
1850 iPTE_SW(p, r, pte, ptr, mode, scratch);
1851 }
1852
1853 /*
1854 * Check if PTE can be modified, if not branch to LABEL. Regardless
1855 * restore PTE with value from PTR when done.
1856 */
1857 static void
build_pte_modifiable(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,int scratch,enum label_id lid)1858 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1859 unsigned int pte, unsigned int ptr, int scratch,
1860 enum label_id lid)
1861 {
1862 if (use_bbit_insns()) {
1863 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1864 uasm_i_nop(p);
1865 } else {
1866 int t = scratch >= 0 ? scratch : pte;
1867 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1868 uasm_i_andi(p, t, t, 1);
1869 uasm_il_beqz(p, r, t, lid);
1870 if (pte == t)
1871 /* You lose the SMP race :-(*/
1872 iPTE_LW(p, pte, ptr);
1873 }
1874 }
1875
1876 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1877
1878
1879 /*
1880 * R3000 style TLB load/store/modify handlers.
1881 */
1882
1883 /*
1884 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1885 * Then it returns.
1886 */
1887 static void
build_r3000_pte_reload_tlbwi(u32 ** p,unsigned int pte,unsigned int tmp)1888 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1889 {
1890 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1891 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1892 uasm_i_tlbwi(p);
1893 uasm_i_jr(p, tmp);
1894 uasm_i_rfe(p); /* branch delay */
1895 }
1896
1897 /*
1898 * This places the pte into ENTRYLO0 and writes it with tlbwi
1899 * or tlbwr as appropriate. This is because the index register
1900 * may have the probe fail bit set as a result of a trap on a
1901 * kseg2 access, i.e. without refill. Then it returns.
1902 */
1903 static void
build_r3000_tlb_reload_write(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int pte,unsigned int tmp)1904 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1905 struct uasm_reloc **r, unsigned int pte,
1906 unsigned int tmp)
1907 {
1908 uasm_i_mfc0(p, tmp, C0_INDEX);
1909 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1910 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1911 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1912 uasm_i_tlbwi(p); /* cp0 delay */
1913 uasm_i_jr(p, tmp);
1914 uasm_i_rfe(p); /* branch delay */
1915 uasm_l_r3000_write_probe_fail(l, *p);
1916 uasm_i_tlbwr(p); /* cp0 delay */
1917 uasm_i_jr(p, tmp);
1918 uasm_i_rfe(p); /* branch delay */
1919 }
1920
1921 static void
build_r3000_tlbchange_handler_head(u32 ** p,unsigned int pte,unsigned int ptr)1922 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1923 unsigned int ptr)
1924 {
1925 long pgdc = (long)pgd_current;
1926
1927 uasm_i_mfc0(p, pte, C0_BADVADDR);
1928 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1929 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1930 uasm_i_srl(p, pte, pte, 22); /* load delay */
1931 uasm_i_sll(p, pte, pte, 2);
1932 uasm_i_addu(p, ptr, ptr, pte);
1933 uasm_i_mfc0(p, pte, C0_CONTEXT);
1934 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1935 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1936 uasm_i_addu(p, ptr, ptr, pte);
1937 uasm_i_lw(p, pte, 0, ptr);
1938 uasm_i_tlbp(p); /* load delay */
1939 }
1940
build_r3000_tlb_load_handler(void)1941 static void build_r3000_tlb_load_handler(void)
1942 {
1943 u32 *p = handle_tlbl;
1944 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1945 struct uasm_label *l = labels;
1946 struct uasm_reloc *r = relocs;
1947
1948 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1949 memset(labels, 0, sizeof(labels));
1950 memset(relocs, 0, sizeof(relocs));
1951
1952 build_r3000_tlbchange_handler_head(&p, K0, K1);
1953 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1954 uasm_i_nop(&p); /* load delay */
1955 build_make_valid(&p, &r, K0, K1, -1);
1956 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1957
1958 uasm_l_nopage_tlbl(&l, p);
1959 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1960 uasm_i_nop(&p);
1961
1962 if (p >= handle_tlbl_end)
1963 panic("TLB load handler fastpath space exceeded");
1964
1965 uasm_resolve_relocs(relocs, labels);
1966 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1967 (unsigned int)(p - handle_tlbl));
1968
1969 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1970 }
1971
build_r3000_tlb_store_handler(void)1972 static void build_r3000_tlb_store_handler(void)
1973 {
1974 u32 *p = handle_tlbs;
1975 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1976 struct uasm_label *l = labels;
1977 struct uasm_reloc *r = relocs;
1978
1979 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1980 memset(labels, 0, sizeof(labels));
1981 memset(relocs, 0, sizeof(relocs));
1982
1983 build_r3000_tlbchange_handler_head(&p, K0, K1);
1984 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1985 uasm_i_nop(&p); /* load delay */
1986 build_make_write(&p, &r, K0, K1, -1);
1987 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1988
1989 uasm_l_nopage_tlbs(&l, p);
1990 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1991 uasm_i_nop(&p);
1992
1993 if (p >= handle_tlbs_end)
1994 panic("TLB store handler fastpath space exceeded");
1995
1996 uasm_resolve_relocs(relocs, labels);
1997 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1998 (unsigned int)(p - handle_tlbs));
1999
2000 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
2001 }
2002
build_r3000_tlb_modify_handler(void)2003 static void build_r3000_tlb_modify_handler(void)
2004 {
2005 u32 *p = handle_tlbm;
2006 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2007 struct uasm_label *l = labels;
2008 struct uasm_reloc *r = relocs;
2009
2010 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2011 memset(labels, 0, sizeof(labels));
2012 memset(relocs, 0, sizeof(relocs));
2013
2014 build_r3000_tlbchange_handler_head(&p, K0, K1);
2015 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
2016 uasm_i_nop(&p); /* load delay */
2017 build_make_write(&p, &r, K0, K1, -1);
2018 build_r3000_pte_reload_tlbwi(&p, K0, K1);
2019
2020 uasm_l_nopage_tlbm(&l, p);
2021 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2022 uasm_i_nop(&p);
2023
2024 if (p >= handle_tlbm_end)
2025 panic("TLB modify handler fastpath space exceeded");
2026
2027 uasm_resolve_relocs(relocs, labels);
2028 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2029 (unsigned int)(p - handle_tlbm));
2030
2031 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
2032 }
2033 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
2034
cpu_has_tlbex_tlbp_race(void)2035 static bool cpu_has_tlbex_tlbp_race(void)
2036 {
2037 /*
2038 * When a Hardware Table Walker is running it can replace TLB entries
2039 * at any time, leading to a race between it & the CPU.
2040 */
2041 if (cpu_has_htw)
2042 return true;
2043
2044 /*
2045 * If the CPU shares FTLB RAM with its siblings then our entry may be
2046 * replaced at any time by a sibling performing a write to the FTLB.
2047 */
2048 if (cpu_has_shared_ftlb_ram)
2049 return true;
2050
2051 /* In all other cases there ought to be no race condition to handle */
2052 return false;
2053 }
2054
2055 /*
2056 * R4000 style TLB load/store/modify handlers.
2057 */
2058 static struct work_registers
build_r4000_tlbchange_handler_head(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r)2059 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
2060 struct uasm_reloc **r)
2061 {
2062 struct work_registers wr = build_get_work_registers(p);
2063
2064 #ifdef CONFIG_64BIT
2065 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
2066 #else
2067 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
2068 #endif
2069
2070 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2071 /*
2072 * For huge tlb entries, pmd doesn't contain an address but
2073 * instead contains the tlb pte. Check the PAGE_HUGE bit and
2074 * see if we need to jump to huge tlb processing.
2075 */
2076 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
2077 #endif
2078
2079 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2080 UASM_i_LW(p, wr.r2, 0, wr.r2);
2081 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2082 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2083 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
2084
2085 #ifdef CONFIG_SMP
2086 uasm_l_smp_pgtable_change(l, *p);
2087 #endif
2088 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2089 if (!m4kc_tlbp_war()) {
2090 build_tlb_probe_entry(p);
2091 if (cpu_has_tlbex_tlbp_race()) {
2092 /* race condition happens, leaving */
2093 uasm_i_ehb(p);
2094 uasm_i_mfc0(p, wr.r3, C0_INDEX);
2095 uasm_il_bltz(p, r, wr.r3, label_leave);
2096 uasm_i_nop(p);
2097 }
2098 }
2099 return wr;
2100 }
2101
2102 static void
build_r4000_tlbchange_handler_tail(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,unsigned int ptr)2103 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2104 struct uasm_reloc **r, unsigned int tmp,
2105 unsigned int ptr)
2106 {
2107 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2108 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
2109 build_update_entries(p, tmp, ptr);
2110 build_tlb_write_entry(p, l, r, tlb_indexed);
2111 uasm_l_leave(l, *p);
2112 build_restore_work_registers(p);
2113 uasm_i_eret(p); /* return from trap */
2114
2115 #ifdef CONFIG_64BIT
2116 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
2117 #endif
2118 }
2119
build_r4000_tlb_load_handler(void)2120 static void build_r4000_tlb_load_handler(void)
2121 {
2122 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
2123 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
2124 struct uasm_label *l = labels;
2125 struct uasm_reloc *r = relocs;
2126 struct work_registers wr;
2127
2128 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
2129 memset(labels, 0, sizeof(labels));
2130 memset(relocs, 0, sizeof(relocs));
2131
2132 if (bcm1250_m3_war()) {
2133 unsigned int segbits = 44;
2134
2135 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2136 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
2137 uasm_i_xor(&p, K0, K0, K1);
2138 uasm_i_dsrl_safe(&p, K1, K0, 62);
2139 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2140 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
2141 uasm_i_or(&p, K0, K0, K1);
2142 uasm_il_bnez(&p, &r, K0, label_leave);
2143 /* No need for uasm_i_nop */
2144 }
2145
2146 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2147 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2148 if (m4kc_tlbp_war())
2149 build_tlb_probe_entry(&p);
2150
2151 if (cpu_has_rixi && !cpu_has_rixiex) {
2152 /*
2153 * If the page is not _PAGE_VALID, RI or XI could not
2154 * have triggered it. Skip the expensive test..
2155 */
2156 if (use_bbit_insns()) {
2157 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2158 label_tlbl_goaround1);
2159 } else {
2160 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2161 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
2162 }
2163 uasm_i_nop(&p);
2164
2165 /*
2166 * Warn if something may race with us & replace the TLB entry
2167 * before we read it here. Everything with such races should
2168 * also have dedicated RiXi exception handlers, so this
2169 * shouldn't be hit.
2170 */
2171 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2172
2173 uasm_i_tlbr(&p);
2174
2175 switch (current_cpu_type()) {
2176 default:
2177 if (cpu_has_mips_r2_exec_hazard) {
2178 uasm_i_ehb(&p);
2179
2180 case CPU_CAVIUM_OCTEON:
2181 case CPU_CAVIUM_OCTEON_PLUS:
2182 case CPU_CAVIUM_OCTEON2:
2183 break;
2184 }
2185 }
2186
2187 /* Examine entrylo 0 or 1 based on ptr. */
2188 if (use_bbit_insns()) {
2189 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2190 } else {
2191 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2192 uasm_i_beqz(&p, wr.r3, 8);
2193 }
2194 /* load it in the delay slot*/
2195 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2196 /* load it if ptr is odd */
2197 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2198 /*
2199 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2200 * XI must have triggered it.
2201 */
2202 if (use_bbit_insns()) {
2203 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2204 uasm_i_nop(&p);
2205 uasm_l_tlbl_goaround1(&l, p);
2206 } else {
2207 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2208 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2209 uasm_i_nop(&p);
2210 }
2211 uasm_l_tlbl_goaround1(&l, p);
2212 }
2213 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
2214 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2215
2216 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2217 /*
2218 * This is the entry point when build_r4000_tlbchange_handler_head
2219 * spots a huge page.
2220 */
2221 uasm_l_tlb_huge_update(&l, p);
2222 iPTE_LW(&p, wr.r1, wr.r2);
2223 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2224 build_tlb_probe_entry(&p);
2225
2226 if (cpu_has_rixi && !cpu_has_rixiex) {
2227 /*
2228 * If the page is not _PAGE_VALID, RI or XI could not
2229 * have triggered it. Skip the expensive test..
2230 */
2231 if (use_bbit_insns()) {
2232 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2233 label_tlbl_goaround2);
2234 } else {
2235 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2236 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2237 }
2238 uasm_i_nop(&p);
2239
2240 /*
2241 * Warn if something may race with us & replace the TLB entry
2242 * before we read it here. Everything with such races should
2243 * also have dedicated RiXi exception handlers, so this
2244 * shouldn't be hit.
2245 */
2246 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2247
2248 uasm_i_tlbr(&p);
2249
2250 switch (current_cpu_type()) {
2251 default:
2252 if (cpu_has_mips_r2_exec_hazard) {
2253 uasm_i_ehb(&p);
2254
2255 case CPU_CAVIUM_OCTEON:
2256 case CPU_CAVIUM_OCTEON_PLUS:
2257 case CPU_CAVIUM_OCTEON2:
2258 break;
2259 }
2260 }
2261
2262 /* Examine entrylo 0 or 1 based on ptr. */
2263 if (use_bbit_insns()) {
2264 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2265 } else {
2266 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2267 uasm_i_beqz(&p, wr.r3, 8);
2268 }
2269 /* load it in the delay slot*/
2270 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2271 /* load it if ptr is odd */
2272 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2273 /*
2274 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2275 * XI must have triggered it.
2276 */
2277 if (use_bbit_insns()) {
2278 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2279 } else {
2280 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2281 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2282 }
2283 if (PM_DEFAULT_MASK == 0)
2284 uasm_i_nop(&p);
2285 /*
2286 * We clobbered C0_PAGEMASK, restore it. On the other branch
2287 * it is restored in build_huge_tlb_write_entry.
2288 */
2289 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2290
2291 uasm_l_tlbl_goaround2(&l, p);
2292 }
2293 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2294 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2295 #endif
2296
2297 uasm_l_nopage_tlbl(&l, p);
2298 build_restore_work_registers(&p);
2299 #ifdef CONFIG_CPU_MICROMIPS
2300 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2301 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2302 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2303 uasm_i_jr(&p, K0);
2304 } else
2305 #endif
2306 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2307 uasm_i_nop(&p);
2308
2309 if (p >= handle_tlbl_end)
2310 panic("TLB load handler fastpath space exceeded");
2311
2312 uasm_resolve_relocs(relocs, labels);
2313 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2314 (unsigned int)(p - handle_tlbl));
2315
2316 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2317 }
2318
build_r4000_tlb_store_handler(void)2319 static void build_r4000_tlb_store_handler(void)
2320 {
2321 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
2322 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2323 struct uasm_label *l = labels;
2324 struct uasm_reloc *r = relocs;
2325 struct work_registers wr;
2326
2327 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2328 memset(labels, 0, sizeof(labels));
2329 memset(relocs, 0, sizeof(relocs));
2330
2331 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2332 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2333 if (m4kc_tlbp_war())
2334 build_tlb_probe_entry(&p);
2335 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2336 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2337
2338 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2339 /*
2340 * This is the entry point when
2341 * build_r4000_tlbchange_handler_head spots a huge page.
2342 */
2343 uasm_l_tlb_huge_update(&l, p);
2344 iPTE_LW(&p, wr.r1, wr.r2);
2345 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2346 build_tlb_probe_entry(&p);
2347 uasm_i_ori(&p, wr.r1, wr.r1,
2348 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2349 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2350 #endif
2351
2352 uasm_l_nopage_tlbs(&l, p);
2353 build_restore_work_registers(&p);
2354 #ifdef CONFIG_CPU_MICROMIPS
2355 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2356 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2357 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2358 uasm_i_jr(&p, K0);
2359 } else
2360 #endif
2361 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2362 uasm_i_nop(&p);
2363
2364 if (p >= handle_tlbs_end)
2365 panic("TLB store handler fastpath space exceeded");
2366
2367 uasm_resolve_relocs(relocs, labels);
2368 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2369 (unsigned int)(p - handle_tlbs));
2370
2371 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2372 }
2373
build_r4000_tlb_modify_handler(void)2374 static void build_r4000_tlb_modify_handler(void)
2375 {
2376 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
2377 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2378 struct uasm_label *l = labels;
2379 struct uasm_reloc *r = relocs;
2380 struct work_registers wr;
2381
2382 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2383 memset(labels, 0, sizeof(labels));
2384 memset(relocs, 0, sizeof(relocs));
2385
2386 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2387 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2388 if (m4kc_tlbp_war())
2389 build_tlb_probe_entry(&p);
2390 /* Present and writable bits set, set accessed and dirty bits. */
2391 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2392 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2393
2394 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2395 /*
2396 * This is the entry point when
2397 * build_r4000_tlbchange_handler_head spots a huge page.
2398 */
2399 uasm_l_tlb_huge_update(&l, p);
2400 iPTE_LW(&p, wr.r1, wr.r2);
2401 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2402 build_tlb_probe_entry(&p);
2403 uasm_i_ori(&p, wr.r1, wr.r1,
2404 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2405 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
2406 #endif
2407
2408 uasm_l_nopage_tlbm(&l, p);
2409 build_restore_work_registers(&p);
2410 #ifdef CONFIG_CPU_MICROMIPS
2411 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2412 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2413 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2414 uasm_i_jr(&p, K0);
2415 } else
2416 #endif
2417 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2418 uasm_i_nop(&p);
2419
2420 if (p >= handle_tlbm_end)
2421 panic("TLB modify handler fastpath space exceeded");
2422
2423 uasm_resolve_relocs(relocs, labels);
2424 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2425 (unsigned int)(p - handle_tlbm));
2426
2427 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2428 }
2429
flush_tlb_handlers(void)2430 static void flush_tlb_handlers(void)
2431 {
2432 local_flush_icache_range((unsigned long)handle_tlbl,
2433 (unsigned long)handle_tlbl_end);
2434 local_flush_icache_range((unsigned long)handle_tlbs,
2435 (unsigned long)handle_tlbs_end);
2436 local_flush_icache_range((unsigned long)handle_tlbm,
2437 (unsigned long)handle_tlbm_end);
2438 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2439 (unsigned long)tlbmiss_handler_setup_pgd_end);
2440 }
2441
print_htw_config(void)2442 static void print_htw_config(void)
2443 {
2444 unsigned long config;
2445 unsigned int pwctl;
2446 const int field = 2 * sizeof(unsigned long);
2447
2448 config = read_c0_pwfield();
2449 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2450 field, config,
2451 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2452 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2453 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2454 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2455 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2456
2457 config = read_c0_pwsize();
2458 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2459 field, config,
2460 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2461 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2462 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2463 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2464 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2465 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2466
2467 pwctl = read_c0_pwctl();
2468 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2469 pwctl,
2470 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2471 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2472 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2473 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2474 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2475 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2476 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2477 }
2478
config_htw_params(void)2479 static void config_htw_params(void)
2480 {
2481 unsigned long pwfield, pwsize, ptei;
2482 unsigned int config;
2483
2484 /*
2485 * We are using 2-level page tables, so we only need to
2486 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2487 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2488 * write values less than 0xc in these fields because the entire
2489 * write will be dropped. As a result of which, we must preserve
2490 * the original reset values and overwrite only what we really want.
2491 */
2492
2493 pwfield = read_c0_pwfield();
2494 /* re-initialize the GDI field */
2495 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2496 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2497 /* re-initialize the PTI field including the even/odd bit */
2498 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2499 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2500 if (CONFIG_PGTABLE_LEVELS >= 3) {
2501 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2502 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2503 }
2504 /* Set the PTEI right shift */
2505 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2506 pwfield |= ptei;
2507 write_c0_pwfield(pwfield);
2508 /* Check whether the PTEI value is supported */
2509 back_to_back_c0_hazard();
2510 pwfield = read_c0_pwfield();
2511 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2512 != ptei) {
2513 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2514 ptei);
2515 /*
2516 * Drop option to avoid HTW being enabled via another path
2517 * (eg htw_reset())
2518 */
2519 current_cpu_data.options &= ~MIPS_CPU_HTW;
2520 return;
2521 }
2522
2523 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2524 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2525 if (CONFIG_PGTABLE_LEVELS >= 3)
2526 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2527
2528 /* Set pointer size to size of directory pointers */
2529 if (IS_ENABLED(CONFIG_64BIT))
2530 pwsize |= MIPS_PWSIZE_PS_MASK;
2531 /* PTEs may be multiple pointers long (e.g. with XPA) */
2532 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2533 & MIPS_PWSIZE_PTEW_MASK;
2534
2535 write_c0_pwsize(pwsize);
2536
2537 /* Make sure everything is set before we enable the HTW */
2538 back_to_back_c0_hazard();
2539
2540 /*
2541 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2542 * the pwctl fields.
2543 */
2544 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2545 if (IS_ENABLED(CONFIG_64BIT))
2546 config |= MIPS_PWCTL_XU_MASK;
2547 write_c0_pwctl(config);
2548 pr_info("Hardware Page Table Walker enabled\n");
2549
2550 print_htw_config();
2551 }
2552
config_xpa_params(void)2553 static void config_xpa_params(void)
2554 {
2555 #ifdef CONFIG_XPA
2556 unsigned int pagegrain;
2557
2558 if (mips_xpa_disabled) {
2559 pr_info("Extended Physical Addressing (XPA) disabled\n");
2560 return;
2561 }
2562
2563 pagegrain = read_c0_pagegrain();
2564 write_c0_pagegrain(pagegrain | PG_ELPA);
2565 back_to_back_c0_hazard();
2566 pagegrain = read_c0_pagegrain();
2567
2568 if (pagegrain & PG_ELPA)
2569 pr_info("Extended Physical Addressing (XPA) enabled\n");
2570 else
2571 panic("Extended Physical Addressing (XPA) disabled");
2572 #endif
2573 }
2574
check_pabits(void)2575 static void check_pabits(void)
2576 {
2577 unsigned long entry;
2578 unsigned pabits, fillbits;
2579
2580 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2581 /*
2582 * We'll only be making use of the fact that we can rotate bits
2583 * into the fill if the CPU supports RIXI, so don't bother
2584 * probing this for CPUs which don't.
2585 */
2586 return;
2587 }
2588
2589 write_c0_entrylo0(~0ul);
2590 back_to_back_c0_hazard();
2591 entry = read_c0_entrylo0();
2592
2593 /* clear all non-PFN bits */
2594 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2595 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2596
2597 /* find a lower bound on PABITS, and upper bound on fill bits */
2598 pabits = fls_long(entry) + 6;
2599 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2600
2601 /* minus the RI & XI bits */
2602 fillbits -= min_t(unsigned, fillbits, 2);
2603
2604 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2605 fill_includes_sw_bits = true;
2606
2607 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2608 }
2609
build_tlb_refill_handler(void)2610 void build_tlb_refill_handler(void)
2611 {
2612 /*
2613 * The refill handler is generated per-CPU, multi-node systems
2614 * may have local storage for it. The other handlers are only
2615 * needed once.
2616 */
2617 static int run_once = 0;
2618
2619 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
2620 panic("Kernels supporting XPA currently require CPUs with RIXI");
2621
2622 output_pgtable_bits_defines();
2623 check_pabits();
2624
2625 #ifdef CONFIG_64BIT
2626 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2627 #endif
2628
2629 switch (current_cpu_type()) {
2630 case CPU_R2000:
2631 case CPU_R3000:
2632 case CPU_R3000A:
2633 case CPU_R3081E:
2634 case CPU_TX3912:
2635 case CPU_TX3922:
2636 case CPU_TX3927:
2637 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2638 if (cpu_has_local_ebase)
2639 build_r3000_tlb_refill_handler();
2640 if (!run_once) {
2641 if (!cpu_has_local_ebase)
2642 build_r3000_tlb_refill_handler();
2643 build_setup_pgd();
2644 build_r3000_tlb_load_handler();
2645 build_r3000_tlb_store_handler();
2646 build_r3000_tlb_modify_handler();
2647 flush_tlb_handlers();
2648 run_once++;
2649 }
2650 #else
2651 panic("No R3000 TLB refill handler");
2652 #endif
2653 break;
2654
2655 case CPU_R8000:
2656 panic("No R8000 TLB refill handler yet");
2657 break;
2658
2659 default:
2660 if (cpu_has_ldpte)
2661 setup_pw();
2662
2663 if (!run_once) {
2664 scratch_reg = allocate_kscratch();
2665 build_setup_pgd();
2666 build_r4000_tlb_load_handler();
2667 build_r4000_tlb_store_handler();
2668 build_r4000_tlb_modify_handler();
2669 if (cpu_has_ldpte)
2670 build_loongson3_tlb_refill_handler();
2671 else if (!cpu_has_local_ebase)
2672 build_r4000_tlb_refill_handler();
2673 flush_tlb_handlers();
2674 run_once++;
2675 }
2676 if (cpu_has_local_ebase)
2677 build_r4000_tlb_refill_handler();
2678 if (cpu_has_xpa)
2679 config_xpa_params();
2680 if (cpu_has_htw)
2681 config_htw_params();
2682 }
2683 }
2684