1 /*
2 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/idr.h>
40 #include <linux/module.h>
41 #include <linux/printk.h>
42 #ifdef CONFIG_INFINIBAND_QIB_DCA
43 #include <linux/dca.h>
44 #endif
45 #include <rdma/rdma_vt.h>
46
47 #include "qib.h"
48 #include "qib_common.h"
49 #include "qib_mad.h"
50 #ifdef CONFIG_DEBUG_FS
51 #include "qib_debugfs.h"
52 #include "qib_verbs.h"
53 #endif
54
55 #undef pr_fmt
56 #define pr_fmt(fmt) QIB_DRV_NAME ": " fmt
57
58 /*
59 * min buffers we want to have per context, after driver
60 */
61 #define QIB_MIN_USER_CTXT_BUFCNT 7
62
63 #define QLOGIC_IB_R_SOFTWARE_MASK 0xFF
64 #define QLOGIC_IB_R_SOFTWARE_SHIFT 24
65 #define QLOGIC_IB_R_EMULATOR_MASK (1ULL<<62)
66
67 /*
68 * Number of ctxts we are configured to use (to allow for more pio
69 * buffers per ctxt, etc.) Zero means use chip value.
70 */
71 ushort qib_cfgctxts;
72 module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO);
73 MODULE_PARM_DESC(cfgctxts, "Set max number of contexts to use");
74
75 unsigned qib_numa_aware;
76 module_param_named(numa_aware, qib_numa_aware, uint, S_IRUGO);
77 MODULE_PARM_DESC(numa_aware,
78 "0 -> PSM allocation close to HCA, 1 -> PSM allocation local to process");
79
80 /*
81 * If set, do not write to any regs if avoidable, hack to allow
82 * check for deranged default register values.
83 */
84 ushort qib_mini_init;
85 module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO);
86 MODULE_PARM_DESC(mini_init, "If set, do minimal diag init");
87
88 unsigned qib_n_krcv_queues;
89 module_param_named(krcvqs, qib_n_krcv_queues, uint, S_IRUGO);
90 MODULE_PARM_DESC(krcvqs, "number of kernel receive queues per IB port");
91
92 unsigned qib_cc_table_size;
93 module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO);
94 MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984");
95
96 static void verify_interrupt(unsigned long);
97
98 static struct idr qib_unit_table;
99 u32 qib_cpulist_count;
100 unsigned long *qib_cpulist;
101
102 /* set number of contexts we'll actually use */
qib_set_ctxtcnt(struct qib_devdata * dd)103 void qib_set_ctxtcnt(struct qib_devdata *dd)
104 {
105 if (!qib_cfgctxts) {
106 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus();
107 if (dd->cfgctxts > dd->ctxtcnt)
108 dd->cfgctxts = dd->ctxtcnt;
109 } else if (qib_cfgctxts < dd->num_pports)
110 dd->cfgctxts = dd->ctxtcnt;
111 else if (qib_cfgctxts <= dd->ctxtcnt)
112 dd->cfgctxts = qib_cfgctxts;
113 else
114 dd->cfgctxts = dd->ctxtcnt;
115 dd->freectxts = (dd->first_user_ctxt > dd->cfgctxts) ? 0 :
116 dd->cfgctxts - dd->first_user_ctxt;
117 }
118
119 /*
120 * Common code for creating the receive context array.
121 */
qib_create_ctxts(struct qib_devdata * dd)122 int qib_create_ctxts(struct qib_devdata *dd)
123 {
124 unsigned i;
125 int local_node_id = pcibus_to_node(dd->pcidev->bus);
126
127 if (local_node_id < 0)
128 local_node_id = numa_node_id();
129 dd->assigned_node_id = local_node_id;
130
131 /*
132 * Allocate full ctxtcnt array, rather than just cfgctxts, because
133 * cleanup iterates across all possible ctxts.
134 */
135 dd->rcd = kcalloc(dd->ctxtcnt, sizeof(*dd->rcd), GFP_KERNEL);
136 if (!dd->rcd)
137 return -ENOMEM;
138
139 /* create (one or more) kctxt */
140 for (i = 0; i < dd->first_user_ctxt; ++i) {
141 struct qib_pportdata *ppd;
142 struct qib_ctxtdata *rcd;
143
144 if (dd->skip_kctxt_mask & (1 << i))
145 continue;
146
147 ppd = dd->pport + (i % dd->num_pports);
148
149 rcd = qib_create_ctxtdata(ppd, i, dd->assigned_node_id);
150 if (!rcd) {
151 qib_dev_err(dd,
152 "Unable to allocate ctxtdata for Kernel ctxt, failing\n");
153 kfree(dd->rcd);
154 dd->rcd = NULL;
155 return -ENOMEM;
156 }
157 rcd->pkeys[0] = QIB_DEFAULT_P_KEY;
158 rcd->seq_cnt = 1;
159 }
160 return 0;
161 }
162
163 /*
164 * Common code for user and kernel context setup.
165 */
qib_create_ctxtdata(struct qib_pportdata * ppd,u32 ctxt,int node_id)166 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *ppd, u32 ctxt,
167 int node_id)
168 {
169 struct qib_devdata *dd = ppd->dd;
170 struct qib_ctxtdata *rcd;
171
172 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, node_id);
173 if (rcd) {
174 INIT_LIST_HEAD(&rcd->qp_wait_list);
175 rcd->node_id = node_id;
176 rcd->ppd = ppd;
177 rcd->dd = dd;
178 rcd->cnt = 1;
179 rcd->ctxt = ctxt;
180 dd->rcd[ctxt] = rcd;
181 #ifdef CONFIG_DEBUG_FS
182 if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */
183 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
184 GFP_KERNEL, node_id);
185 if (!rcd->opstats) {
186 kfree(rcd);
187 qib_dev_err(dd,
188 "Unable to allocate per ctxt stats buffer\n");
189 return NULL;
190 }
191 }
192 #endif
193 dd->f_init_ctxt(rcd);
194
195 /*
196 * To avoid wasting a lot of memory, we allocate 32KB chunks
197 * of physically contiguous memory, advance through it until
198 * used up and then allocate more. Of course, we need
199 * memory to store those extra pointers, now. 32KB seems to
200 * be the most that is "safe" under memory pressure
201 * (creating large files and then copying them over
202 * NFS while doing lots of MPI jobs). The OOM killer can
203 * get invoked, even though we say we can sleep and this can
204 * cause significant system problems....
205 */
206 rcd->rcvegrbuf_size = 0x8000;
207 rcd->rcvegrbufs_perchunk =
208 rcd->rcvegrbuf_size / dd->rcvegrbufsize;
209 rcd->rcvegrbuf_chunks = (rcd->rcvegrcnt +
210 rcd->rcvegrbufs_perchunk - 1) /
211 rcd->rcvegrbufs_perchunk;
212 BUG_ON(!is_power_of_2(rcd->rcvegrbufs_perchunk));
213 rcd->rcvegrbufs_perchunk_shift =
214 ilog2(rcd->rcvegrbufs_perchunk);
215 }
216 return rcd;
217 }
218
219 /*
220 * Common code for initializing the physical port structure.
221 */
qib_init_pportdata(struct qib_pportdata * ppd,struct qib_devdata * dd,u8 hw_pidx,u8 port)222 int qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
223 u8 hw_pidx, u8 port)
224 {
225 int size;
226
227 ppd->dd = dd;
228 ppd->hw_pidx = hw_pidx;
229 ppd->port = port; /* IB port number, not index */
230
231 spin_lock_init(&ppd->sdma_lock);
232 spin_lock_init(&ppd->lflags_lock);
233 spin_lock_init(&ppd->cc_shadow_lock);
234 init_waitqueue_head(&ppd->state_wait);
235
236 setup_timer(&ppd->symerr_clear_timer, qib_clear_symerror_on_linkup,
237 (unsigned long)ppd);
238
239 ppd->qib_wq = NULL;
240 ppd->ibport_data.pmastats =
241 alloc_percpu(struct qib_pma_counters);
242 if (!ppd->ibport_data.pmastats)
243 return -ENOMEM;
244 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
245 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
246 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
247 if (!(ppd->ibport_data.rvp.rc_acks) ||
248 !(ppd->ibport_data.rvp.rc_qacks) ||
249 !(ppd->ibport_data.rvp.rc_delayed_comp))
250 return -ENOMEM;
251
252 if (qib_cc_table_size < IB_CCT_MIN_ENTRIES)
253 goto bail;
254
255 ppd->cc_supported_table_entries = min(max_t(int, qib_cc_table_size,
256 IB_CCT_MIN_ENTRIES), IB_CCT_ENTRIES*IB_CC_TABLE_CAP_DEFAULT);
257
258 ppd->cc_max_table_entries =
259 ppd->cc_supported_table_entries/IB_CCT_ENTRIES;
260
261 size = IB_CC_TABLE_CAP_DEFAULT * sizeof(struct ib_cc_table_entry)
262 * IB_CCT_ENTRIES;
263 ppd->ccti_entries = kzalloc(size, GFP_KERNEL);
264 if (!ppd->ccti_entries)
265 goto bail;
266
267 size = IB_CC_CCS_ENTRIES * sizeof(struct ib_cc_congestion_entry);
268 ppd->congestion_entries = kzalloc(size, GFP_KERNEL);
269 if (!ppd->congestion_entries)
270 goto bail_1;
271
272 size = sizeof(struct cc_table_shadow);
273 ppd->ccti_entries_shadow = kzalloc(size, GFP_KERNEL);
274 if (!ppd->ccti_entries_shadow)
275 goto bail_2;
276
277 size = sizeof(struct ib_cc_congestion_setting_attr);
278 ppd->congestion_entries_shadow = kzalloc(size, GFP_KERNEL);
279 if (!ppd->congestion_entries_shadow)
280 goto bail_3;
281
282 return 0;
283
284 bail_3:
285 kfree(ppd->ccti_entries_shadow);
286 ppd->ccti_entries_shadow = NULL;
287 bail_2:
288 kfree(ppd->congestion_entries);
289 ppd->congestion_entries = NULL;
290 bail_1:
291 kfree(ppd->ccti_entries);
292 ppd->ccti_entries = NULL;
293 bail:
294 /* User is intentionally disabling the congestion control agent */
295 if (!qib_cc_table_size)
296 return 0;
297
298 if (qib_cc_table_size < IB_CCT_MIN_ENTRIES) {
299 qib_cc_table_size = 0;
300 qib_dev_err(dd,
301 "Congestion Control table size %d less than minimum %d for port %d\n",
302 qib_cc_table_size, IB_CCT_MIN_ENTRIES, port);
303 }
304
305 qib_dev_err(dd, "Congestion Control Agent disabled for port %d\n",
306 port);
307 return 0;
308 }
309
init_pioavailregs(struct qib_devdata * dd)310 static int init_pioavailregs(struct qib_devdata *dd)
311 {
312 int ret, pidx;
313 u64 *status_page;
314
315 dd->pioavailregs_dma = dma_alloc_coherent(
316 &dd->pcidev->dev, PAGE_SIZE, &dd->pioavailregs_phys,
317 GFP_KERNEL);
318 if (!dd->pioavailregs_dma) {
319 qib_dev_err(dd,
320 "failed to allocate PIOavail reg area in memory\n");
321 ret = -ENOMEM;
322 goto done;
323 }
324
325 /*
326 * We really want L2 cache aligned, but for current CPUs of
327 * interest, they are the same.
328 */
329 status_page = (u64 *)
330 ((char *) dd->pioavailregs_dma +
331 ((2 * L1_CACHE_BYTES +
332 dd->pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
333 /* device status comes first, for backwards compatibility */
334 dd->devstatusp = status_page;
335 *status_page++ = 0;
336 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
337 dd->pport[pidx].statusp = status_page;
338 *status_page++ = 0;
339 }
340
341 /*
342 * Setup buffer to hold freeze and other messages, accessible to
343 * apps, following statusp. This is per-unit, not per port.
344 */
345 dd->freezemsg = (char *) status_page;
346 *dd->freezemsg = 0;
347 /* length of msg buffer is "whatever is left" */
348 ret = (char *) status_page - (char *) dd->pioavailregs_dma;
349 dd->freezelen = PAGE_SIZE - ret;
350
351 ret = 0;
352
353 done:
354 return ret;
355 }
356
357 /**
358 * init_shadow_tids - allocate the shadow TID array
359 * @dd: the qlogic_ib device
360 *
361 * allocate the shadow TID array, so we can qib_munlock previous
362 * entries. It may make more sense to move the pageshadow to the
363 * ctxt data structure, so we only allocate memory for ctxts actually
364 * in use, since we at 8k per ctxt, now.
365 * We don't want failures here to prevent use of the driver/chip,
366 * so no return value.
367 */
init_shadow_tids(struct qib_devdata * dd)368 static void init_shadow_tids(struct qib_devdata *dd)
369 {
370 struct page **pages;
371 dma_addr_t *addrs;
372
373 pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *));
374 if (!pages)
375 goto bail;
376
377 addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t));
378 if (!addrs)
379 goto bail_free;
380
381 dd->pageshadow = pages;
382 dd->physshadow = addrs;
383 return;
384
385 bail_free:
386 vfree(pages);
387 bail:
388 dd->pageshadow = NULL;
389 }
390
391 /*
392 * Do initialization for device that is only needed on
393 * first detect, not on resets.
394 */
loadtime_init(struct qib_devdata * dd)395 static int loadtime_init(struct qib_devdata *dd)
396 {
397 int ret = 0;
398
399 if (((dd->revision >> QLOGIC_IB_R_SOFTWARE_SHIFT) &
400 QLOGIC_IB_R_SOFTWARE_MASK) != QIB_CHIP_SWVERSION) {
401 qib_dev_err(dd,
402 "Driver only handles version %d, chip swversion is %d (%llx), failing\n",
403 QIB_CHIP_SWVERSION,
404 (int)(dd->revision >>
405 QLOGIC_IB_R_SOFTWARE_SHIFT) &
406 QLOGIC_IB_R_SOFTWARE_MASK,
407 (unsigned long long) dd->revision);
408 ret = -ENOSYS;
409 goto done;
410 }
411
412 if (dd->revision & QLOGIC_IB_R_EMULATOR_MASK)
413 qib_devinfo(dd->pcidev, "%s", dd->boardversion);
414
415 spin_lock_init(&dd->pioavail_lock);
416 spin_lock_init(&dd->sendctrl_lock);
417 spin_lock_init(&dd->uctxt_lock);
418 spin_lock_init(&dd->qib_diag_trans_lock);
419 spin_lock_init(&dd->eep_st_lock);
420 mutex_init(&dd->eep_lock);
421
422 if (qib_mini_init)
423 goto done;
424
425 ret = init_pioavailregs(dd);
426 init_shadow_tids(dd);
427
428 qib_get_eeprom_info(dd);
429
430 /* setup time (don't start yet) to verify we got interrupt */
431 setup_timer(&dd->intrchk_timer, verify_interrupt,
432 (unsigned long)dd);
433 done:
434 return ret;
435 }
436
437 /**
438 * init_after_reset - re-initialize after a reset
439 * @dd: the qlogic_ib device
440 *
441 * sanity check at least some of the values after reset, and
442 * ensure no receive or transmit (explicitly, in case reset
443 * failed
444 */
init_after_reset(struct qib_devdata * dd)445 static int init_after_reset(struct qib_devdata *dd)
446 {
447 int i;
448
449 /*
450 * Ensure chip does no sends or receives, tail updates, or
451 * pioavail updates while we re-initialize. This is mostly
452 * for the driver data structures, not chip registers.
453 */
454 for (i = 0; i < dd->num_pports; ++i) {
455 /*
456 * ctxt == -1 means "all contexts". Only really safe for
457 * _dis_abling things, as here.
458 */
459 dd->f_rcvctrl(dd->pport + i, QIB_RCVCTRL_CTXT_DIS |
460 QIB_RCVCTRL_INTRAVAIL_DIS |
461 QIB_RCVCTRL_TAILUPD_DIS, -1);
462 /* Redundant across ports for some, but no big deal. */
463 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_DIS |
464 QIB_SENDCTRL_AVAIL_DIS);
465 }
466
467 return 0;
468 }
469
enable_chip(struct qib_devdata * dd)470 static void enable_chip(struct qib_devdata *dd)
471 {
472 u64 rcvmask;
473 int i;
474
475 /*
476 * Enable PIO send, and update of PIOavail regs to memory.
477 */
478 for (i = 0; i < dd->num_pports; ++i)
479 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_ENB |
480 QIB_SENDCTRL_AVAIL_ENB);
481 /*
482 * Enable kernel ctxts' receive and receive interrupt.
483 * Other ctxts done as user opens and inits them.
484 */
485 rcvmask = QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_INTRAVAIL_ENB;
486 rcvmask |= (dd->flags & QIB_NODMA_RTAIL) ?
487 QIB_RCVCTRL_TAILUPD_DIS : QIB_RCVCTRL_TAILUPD_ENB;
488 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
489 struct qib_ctxtdata *rcd = dd->rcd[i];
490
491 if (rcd)
492 dd->f_rcvctrl(rcd->ppd, rcvmask, i);
493 }
494 }
495
verify_interrupt(unsigned long opaque)496 static void verify_interrupt(unsigned long opaque)
497 {
498 struct qib_devdata *dd = (struct qib_devdata *) opaque;
499 u64 int_counter;
500
501 if (!dd)
502 return; /* being torn down */
503
504 /*
505 * If we don't have a lid or any interrupts, let the user know and
506 * don't bother checking again.
507 */
508 int_counter = qib_int_counter(dd) - dd->z_int_counter;
509 if (int_counter == 0) {
510 if (!dd->f_intr_fallback(dd))
511 dev_err(&dd->pcidev->dev,
512 "No interrupts detected, not usable.\n");
513 else /* re-arm the timer to see if fallback works */
514 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
515 }
516 }
517
init_piobuf_state(struct qib_devdata * dd)518 static void init_piobuf_state(struct qib_devdata *dd)
519 {
520 int i, pidx;
521 u32 uctxts;
522
523 /*
524 * Ensure all buffers are free, and fifos empty. Buffers
525 * are common, so only do once for port 0.
526 *
527 * After enable and qib_chg_pioavailkernel so we can safely
528 * enable pioavail updates and PIOENABLE. After this, packets
529 * are ready and able to go out.
530 */
531 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_ALL);
532 for (pidx = 0; pidx < dd->num_pports; ++pidx)
533 dd->f_sendctrl(dd->pport + pidx, QIB_SENDCTRL_FLUSH);
534
535 /*
536 * If not all sendbufs are used, add the one to each of the lower
537 * numbered contexts. pbufsctxt and lastctxt_piobuf are
538 * calculated in chip-specific code because it may cause some
539 * chip-specific adjustments to be made.
540 */
541 uctxts = dd->cfgctxts - dd->first_user_ctxt;
542 dd->ctxts_extrabuf = dd->pbufsctxt ?
543 dd->lastctxt_piobuf - (dd->pbufsctxt * uctxts) : 0;
544
545 /*
546 * Set up the shadow copies of the piobufavail registers,
547 * which we compare against the chip registers for now, and
548 * the in memory DMA'ed copies of the registers.
549 * By now pioavail updates to memory should have occurred, so
550 * copy them into our working/shadow registers; this is in
551 * case something went wrong with abort, but mostly to get the
552 * initial values of the generation bit correct.
553 */
554 for (i = 0; i < dd->pioavregs; i++) {
555 __le64 tmp;
556
557 tmp = dd->pioavailregs_dma[i];
558 /*
559 * Don't need to worry about pioavailkernel here
560 * because we will call qib_chg_pioavailkernel() later
561 * in initialization, to busy out buffers as needed.
562 */
563 dd->pioavailshadow[i] = le64_to_cpu(tmp);
564 }
565 while (i < ARRAY_SIZE(dd->pioavailshadow))
566 dd->pioavailshadow[i++] = 0; /* for debugging sanity */
567
568 /* after pioavailshadow is setup */
569 qib_chg_pioavailkernel(dd, 0, dd->piobcnt2k + dd->piobcnt4k,
570 TXCHK_CHG_TYPE_KERN, NULL);
571 dd->f_initvl15_bufs(dd);
572 }
573
574 /**
575 * qib_create_workqueues - create per port workqueues
576 * @dd: the qlogic_ib device
577 */
qib_create_workqueues(struct qib_devdata * dd)578 static int qib_create_workqueues(struct qib_devdata *dd)
579 {
580 int pidx;
581 struct qib_pportdata *ppd;
582
583 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
584 ppd = dd->pport + pidx;
585 if (!ppd->qib_wq) {
586 char wq_name[8]; /* 3 + 2 + 1 + 1 + 1 */
587
588 snprintf(wq_name, sizeof(wq_name), "qib%d_%d",
589 dd->unit, pidx);
590 ppd->qib_wq = alloc_ordered_workqueue(wq_name,
591 WQ_MEM_RECLAIM);
592 if (!ppd->qib_wq)
593 goto wq_error;
594 }
595 }
596 return 0;
597 wq_error:
598 pr_err("create_singlethread_workqueue failed for port %d\n",
599 pidx + 1);
600 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
601 ppd = dd->pport + pidx;
602 if (ppd->qib_wq) {
603 destroy_workqueue(ppd->qib_wq);
604 ppd->qib_wq = NULL;
605 }
606 }
607 return -ENOMEM;
608 }
609
qib_free_pportdata(struct qib_pportdata * ppd)610 static void qib_free_pportdata(struct qib_pportdata *ppd)
611 {
612 free_percpu(ppd->ibport_data.pmastats);
613 free_percpu(ppd->ibport_data.rvp.rc_acks);
614 free_percpu(ppd->ibport_data.rvp.rc_qacks);
615 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
616 ppd->ibport_data.pmastats = NULL;
617 }
618
619 /**
620 * qib_init - do the actual initialization sequence on the chip
621 * @dd: the qlogic_ib device
622 * @reinit: reinitializing, so don't allocate new memory
623 *
624 * Do the actual initialization sequence on the chip. This is done
625 * both from the init routine called from the PCI infrastructure, and
626 * when we reset the chip, or detect that it was reset internally,
627 * or it's administratively re-enabled.
628 *
629 * Memory allocation here and in called routines is only done in
630 * the first case (reinit == 0). We have to be careful, because even
631 * without memory allocation, we need to re-write all the chip registers
632 * TIDs, etc. after the reset or enable has completed.
633 */
qib_init(struct qib_devdata * dd,int reinit)634 int qib_init(struct qib_devdata *dd, int reinit)
635 {
636 int ret = 0, pidx, lastfail = 0;
637 u32 portok = 0;
638 unsigned i;
639 struct qib_ctxtdata *rcd;
640 struct qib_pportdata *ppd;
641 unsigned long flags;
642
643 /* Set linkstate to unknown, so we can watch for a transition. */
644 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
645 ppd = dd->pport + pidx;
646 spin_lock_irqsave(&ppd->lflags_lock, flags);
647 ppd->lflags &= ~(QIBL_LINKACTIVE | QIBL_LINKARMED |
648 QIBL_LINKDOWN | QIBL_LINKINIT |
649 QIBL_LINKV);
650 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
651 }
652
653 if (reinit)
654 ret = init_after_reset(dd);
655 else
656 ret = loadtime_init(dd);
657 if (ret)
658 goto done;
659
660 /* Bypass most chip-init, to get to device creation */
661 if (qib_mini_init)
662 return 0;
663
664 ret = dd->f_late_initreg(dd);
665 if (ret)
666 goto done;
667
668 /* dd->rcd can be NULL if early init failed */
669 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
670 /*
671 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
672 * re-init, the simplest way to handle this is to free
673 * existing, and re-allocate.
674 * Need to re-create rest of ctxt 0 ctxtdata as well.
675 */
676 rcd = dd->rcd[i];
677 if (!rcd)
678 continue;
679
680 lastfail = qib_create_rcvhdrq(dd, rcd);
681 if (!lastfail)
682 lastfail = qib_setup_eagerbufs(rcd);
683 if (lastfail) {
684 qib_dev_err(dd,
685 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
686 continue;
687 }
688 }
689
690 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
691 int mtu;
692
693 if (lastfail)
694 ret = lastfail;
695 ppd = dd->pport + pidx;
696 mtu = ib_mtu_enum_to_int(qib_ibmtu);
697 if (mtu == -1) {
698 mtu = QIB_DEFAULT_MTU;
699 qib_ibmtu = 0; /* don't leave invalid value */
700 }
701 /* set max we can ever have for this driver load */
702 ppd->init_ibmaxlen = min(mtu > 2048 ?
703 dd->piosize4k : dd->piosize2k,
704 dd->rcvegrbufsize +
705 (dd->rcvhdrentsize << 2));
706 /*
707 * Have to initialize ibmaxlen, but this will normally
708 * change immediately in qib_set_mtu().
709 */
710 ppd->ibmaxlen = ppd->init_ibmaxlen;
711 qib_set_mtu(ppd, mtu);
712
713 spin_lock_irqsave(&ppd->lflags_lock, flags);
714 ppd->lflags |= QIBL_IB_LINK_DISABLED;
715 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
716
717 lastfail = dd->f_bringup_serdes(ppd);
718 if (lastfail) {
719 qib_devinfo(dd->pcidev,
720 "Failed to bringup IB port %u\n", ppd->port);
721 lastfail = -ENETDOWN;
722 continue;
723 }
724
725 portok++;
726 }
727
728 if (!portok) {
729 /* none of the ports initialized */
730 if (!ret && lastfail)
731 ret = lastfail;
732 else if (!ret)
733 ret = -ENETDOWN;
734 /* but continue on, so we can debug cause */
735 }
736
737 enable_chip(dd);
738
739 init_piobuf_state(dd);
740
741 done:
742 if (!ret) {
743 /* chip is OK for user apps; mark it as initialized */
744 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
745 ppd = dd->pport + pidx;
746 /*
747 * Set status even if port serdes is not initialized
748 * so that diags will work.
749 */
750 *ppd->statusp |= QIB_STATUS_CHIP_PRESENT |
751 QIB_STATUS_INITTED;
752 if (!ppd->link_speed_enabled)
753 continue;
754 if (dd->flags & QIB_HAS_SEND_DMA)
755 ret = qib_setup_sdma(ppd);
756 setup_timer(&ppd->hol_timer, qib_hol_event,
757 (unsigned long)ppd);
758 ppd->hol_state = QIB_HOL_UP;
759 }
760
761 /* now we can enable all interrupts from the chip */
762 dd->f_set_intr_state(dd, 1);
763
764 /*
765 * Setup to verify we get an interrupt, and fallback
766 * to an alternate if necessary and possible.
767 */
768 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
769 /* start stats retrieval timer */
770 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
771 }
772
773 /* if ret is non-zero, we probably should do some cleanup here... */
774 return ret;
775 }
776
777 /*
778 * These next two routines are placeholders in case we don't have per-arch
779 * code for controlling write combining. If explicit control of write
780 * combining is not available, performance will probably be awful.
781 */
782
qib_enable_wc(struct qib_devdata * dd)783 int __attribute__((weak)) qib_enable_wc(struct qib_devdata *dd)
784 {
785 return -EOPNOTSUPP;
786 }
787
qib_disable_wc(struct qib_devdata * dd)788 void __attribute__((weak)) qib_disable_wc(struct qib_devdata *dd)
789 {
790 }
791
__qib_lookup(int unit)792 static inline struct qib_devdata *__qib_lookup(int unit)
793 {
794 return idr_find(&qib_unit_table, unit);
795 }
796
qib_lookup(int unit)797 struct qib_devdata *qib_lookup(int unit)
798 {
799 struct qib_devdata *dd;
800 unsigned long flags;
801
802 spin_lock_irqsave(&qib_devs_lock, flags);
803 dd = __qib_lookup(unit);
804 spin_unlock_irqrestore(&qib_devs_lock, flags);
805
806 return dd;
807 }
808
809 /*
810 * Stop the timers during unit shutdown, or after an error late
811 * in initialization.
812 */
qib_stop_timers(struct qib_devdata * dd)813 static void qib_stop_timers(struct qib_devdata *dd)
814 {
815 struct qib_pportdata *ppd;
816 int pidx;
817
818 if (dd->stats_timer.data) {
819 del_timer_sync(&dd->stats_timer);
820 dd->stats_timer.data = 0;
821 }
822 if (dd->intrchk_timer.data) {
823 del_timer_sync(&dd->intrchk_timer);
824 dd->intrchk_timer.data = 0;
825 }
826 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
827 ppd = dd->pport + pidx;
828 if (ppd->hol_timer.data)
829 del_timer_sync(&ppd->hol_timer);
830 if (ppd->led_override_timer.data) {
831 del_timer_sync(&ppd->led_override_timer);
832 atomic_set(&ppd->led_override_timer_active, 0);
833 }
834 if (ppd->symerr_clear_timer.data)
835 del_timer_sync(&ppd->symerr_clear_timer);
836 }
837 }
838
839 /**
840 * qib_shutdown_device - shut down a device
841 * @dd: the qlogic_ib device
842 *
843 * This is called to make the device quiet when we are about to
844 * unload the driver, and also when the device is administratively
845 * disabled. It does not free any data structures.
846 * Everything it does has to be setup again by qib_init(dd, 1)
847 */
qib_shutdown_device(struct qib_devdata * dd)848 static void qib_shutdown_device(struct qib_devdata *dd)
849 {
850 struct qib_pportdata *ppd;
851 unsigned pidx;
852
853 if (dd->flags & QIB_SHUTDOWN)
854 return;
855 dd->flags |= QIB_SHUTDOWN;
856
857 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
858 ppd = dd->pport + pidx;
859
860 spin_lock_irq(&ppd->lflags_lock);
861 ppd->lflags &= ~(QIBL_LINKDOWN | QIBL_LINKINIT |
862 QIBL_LINKARMED | QIBL_LINKACTIVE |
863 QIBL_LINKV);
864 spin_unlock_irq(&ppd->lflags_lock);
865 *ppd->statusp &= ~(QIB_STATUS_IB_CONF | QIB_STATUS_IB_READY);
866 }
867 dd->flags &= ~QIB_INITTED;
868
869 /* mask interrupts, but not errors */
870 dd->f_set_intr_state(dd, 0);
871
872 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
873 ppd = dd->pport + pidx;
874 dd->f_rcvctrl(ppd, QIB_RCVCTRL_TAILUPD_DIS |
875 QIB_RCVCTRL_CTXT_DIS |
876 QIB_RCVCTRL_INTRAVAIL_DIS |
877 QIB_RCVCTRL_PKEY_ENB, -1);
878 /*
879 * Gracefully stop all sends allowing any in progress to
880 * trickle out first.
881 */
882 dd->f_sendctrl(ppd, QIB_SENDCTRL_CLEAR);
883 }
884
885 /*
886 * Enough for anything that's going to trickle out to have actually
887 * done so.
888 */
889 udelay(20);
890
891 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
892 ppd = dd->pport + pidx;
893 dd->f_setextled(ppd, 0); /* make sure LEDs are off */
894
895 if (dd->flags & QIB_HAS_SEND_DMA)
896 qib_teardown_sdma(ppd);
897
898 dd->f_sendctrl(ppd, QIB_SENDCTRL_AVAIL_DIS |
899 QIB_SENDCTRL_SEND_DIS);
900 /*
901 * Clear SerdesEnable.
902 * We can't count on interrupts since we are stopping.
903 */
904 dd->f_quiet_serdes(ppd);
905
906 if (ppd->qib_wq) {
907 destroy_workqueue(ppd->qib_wq);
908 ppd->qib_wq = NULL;
909 }
910 qib_free_pportdata(ppd);
911 }
912
913 }
914
915 /**
916 * qib_free_ctxtdata - free a context's allocated data
917 * @dd: the qlogic_ib device
918 * @rcd: the ctxtdata structure
919 *
920 * free up any allocated data for a context
921 * This should not touch anything that would affect a simultaneous
922 * re-allocation of context data, because it is called after qib_mutex
923 * is released (and can be called from reinit as well).
924 * It should never change any chip state, or global driver state.
925 */
qib_free_ctxtdata(struct qib_devdata * dd,struct qib_ctxtdata * rcd)926 void qib_free_ctxtdata(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
927 {
928 if (!rcd)
929 return;
930
931 if (rcd->rcvhdrq) {
932 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
933 rcd->rcvhdrq, rcd->rcvhdrq_phys);
934 rcd->rcvhdrq = NULL;
935 if (rcd->rcvhdrtail_kvaddr) {
936 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
937 rcd->rcvhdrtail_kvaddr,
938 rcd->rcvhdrqtailaddr_phys);
939 rcd->rcvhdrtail_kvaddr = NULL;
940 }
941 }
942 if (rcd->rcvegrbuf) {
943 unsigned e;
944
945 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
946 void *base = rcd->rcvegrbuf[e];
947 size_t size = rcd->rcvegrbuf_size;
948
949 dma_free_coherent(&dd->pcidev->dev, size,
950 base, rcd->rcvegrbuf_phys[e]);
951 }
952 kfree(rcd->rcvegrbuf);
953 rcd->rcvegrbuf = NULL;
954 kfree(rcd->rcvegrbuf_phys);
955 rcd->rcvegrbuf_phys = NULL;
956 rcd->rcvegrbuf_chunks = 0;
957 }
958
959 kfree(rcd->tid_pg_list);
960 vfree(rcd->user_event_mask);
961 vfree(rcd->subctxt_uregbase);
962 vfree(rcd->subctxt_rcvegrbuf);
963 vfree(rcd->subctxt_rcvhdr_base);
964 #ifdef CONFIG_DEBUG_FS
965 kfree(rcd->opstats);
966 rcd->opstats = NULL;
967 #endif
968 kfree(rcd);
969 }
970
971 /*
972 * Perform a PIO buffer bandwidth write test, to verify proper system
973 * configuration. Even when all the setup calls work, occasionally
974 * BIOS or other issues can prevent write combining from working, or
975 * can cause other bandwidth problems to the chip.
976 *
977 * This test simply writes the same buffer over and over again, and
978 * measures close to the peak bandwidth to the chip (not testing
979 * data bandwidth to the wire). On chips that use an address-based
980 * trigger to send packets to the wire, this is easy. On chips that
981 * use a count to trigger, we want to make sure that the packet doesn't
982 * go out on the wire, or trigger flow control checks.
983 */
qib_verify_pioperf(struct qib_devdata * dd)984 static void qib_verify_pioperf(struct qib_devdata *dd)
985 {
986 u32 pbnum, cnt, lcnt;
987 u32 __iomem *piobuf;
988 u32 *addr;
989 u64 msecs, emsecs;
990
991 piobuf = dd->f_getsendbuf(dd->pport, 0ULL, &pbnum);
992 if (!piobuf) {
993 qib_devinfo(dd->pcidev,
994 "No PIObufs for checking perf, skipping\n");
995 return;
996 }
997
998 /*
999 * Enough to give us a reasonable test, less than piobuf size, and
1000 * likely multiple of store buffer length.
1001 */
1002 cnt = 1024;
1003
1004 addr = vmalloc(cnt);
1005 if (!addr)
1006 goto done;
1007
1008 preempt_disable(); /* we want reasonably accurate elapsed time */
1009 msecs = 1 + jiffies_to_msecs(jiffies);
1010 for (lcnt = 0; lcnt < 10000U; lcnt++) {
1011 /* wait until we cross msec boundary */
1012 if (jiffies_to_msecs(jiffies) >= msecs)
1013 break;
1014 udelay(1);
1015 }
1016
1017 dd->f_set_armlaunch(dd, 0);
1018
1019 /*
1020 * length 0, no dwords actually sent
1021 */
1022 writeq(0, piobuf);
1023 qib_flush_wc();
1024
1025 /*
1026 * This is only roughly accurate, since even with preempt we
1027 * still take interrupts that could take a while. Running for
1028 * >= 5 msec seems to get us "close enough" to accurate values.
1029 */
1030 msecs = jiffies_to_msecs(jiffies);
1031 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
1032 qib_pio_copy(piobuf + 64, addr, cnt >> 2);
1033 emsecs = jiffies_to_msecs(jiffies) - msecs;
1034 }
1035
1036 /* 1 GiB/sec, slightly over IB SDR line rate */
1037 if (lcnt < (emsecs * 1024U))
1038 qib_dev_err(dd,
1039 "Performance problem: bandwidth to PIO buffers is only %u MiB/sec\n",
1040 lcnt / (u32) emsecs);
1041
1042 preempt_enable();
1043
1044 vfree(addr);
1045
1046 done:
1047 /* disarm piobuf, so it's available again */
1048 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbnum));
1049 qib_sendbuf_done(dd, pbnum);
1050 dd->f_set_armlaunch(dd, 1);
1051 }
1052
qib_free_devdata(struct qib_devdata * dd)1053 void qib_free_devdata(struct qib_devdata *dd)
1054 {
1055 unsigned long flags;
1056
1057 spin_lock_irqsave(&qib_devs_lock, flags);
1058 idr_remove(&qib_unit_table, dd->unit);
1059 list_del(&dd->list);
1060 spin_unlock_irqrestore(&qib_devs_lock, flags);
1061
1062 #ifdef CONFIG_DEBUG_FS
1063 qib_dbg_ibdev_exit(&dd->verbs_dev);
1064 #endif
1065 free_percpu(dd->int_counter);
1066 rvt_dealloc_device(&dd->verbs_dev.rdi);
1067 }
1068
qib_int_counter(struct qib_devdata * dd)1069 u64 qib_int_counter(struct qib_devdata *dd)
1070 {
1071 int cpu;
1072 u64 int_counter = 0;
1073
1074 for_each_possible_cpu(cpu)
1075 int_counter += *per_cpu_ptr(dd->int_counter, cpu);
1076 return int_counter;
1077 }
1078
qib_sps_ints(void)1079 u64 qib_sps_ints(void)
1080 {
1081 unsigned long flags;
1082 struct qib_devdata *dd;
1083 u64 sps_ints = 0;
1084
1085 spin_lock_irqsave(&qib_devs_lock, flags);
1086 list_for_each_entry(dd, &qib_dev_list, list) {
1087 sps_ints += qib_int_counter(dd);
1088 }
1089 spin_unlock_irqrestore(&qib_devs_lock, flags);
1090 return sps_ints;
1091 }
1092
1093 /*
1094 * Allocate our primary per-unit data structure. Must be done via verbs
1095 * allocator, because the verbs cleanup process both does cleanup and
1096 * free of the data structure.
1097 * "extra" is for chip-specific data.
1098 *
1099 * Use the idr mechanism to get a unit number for this unit.
1100 */
qib_alloc_devdata(struct pci_dev * pdev,size_t extra)1101 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra)
1102 {
1103 unsigned long flags;
1104 struct qib_devdata *dd;
1105 int ret, nports;
1106
1107 /* extra is * number of ports */
1108 nports = extra / sizeof(struct qib_pportdata);
1109 dd = (struct qib_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1110 nports);
1111 if (!dd)
1112 return ERR_PTR(-ENOMEM);
1113
1114 INIT_LIST_HEAD(&dd->list);
1115
1116 idr_preload(GFP_KERNEL);
1117 spin_lock_irqsave(&qib_devs_lock, flags);
1118
1119 ret = idr_alloc(&qib_unit_table, dd, 0, 0, GFP_NOWAIT);
1120 if (ret >= 0) {
1121 dd->unit = ret;
1122 list_add(&dd->list, &qib_dev_list);
1123 }
1124
1125 spin_unlock_irqrestore(&qib_devs_lock, flags);
1126 idr_preload_end();
1127
1128 if (ret < 0) {
1129 qib_early_err(&pdev->dev,
1130 "Could not allocate unit ID: error %d\n", -ret);
1131 goto bail;
1132 }
1133 dd->int_counter = alloc_percpu(u64);
1134 if (!dd->int_counter) {
1135 ret = -ENOMEM;
1136 qib_early_err(&pdev->dev,
1137 "Could not allocate per-cpu int_counter\n");
1138 goto bail;
1139 }
1140
1141 if (!qib_cpulist_count) {
1142 u32 count = num_online_cpus();
1143
1144 qib_cpulist = kzalloc(BITS_TO_LONGS(count) *
1145 sizeof(long), GFP_KERNEL);
1146 if (qib_cpulist)
1147 qib_cpulist_count = count;
1148 }
1149 #ifdef CONFIG_DEBUG_FS
1150 qib_dbg_ibdev_init(&dd->verbs_dev);
1151 #endif
1152 return dd;
1153 bail:
1154 if (!list_empty(&dd->list))
1155 list_del_init(&dd->list);
1156 rvt_dealloc_device(&dd->verbs_dev.rdi);
1157 return ERR_PTR(ret);
1158 }
1159
1160 /*
1161 * Called from freeze mode handlers, and from PCI error
1162 * reporting code. Should be paranoid about state of
1163 * system and data structures.
1164 */
qib_disable_after_error(struct qib_devdata * dd)1165 void qib_disable_after_error(struct qib_devdata *dd)
1166 {
1167 if (dd->flags & QIB_INITTED) {
1168 u32 pidx;
1169
1170 dd->flags &= ~QIB_INITTED;
1171 if (dd->pport)
1172 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1173 struct qib_pportdata *ppd;
1174
1175 ppd = dd->pport + pidx;
1176 if (dd->flags & QIB_PRESENT) {
1177 qib_set_linkstate(ppd,
1178 QIB_IB_LINKDOWN_DISABLE);
1179 dd->f_setextled(ppd, 0);
1180 }
1181 *ppd->statusp &= ~QIB_STATUS_IB_READY;
1182 }
1183 }
1184
1185 /*
1186 * Mark as having had an error for driver, and also
1187 * for /sys and status word mapped to user programs.
1188 * This marks unit as not usable, until reset.
1189 */
1190 if (dd->devstatusp)
1191 *dd->devstatusp |= QIB_STATUS_HWERROR;
1192 }
1193
1194 static void qib_remove_one(struct pci_dev *);
1195 static int qib_init_one(struct pci_dev *, const struct pci_device_id *);
1196 static void qib_shutdown_one(struct pci_dev *);
1197
1198 #define DRIVER_LOAD_MSG "Intel " QIB_DRV_NAME " loaded: "
1199 #define PFX QIB_DRV_NAME ": "
1200
1201 static const struct pci_device_id qib_pci_tbl[] = {
1202 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_QLOGIC_IB_6120) },
1203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7220) },
1204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7322) },
1205 { 0, }
1206 };
1207
1208 MODULE_DEVICE_TABLE(pci, qib_pci_tbl);
1209
1210 static struct pci_driver qib_driver = {
1211 .name = QIB_DRV_NAME,
1212 .probe = qib_init_one,
1213 .remove = qib_remove_one,
1214 .shutdown = qib_shutdown_one,
1215 .id_table = qib_pci_tbl,
1216 .err_handler = &qib_pci_err_handler,
1217 };
1218
1219 #ifdef CONFIG_INFINIBAND_QIB_DCA
1220
1221 static int qib_notify_dca(struct notifier_block *, unsigned long, void *);
1222 static struct notifier_block dca_notifier = {
1223 .notifier_call = qib_notify_dca,
1224 .next = NULL,
1225 .priority = 0
1226 };
1227
qib_notify_dca_device(struct device * device,void * data)1228 static int qib_notify_dca_device(struct device *device, void *data)
1229 {
1230 struct qib_devdata *dd = dev_get_drvdata(device);
1231 unsigned long event = *(unsigned long *)data;
1232
1233 return dd->f_notify_dca(dd, event);
1234 }
1235
qib_notify_dca(struct notifier_block * nb,unsigned long event,void * p)1236 static int qib_notify_dca(struct notifier_block *nb, unsigned long event,
1237 void *p)
1238 {
1239 int rval;
1240
1241 rval = driver_for_each_device(&qib_driver.driver, NULL,
1242 &event, qib_notify_dca_device);
1243 return rval ? NOTIFY_BAD : NOTIFY_DONE;
1244 }
1245
1246 #endif
1247
1248 /*
1249 * Do all the generic driver unit- and chip-independent memory
1250 * allocation and initialization.
1251 */
qib_ib_init(void)1252 static int __init qib_ib_init(void)
1253 {
1254 int ret;
1255
1256 ret = qib_dev_init();
1257 if (ret)
1258 goto bail;
1259
1260 /*
1261 * These must be called before the driver is registered with
1262 * the PCI subsystem.
1263 */
1264 idr_init(&qib_unit_table);
1265
1266 #ifdef CONFIG_INFINIBAND_QIB_DCA
1267 dca_register_notify(&dca_notifier);
1268 #endif
1269 #ifdef CONFIG_DEBUG_FS
1270 qib_dbg_init();
1271 #endif
1272 ret = pci_register_driver(&qib_driver);
1273 if (ret < 0) {
1274 pr_err("Unable to register driver: error %d\n", -ret);
1275 goto bail_dev;
1276 }
1277
1278 /* not fatal if it doesn't work */
1279 if (qib_init_qibfs())
1280 pr_err("Unable to register ipathfs\n");
1281 goto bail; /* all OK */
1282
1283 bail_dev:
1284 #ifdef CONFIG_INFINIBAND_QIB_DCA
1285 dca_unregister_notify(&dca_notifier);
1286 #endif
1287 #ifdef CONFIG_DEBUG_FS
1288 qib_dbg_exit();
1289 #endif
1290 idr_destroy(&qib_unit_table);
1291 qib_dev_cleanup();
1292 bail:
1293 return ret;
1294 }
1295
1296 module_init(qib_ib_init);
1297
1298 /*
1299 * Do the non-unit driver cleanup, memory free, etc. at unload.
1300 */
qib_ib_cleanup(void)1301 static void __exit qib_ib_cleanup(void)
1302 {
1303 int ret;
1304
1305 ret = qib_exit_qibfs();
1306 if (ret)
1307 pr_err(
1308 "Unable to cleanup counter filesystem: error %d\n",
1309 -ret);
1310
1311 #ifdef CONFIG_INFINIBAND_QIB_DCA
1312 dca_unregister_notify(&dca_notifier);
1313 #endif
1314 pci_unregister_driver(&qib_driver);
1315 #ifdef CONFIG_DEBUG_FS
1316 qib_dbg_exit();
1317 #endif
1318
1319 qib_cpulist_count = 0;
1320 kfree(qib_cpulist);
1321
1322 idr_destroy(&qib_unit_table);
1323 qib_dev_cleanup();
1324 }
1325
1326 module_exit(qib_ib_cleanup);
1327
1328 /* this can only be called after a successful initialization */
cleanup_device_data(struct qib_devdata * dd)1329 static void cleanup_device_data(struct qib_devdata *dd)
1330 {
1331 int ctxt;
1332 int pidx;
1333 struct qib_ctxtdata **tmp;
1334 unsigned long flags;
1335
1336 /* users can't do anything more with chip */
1337 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1338 if (dd->pport[pidx].statusp)
1339 *dd->pport[pidx].statusp &= ~QIB_STATUS_CHIP_PRESENT;
1340
1341 spin_lock(&dd->pport[pidx].cc_shadow_lock);
1342
1343 kfree(dd->pport[pidx].congestion_entries);
1344 dd->pport[pidx].congestion_entries = NULL;
1345 kfree(dd->pport[pidx].ccti_entries);
1346 dd->pport[pidx].ccti_entries = NULL;
1347 kfree(dd->pport[pidx].ccti_entries_shadow);
1348 dd->pport[pidx].ccti_entries_shadow = NULL;
1349 kfree(dd->pport[pidx].congestion_entries_shadow);
1350 dd->pport[pidx].congestion_entries_shadow = NULL;
1351
1352 spin_unlock(&dd->pport[pidx].cc_shadow_lock);
1353 }
1354
1355 qib_disable_wc(dd);
1356
1357 if (dd->pioavailregs_dma) {
1358 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1359 (void *) dd->pioavailregs_dma,
1360 dd->pioavailregs_phys);
1361 dd->pioavailregs_dma = NULL;
1362 }
1363
1364 if (dd->pageshadow) {
1365 struct page **tmpp = dd->pageshadow;
1366 dma_addr_t *tmpd = dd->physshadow;
1367 int i;
1368
1369 for (ctxt = 0; ctxt < dd->cfgctxts; ctxt++) {
1370 int ctxt_tidbase = ctxt * dd->rcvtidcnt;
1371 int maxtid = ctxt_tidbase + dd->rcvtidcnt;
1372
1373 for (i = ctxt_tidbase; i < maxtid; i++) {
1374 if (!tmpp[i])
1375 continue;
1376 pci_unmap_page(dd->pcidev, tmpd[i],
1377 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1378 qib_release_user_pages(&tmpp[i], 1);
1379 tmpp[i] = NULL;
1380 }
1381 }
1382
1383 dd->pageshadow = NULL;
1384 vfree(tmpp);
1385 dd->physshadow = NULL;
1386 vfree(tmpd);
1387 }
1388
1389 /*
1390 * Free any resources still in use (usually just kernel contexts)
1391 * at unload; we do for ctxtcnt, because that's what we allocate.
1392 * We acquire lock to be really paranoid that rcd isn't being
1393 * accessed from some interrupt-related code (that should not happen,
1394 * but best to be sure).
1395 */
1396 spin_lock_irqsave(&dd->uctxt_lock, flags);
1397 tmp = dd->rcd;
1398 dd->rcd = NULL;
1399 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1400 for (ctxt = 0; tmp && ctxt < dd->ctxtcnt; ctxt++) {
1401 struct qib_ctxtdata *rcd = tmp[ctxt];
1402
1403 tmp[ctxt] = NULL; /* debugging paranoia */
1404 qib_free_ctxtdata(dd, rcd);
1405 }
1406 kfree(tmp);
1407 }
1408
1409 /*
1410 * Clean up on unit shutdown, or error during unit load after
1411 * successful initialization.
1412 */
qib_postinit_cleanup(struct qib_devdata * dd)1413 static void qib_postinit_cleanup(struct qib_devdata *dd)
1414 {
1415 /*
1416 * Clean up chip-specific stuff.
1417 * We check for NULL here, because it's outside
1418 * the kregbase check, and we need to call it
1419 * after the free_irq. Thus it's possible that
1420 * the function pointers were never initialized.
1421 */
1422 if (dd->f_cleanup)
1423 dd->f_cleanup(dd);
1424
1425 qib_pcie_ddcleanup(dd);
1426
1427 cleanup_device_data(dd);
1428
1429 qib_free_devdata(dd);
1430 }
1431
qib_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1432 static int qib_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1433 {
1434 int ret, j, pidx, initfail;
1435 struct qib_devdata *dd = NULL;
1436
1437 ret = qib_pcie_init(pdev, ent);
1438 if (ret)
1439 goto bail;
1440
1441 /*
1442 * Do device-specific initialiation, function table setup, dd
1443 * allocation, etc.
1444 */
1445 switch (ent->device) {
1446 case PCI_DEVICE_ID_QLOGIC_IB_6120:
1447 #ifdef CONFIG_PCI_MSI
1448 dd = qib_init_iba6120_funcs(pdev, ent);
1449 #else
1450 qib_early_err(&pdev->dev,
1451 "Intel PCIE device 0x%x cannot work if CONFIG_PCI_MSI is not enabled\n",
1452 ent->device);
1453 dd = ERR_PTR(-ENODEV);
1454 #endif
1455 break;
1456
1457 case PCI_DEVICE_ID_QLOGIC_IB_7220:
1458 dd = qib_init_iba7220_funcs(pdev, ent);
1459 break;
1460
1461 case PCI_DEVICE_ID_QLOGIC_IB_7322:
1462 dd = qib_init_iba7322_funcs(pdev, ent);
1463 break;
1464
1465 default:
1466 qib_early_err(&pdev->dev,
1467 "Failing on unknown Intel deviceid 0x%x\n",
1468 ent->device);
1469 ret = -ENODEV;
1470 }
1471
1472 if (IS_ERR(dd))
1473 ret = PTR_ERR(dd);
1474 if (ret)
1475 goto bail; /* error already printed */
1476
1477 ret = qib_create_workqueues(dd);
1478 if (ret)
1479 goto bail;
1480
1481 /* do the generic initialization */
1482 initfail = qib_init(dd, 0);
1483
1484 ret = qib_register_ib_device(dd);
1485
1486 /*
1487 * Now ready for use. this should be cleared whenever we
1488 * detect a reset, or initiate one. If earlier failure,
1489 * we still create devices, so diags, etc. can be used
1490 * to determine cause of problem.
1491 */
1492 if (!qib_mini_init && !initfail && !ret)
1493 dd->flags |= QIB_INITTED;
1494
1495 j = qib_device_create(dd);
1496 if (j)
1497 qib_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1498 j = qibfs_add(dd);
1499 if (j)
1500 qib_dev_err(dd, "Failed filesystem setup for counters: %d\n",
1501 -j);
1502
1503 if (qib_mini_init || initfail || ret) {
1504 qib_stop_timers(dd);
1505 flush_workqueue(ib_wq);
1506 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1507 dd->f_quiet_serdes(dd->pport + pidx);
1508 if (qib_mini_init)
1509 goto bail;
1510 if (!j) {
1511 (void) qibfs_remove(dd);
1512 qib_device_remove(dd);
1513 }
1514 if (!ret)
1515 qib_unregister_ib_device(dd);
1516 qib_postinit_cleanup(dd);
1517 if (initfail)
1518 ret = initfail;
1519 goto bail;
1520 }
1521
1522 ret = qib_enable_wc(dd);
1523 if (ret) {
1524 qib_dev_err(dd,
1525 "Write combining not enabled (err %d): performance may be poor\n",
1526 -ret);
1527 ret = 0;
1528 }
1529
1530 qib_verify_pioperf(dd);
1531 bail:
1532 return ret;
1533 }
1534
qib_remove_one(struct pci_dev * pdev)1535 static void qib_remove_one(struct pci_dev *pdev)
1536 {
1537 struct qib_devdata *dd = pci_get_drvdata(pdev);
1538 int ret;
1539
1540 /* unregister from IB core */
1541 qib_unregister_ib_device(dd);
1542
1543 /*
1544 * Disable the IB link, disable interrupts on the device,
1545 * clear dma engines, etc.
1546 */
1547 if (!qib_mini_init)
1548 qib_shutdown_device(dd);
1549
1550 qib_stop_timers(dd);
1551
1552 /* wait until all of our (qsfp) queue_work() calls complete */
1553 flush_workqueue(ib_wq);
1554
1555 ret = qibfs_remove(dd);
1556 if (ret)
1557 qib_dev_err(dd, "Failed counters filesystem cleanup: %d\n",
1558 -ret);
1559
1560 qib_device_remove(dd);
1561
1562 qib_postinit_cleanup(dd);
1563 }
1564
qib_shutdown_one(struct pci_dev * pdev)1565 static void qib_shutdown_one(struct pci_dev *pdev)
1566 {
1567 struct qib_devdata *dd = pci_get_drvdata(pdev);
1568
1569 qib_shutdown_device(dd);
1570 }
1571
1572 /**
1573 * qib_create_rcvhdrq - create a receive header queue
1574 * @dd: the qlogic_ib device
1575 * @rcd: the context data
1576 *
1577 * This must be contiguous memory (from an i/o perspective), and must be
1578 * DMA'able (which means for some systems, it will go through an IOMMU,
1579 * or be forced into a low address range).
1580 */
qib_create_rcvhdrq(struct qib_devdata * dd,struct qib_ctxtdata * rcd)1581 int qib_create_rcvhdrq(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
1582 {
1583 unsigned amt;
1584 int old_node_id;
1585
1586 if (!rcd->rcvhdrq) {
1587 dma_addr_t phys_hdrqtail;
1588 gfp_t gfp_flags;
1589
1590 amt = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize *
1591 sizeof(u32), PAGE_SIZE);
1592 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1593 GFP_USER : GFP_KERNEL;
1594
1595 old_node_id = dev_to_node(&dd->pcidev->dev);
1596 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1597 rcd->rcvhdrq = dma_alloc_coherent(
1598 &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1599 gfp_flags | __GFP_COMP);
1600 set_dev_node(&dd->pcidev->dev, old_node_id);
1601
1602 if (!rcd->rcvhdrq) {
1603 qib_dev_err(dd,
1604 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1605 amt, rcd->ctxt);
1606 goto bail;
1607 }
1608
1609 if (rcd->ctxt >= dd->first_user_ctxt) {
1610 rcd->user_event_mask = vmalloc_user(PAGE_SIZE);
1611 if (!rcd->user_event_mask)
1612 goto bail_free_hdrq;
1613 }
1614
1615 if (!(dd->flags & QIB_NODMA_RTAIL)) {
1616 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1617 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(
1618 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1619 gfp_flags);
1620 set_dev_node(&dd->pcidev->dev, old_node_id);
1621 if (!rcd->rcvhdrtail_kvaddr)
1622 goto bail_free;
1623 rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1624 }
1625
1626 rcd->rcvhdrq_size = amt;
1627 }
1628
1629 /* clear for security and sanity on each use */
1630 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
1631 if (rcd->rcvhdrtail_kvaddr)
1632 memset(rcd->rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1633 return 0;
1634
1635 bail_free:
1636 qib_dev_err(dd,
1637 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1638 rcd->ctxt);
1639 vfree(rcd->user_event_mask);
1640 rcd->user_event_mask = NULL;
1641 bail_free_hdrq:
1642 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1643 rcd->rcvhdrq_phys);
1644 rcd->rcvhdrq = NULL;
1645 bail:
1646 return -ENOMEM;
1647 }
1648
1649 /**
1650 * allocate eager buffers, both kernel and user contexts.
1651 * @rcd: the context we are setting up.
1652 *
1653 * Allocate the eager TID buffers and program them into hip.
1654 * They are no longer completely contiguous, we do multiple allocation
1655 * calls. Otherwise we get the OOM code involved, by asking for too
1656 * much per call, with disastrous results on some kernels.
1657 */
qib_setup_eagerbufs(struct qib_ctxtdata * rcd)1658 int qib_setup_eagerbufs(struct qib_ctxtdata *rcd)
1659 {
1660 struct qib_devdata *dd = rcd->dd;
1661 unsigned e, egrcnt, egrperchunk, chunk, egrsize, egroff;
1662 size_t size;
1663 gfp_t gfp_flags;
1664 int old_node_id;
1665
1666 /*
1667 * GFP_USER, but without GFP_FS, so buffer cache can be
1668 * coalesced (we hope); otherwise, even at order 4,
1669 * heavy filesystem activity makes these fail, and we can
1670 * use compound pages.
1671 */
1672 gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1673
1674 egrcnt = rcd->rcvegrcnt;
1675 egroff = rcd->rcvegr_tid_base;
1676 egrsize = dd->rcvegrbufsize;
1677
1678 chunk = rcd->rcvegrbuf_chunks;
1679 egrperchunk = rcd->rcvegrbufs_perchunk;
1680 size = rcd->rcvegrbuf_size;
1681 if (!rcd->rcvegrbuf) {
1682 rcd->rcvegrbuf =
1683 kzalloc_node(chunk * sizeof(rcd->rcvegrbuf[0]),
1684 GFP_KERNEL, rcd->node_id);
1685 if (!rcd->rcvegrbuf)
1686 goto bail;
1687 }
1688 if (!rcd->rcvegrbuf_phys) {
1689 rcd->rcvegrbuf_phys =
1690 kmalloc_node(chunk * sizeof(rcd->rcvegrbuf_phys[0]),
1691 GFP_KERNEL, rcd->node_id);
1692 if (!rcd->rcvegrbuf_phys)
1693 goto bail_rcvegrbuf;
1694 }
1695 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
1696 if (rcd->rcvegrbuf[e])
1697 continue;
1698
1699 old_node_id = dev_to_node(&dd->pcidev->dev);
1700 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1701 rcd->rcvegrbuf[e] =
1702 dma_alloc_coherent(&dd->pcidev->dev, size,
1703 &rcd->rcvegrbuf_phys[e],
1704 gfp_flags);
1705 set_dev_node(&dd->pcidev->dev, old_node_id);
1706 if (!rcd->rcvegrbuf[e])
1707 goto bail_rcvegrbuf_phys;
1708 }
1709
1710 rcd->rcvegr_phys = rcd->rcvegrbuf_phys[0];
1711
1712 for (e = chunk = 0; chunk < rcd->rcvegrbuf_chunks; chunk++) {
1713 dma_addr_t pa = rcd->rcvegrbuf_phys[chunk];
1714 unsigned i;
1715
1716 /* clear for security and sanity on each use */
1717 memset(rcd->rcvegrbuf[chunk], 0, size);
1718
1719 for (i = 0; e < egrcnt && i < egrperchunk; e++, i++) {
1720 dd->f_put_tid(dd, e + egroff +
1721 (u64 __iomem *)
1722 ((char __iomem *)
1723 dd->kregbase +
1724 dd->rcvegrbase),
1725 RCVHQ_RCV_TYPE_EAGER, pa);
1726 pa += egrsize;
1727 }
1728 cond_resched(); /* don't hog the cpu */
1729 }
1730
1731 return 0;
1732
1733 bail_rcvegrbuf_phys:
1734 for (e = 0; e < rcd->rcvegrbuf_chunks && rcd->rcvegrbuf[e]; e++)
1735 dma_free_coherent(&dd->pcidev->dev, size,
1736 rcd->rcvegrbuf[e], rcd->rcvegrbuf_phys[e]);
1737 kfree(rcd->rcvegrbuf_phys);
1738 rcd->rcvegrbuf_phys = NULL;
1739 bail_rcvegrbuf:
1740 kfree(rcd->rcvegrbuf);
1741 rcd->rcvegrbuf = NULL;
1742 bail:
1743 return -ENOMEM;
1744 }
1745
1746 /*
1747 * Note: Changes to this routine should be mirrored
1748 * for the diagnostics routine qib_remap_ioaddr32().
1749 * There is also related code for VL15 buffers in qib_init_7322_variables().
1750 * The teardown code that unmaps is in qib_pcie_ddcleanup()
1751 */
init_chip_wc_pat(struct qib_devdata * dd,u32 vl15buflen)1752 int init_chip_wc_pat(struct qib_devdata *dd, u32 vl15buflen)
1753 {
1754 u64 __iomem *qib_kregbase = NULL;
1755 void __iomem *qib_piobase = NULL;
1756 u64 __iomem *qib_userbase = NULL;
1757 u64 qib_kreglen;
1758 u64 qib_pio2koffset = dd->piobufbase & 0xffffffff;
1759 u64 qib_pio4koffset = dd->piobufbase >> 32;
1760 u64 qib_pio2klen = dd->piobcnt2k * dd->palign;
1761 u64 qib_pio4klen = dd->piobcnt4k * dd->align4k;
1762 u64 qib_physaddr = dd->physaddr;
1763 u64 qib_piolen;
1764 u64 qib_userlen = 0;
1765
1766 /*
1767 * Free the old mapping because the kernel will try to reuse the
1768 * old mapping and not create a new mapping with the
1769 * write combining attribute.
1770 */
1771 iounmap(dd->kregbase);
1772 dd->kregbase = NULL;
1773
1774 /*
1775 * Assumes chip address space looks like:
1776 * - kregs + sregs + cregs + uregs (in any order)
1777 * - piobufs (2K and 4K bufs in either order)
1778 * or:
1779 * - kregs + sregs + cregs (in any order)
1780 * - piobufs (2K and 4K bufs in either order)
1781 * - uregs
1782 */
1783 if (dd->piobcnt4k == 0) {
1784 qib_kreglen = qib_pio2koffset;
1785 qib_piolen = qib_pio2klen;
1786 } else if (qib_pio2koffset < qib_pio4koffset) {
1787 qib_kreglen = qib_pio2koffset;
1788 qib_piolen = qib_pio4koffset + qib_pio4klen - qib_kreglen;
1789 } else {
1790 qib_kreglen = qib_pio4koffset;
1791 qib_piolen = qib_pio2koffset + qib_pio2klen - qib_kreglen;
1792 }
1793 qib_piolen += vl15buflen;
1794 /* Map just the configured ports (not all hw ports) */
1795 if (dd->uregbase > qib_kreglen)
1796 qib_userlen = dd->ureg_align * dd->cfgctxts;
1797
1798 /* Sanity checks passed, now create the new mappings */
1799 qib_kregbase = ioremap_nocache(qib_physaddr, qib_kreglen);
1800 if (!qib_kregbase)
1801 goto bail;
1802
1803 qib_piobase = ioremap_wc(qib_physaddr + qib_kreglen, qib_piolen);
1804 if (!qib_piobase)
1805 goto bail_kregbase;
1806
1807 if (qib_userlen) {
1808 qib_userbase = ioremap_nocache(qib_physaddr + dd->uregbase,
1809 qib_userlen);
1810 if (!qib_userbase)
1811 goto bail_piobase;
1812 }
1813
1814 dd->kregbase = qib_kregbase;
1815 dd->kregend = (u64 __iomem *)
1816 ((char __iomem *) qib_kregbase + qib_kreglen);
1817 dd->piobase = qib_piobase;
1818 dd->pio2kbase = (void __iomem *)
1819 (((char __iomem *) dd->piobase) +
1820 qib_pio2koffset - qib_kreglen);
1821 if (dd->piobcnt4k)
1822 dd->pio4kbase = (void __iomem *)
1823 (((char __iomem *) dd->piobase) +
1824 qib_pio4koffset - qib_kreglen);
1825 if (qib_userlen)
1826 /* ureg will now be accessed relative to dd->userbase */
1827 dd->userbase = qib_userbase;
1828 return 0;
1829
1830 bail_piobase:
1831 iounmap(qib_piobase);
1832 bail_kregbase:
1833 iounmap(qib_kregbase);
1834 bail:
1835 return -ENOMEM;
1836 }
1837