1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_edid.h>
37
38 #include <linux/gcd.h>
39
avivo_crtc_load_lut(struct drm_crtc * crtc)40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41 {
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
45 u16 *r, *g, *b;
46 int i;
47
48 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
49 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
50
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
53 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
54
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
57 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
58
59 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
60 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
61 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
62
63 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
64 r = crtc->gamma_store;
65 g = r + crtc->gamma_size;
66 b = g + crtc->gamma_size;
67 for (i = 0; i < 256; i++) {
68 WREG32(AVIVO_DC_LUT_30_COLOR,
69 ((*r++ & 0xffc0) << 14) |
70 ((*g++ & 0xffc0) << 4) |
71 (*b++ >> 6));
72 }
73
74 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
75 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
76 }
77
dce4_crtc_load_lut(struct drm_crtc * crtc)78 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
79 {
80 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 u16 *r, *g, *b;
84 int i;
85
86 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
87 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
88
89 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
92
93 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
94 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
96
97 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
98 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
99
100 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
101 r = crtc->gamma_store;
102 g = r + crtc->gamma_size;
103 b = g + crtc->gamma_size;
104 for (i = 0; i < 256; i++) {
105 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
106 ((*r++ & 0xffc0) << 14) |
107 ((*g++ & 0xffc0) << 4) |
108 (*b++ >> 6));
109 }
110 }
111
dce5_crtc_load_lut(struct drm_crtc * crtc)112 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
113 {
114 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
115 struct drm_device *dev = crtc->dev;
116 struct radeon_device *rdev = dev->dev_private;
117 u16 *r, *g, *b;
118 int i;
119
120 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
121
122 msleep(10);
123
124 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
125 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
126 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
127 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
128 NI_GRPH_PRESCALE_BYPASS);
129 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
130 NI_OVL_PRESCALE_BYPASS);
131 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
132 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
133 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
134
135 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
136
137 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
138 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
139 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
140
141 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
142 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
143 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
144
145 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
146 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
147
148 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
149 r = crtc->gamma_store;
150 g = r + crtc->gamma_size;
151 b = g + crtc->gamma_size;
152 for (i = 0; i < 256; i++) {
153 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
154 ((*r++ & 0xffc0) << 14) |
155 ((*g++ & 0xffc0) << 4) |
156 (*b++ >> 6));
157 }
158
159 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
160 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
161 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
162 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
163 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
164 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
165 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
166 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
167 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
168 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
169 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
170 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
171 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
172 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
173 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
174 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
175 if (ASIC_IS_DCE8(rdev)) {
176 /* XXX this only needs to be programmed once per crtc at startup,
177 * not sure where the best place for it is
178 */
179 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
180 CIK_CURSOR_ALPHA_BLND_ENA);
181 }
182 }
183
legacy_crtc_load_lut(struct drm_crtc * crtc)184 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
185 {
186 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
187 struct drm_device *dev = crtc->dev;
188 struct radeon_device *rdev = dev->dev_private;
189 u16 *r, *g, *b;
190 int i;
191 uint32_t dac2_cntl;
192
193 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
194 if (radeon_crtc->crtc_id == 0)
195 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
196 else
197 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
198 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
199
200 WREG8(RADEON_PALETTE_INDEX, 0);
201 r = crtc->gamma_store;
202 g = r + crtc->gamma_size;
203 b = g + crtc->gamma_size;
204 for (i = 0; i < 256; i++) {
205 WREG32(RADEON_PALETTE_30_DATA,
206 ((*r++ & 0xffc0) << 14) |
207 ((*g++ & 0xffc0) << 4) |
208 (*b++ >> 6));
209 }
210 }
211
radeon_crtc_load_lut(struct drm_crtc * crtc)212 void radeon_crtc_load_lut(struct drm_crtc *crtc)
213 {
214 struct drm_device *dev = crtc->dev;
215 struct radeon_device *rdev = dev->dev_private;
216
217 if (!crtc->enabled)
218 return;
219
220 if (ASIC_IS_DCE5(rdev))
221 dce5_crtc_load_lut(crtc);
222 else if (ASIC_IS_DCE4(rdev))
223 dce4_crtc_load_lut(crtc);
224 else if (ASIC_IS_AVIVO(rdev))
225 avivo_crtc_load_lut(crtc);
226 else
227 legacy_crtc_load_lut(crtc);
228 }
229
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)230 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
231 u16 *blue, uint32_t size,
232 struct drm_modeset_acquire_ctx *ctx)
233 {
234 radeon_crtc_load_lut(crtc);
235
236 return 0;
237 }
238
radeon_crtc_destroy(struct drm_crtc * crtc)239 static void radeon_crtc_destroy(struct drm_crtc *crtc)
240 {
241 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
242
243 drm_crtc_cleanup(crtc);
244 destroy_workqueue(radeon_crtc->flip_queue);
245 kfree(radeon_crtc);
246 }
247
248 /**
249 * radeon_unpin_work_func - unpin old buffer object
250 *
251 * @__work - kernel work item
252 *
253 * Unpin the old frame buffer object outside of the interrupt handler
254 */
radeon_unpin_work_func(struct work_struct * __work)255 static void radeon_unpin_work_func(struct work_struct *__work)
256 {
257 struct radeon_flip_work *work =
258 container_of(__work, struct radeon_flip_work, unpin_work);
259 int r;
260
261 /* unpin of the old buffer */
262 r = radeon_bo_reserve(work->old_rbo, false);
263 if (likely(r == 0)) {
264 r = radeon_bo_unpin(work->old_rbo);
265 if (unlikely(r != 0)) {
266 DRM_ERROR("failed to unpin buffer after flip\n");
267 }
268 radeon_bo_unreserve(work->old_rbo);
269 } else
270 DRM_ERROR("failed to reserve buffer after flip\n");
271
272 drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
273 kfree(work);
274 }
275
radeon_crtc_handle_vblank(struct radeon_device * rdev,int crtc_id)276 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
277 {
278 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
279 unsigned long flags;
280 u32 update_pending;
281 int vpos, hpos;
282
283 /* can happen during initialization */
284 if (radeon_crtc == NULL)
285 return;
286
287 /* Skip the pageflip completion check below (based on polling) on
288 * asics which reliably support hw pageflip completion irqs. pflip
289 * irqs are a reliable and race-free method of handling pageflip
290 * completion detection. A use_pflipirq module parameter < 2 allows
291 * to override this in case of asics with faulty pflip irqs.
292 * A module parameter of 0 would only use this polling based path,
293 * a parameter of 1 would use pflip irq only as a backup to this
294 * path, as in Linux 3.16.
295 */
296 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
297 return;
298
299 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
300 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
301 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
302 "RADEON_FLIP_SUBMITTED(%d)\n",
303 radeon_crtc->flip_status,
304 RADEON_FLIP_SUBMITTED);
305 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
306 return;
307 }
308
309 update_pending = radeon_page_flip_pending(rdev, crtc_id);
310
311 /* Has the pageflip already completed in crtc, or is it certain
312 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
313 * distance to start of "fudged earlier" vblank in vpos, distance to
314 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
315 * the last few scanlines before start of real vblank, where the vblank
316 * irq can fire, so we have sampled update_pending a bit too early and
317 * know the flip will complete at leading edge of the upcoming real
318 * vblank. On pre-AVIVO hardware, flips also complete inside the real
319 * vblank, not only at leading edge, so if update_pending for hpos >= 0
320 * == inside real vblank, the flip will complete almost immediately.
321 * Note that this method of completion handling is still not 100% race
322 * free, as we could execute before the radeon_flip_work_func managed
323 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
324 * but the flip still gets programmed into hw and completed during
325 * vblank, leading to a delayed emission of the flip completion event.
326 * This applies at least to pre-AVIVO hardware, where flips are always
327 * completing inside vblank, not only at leading edge of vblank.
328 */
329 if (update_pending &&
330 (DRM_SCANOUTPOS_VALID &
331 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
332 GET_DISTANCE_TO_VBLANKSTART,
333 &vpos, &hpos, NULL, NULL,
334 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
335 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
336 /* crtc didn't flip in this target vblank interval,
337 * but flip is pending in crtc. Based on the current
338 * scanout position we know that the current frame is
339 * (nearly) complete and the flip will (likely)
340 * complete before the start of the next frame.
341 */
342 update_pending = 0;
343 }
344 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
345 if (!update_pending)
346 radeon_crtc_handle_flip(rdev, crtc_id);
347 }
348
349 /**
350 * radeon_crtc_handle_flip - page flip completed
351 *
352 * @rdev: radeon device pointer
353 * @crtc_id: crtc number this event is for
354 *
355 * Called when we are sure that a page flip for this crtc is completed.
356 */
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)357 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
358 {
359 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
360 struct radeon_flip_work *work;
361 unsigned long flags;
362
363 /* this can happen at init */
364 if (radeon_crtc == NULL)
365 return;
366
367 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
368 work = radeon_crtc->flip_work;
369 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
370 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
371 "RADEON_FLIP_SUBMITTED(%d)\n",
372 radeon_crtc->flip_status,
373 RADEON_FLIP_SUBMITTED);
374 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
375 return;
376 }
377
378 /* Pageflip completed. Clean up. */
379 radeon_crtc->flip_status = RADEON_FLIP_NONE;
380 radeon_crtc->flip_work = NULL;
381
382 /* wakeup userspace */
383 if (work->event)
384 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
385
386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
387
388 drm_crtc_vblank_put(&radeon_crtc->base);
389 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
390 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
391 }
392
393 /**
394 * radeon_flip_work_func - page flip framebuffer
395 *
396 * @work - kernel work item
397 *
398 * Wait for the buffer object to become idle and do the actual page flip
399 */
radeon_flip_work_func(struct work_struct * __work)400 static void radeon_flip_work_func(struct work_struct *__work)
401 {
402 struct radeon_flip_work *work =
403 container_of(__work, struct radeon_flip_work, flip_work);
404 struct radeon_device *rdev = work->rdev;
405 struct drm_device *dev = rdev->ddev;
406 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
407
408 struct drm_crtc *crtc = &radeon_crtc->base;
409 unsigned long flags;
410 int r;
411 int vpos, hpos;
412
413 down_read(&rdev->exclusive_lock);
414 if (work->fence) {
415 struct radeon_fence *fence;
416
417 fence = to_radeon_fence(work->fence);
418 if (fence && fence->rdev == rdev) {
419 r = radeon_fence_wait(fence, false);
420 if (r == -EDEADLK) {
421 up_read(&rdev->exclusive_lock);
422 do {
423 r = radeon_gpu_reset(rdev);
424 } while (r == -EAGAIN);
425 down_read(&rdev->exclusive_lock);
426 }
427 } else
428 r = dma_fence_wait(work->fence, false);
429
430 if (r)
431 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
432
433 /* We continue with the page flip even if we failed to wait on
434 * the fence, otherwise the DRM core and userspace will be
435 * confused about which BO the CRTC is scanning out
436 */
437
438 dma_fence_put(work->fence);
439 work->fence = NULL;
440 }
441
442 /* Wait until we're out of the vertical blank period before the one
443 * targeted by the flip. Always wait on pre DCE4 to avoid races with
444 * flip completion handling from vblank irq, as these old asics don't
445 * have reliable pageflip completion interrupts.
446 */
447 while (radeon_crtc->enabled &&
448 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
449 &vpos, &hpos, NULL, NULL,
450 &crtc->hwmode)
451 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
452 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
453 (!ASIC_IS_AVIVO(rdev) ||
454 ((int) (work->target_vblank -
455 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)))
456 usleep_range(1000, 2000);
457
458 /* We borrow the event spin lock for protecting flip_status */
459 spin_lock_irqsave(&crtc->dev->event_lock, flags);
460
461 /* set the proper interrupt */
462 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
463
464 /* do the flip (mmio) */
465 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
466
467 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
468 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
469 up_read(&rdev->exclusive_lock);
470 }
471
radeon_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)472 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
473 struct drm_framebuffer *fb,
474 struct drm_pending_vblank_event *event,
475 uint32_t page_flip_flags,
476 uint32_t target,
477 struct drm_modeset_acquire_ctx *ctx)
478 {
479 struct drm_device *dev = crtc->dev;
480 struct radeon_device *rdev = dev->dev_private;
481 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
482 struct radeon_framebuffer *old_radeon_fb;
483 struct radeon_framebuffer *new_radeon_fb;
484 struct drm_gem_object *obj;
485 struct radeon_flip_work *work;
486 struct radeon_bo *new_rbo;
487 uint32_t tiling_flags, pitch_pixels;
488 uint64_t base;
489 unsigned long flags;
490 int r;
491
492 work = kzalloc(sizeof *work, GFP_KERNEL);
493 if (work == NULL)
494 return -ENOMEM;
495
496 INIT_WORK(&work->flip_work, radeon_flip_work_func);
497 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
498
499 work->rdev = rdev;
500 work->crtc_id = radeon_crtc->crtc_id;
501 work->event = event;
502 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
503
504 /* schedule unpin of the old buffer */
505 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
506 obj = old_radeon_fb->obj;
507
508 /* take a reference to the old object */
509 drm_gem_object_get(obj);
510 work->old_rbo = gem_to_radeon_bo(obj);
511
512 new_radeon_fb = to_radeon_framebuffer(fb);
513 obj = new_radeon_fb->obj;
514 new_rbo = gem_to_radeon_bo(obj);
515
516 /* pin the new buffer */
517 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
518 work->old_rbo, new_rbo);
519
520 r = radeon_bo_reserve(new_rbo, false);
521 if (unlikely(r != 0)) {
522 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
523 goto cleanup;
524 }
525 /* Only 27 bit offset for legacy CRTC */
526 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
527 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
528 if (unlikely(r != 0)) {
529 radeon_bo_unreserve(new_rbo);
530 r = -EINVAL;
531 DRM_ERROR("failed to pin new rbo buffer before flip\n");
532 goto cleanup;
533 }
534 work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
535 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
536 radeon_bo_unreserve(new_rbo);
537
538 if (!ASIC_IS_AVIVO(rdev)) {
539 /* crtc offset is from display base addr not FB location */
540 base -= radeon_crtc->legacy_display_base_addr;
541 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
542
543 if (tiling_flags & RADEON_TILING_MACRO) {
544 if (ASIC_IS_R300(rdev)) {
545 base &= ~0x7ff;
546 } else {
547 int byteshift = fb->format->cpp[0] * 8 >> 4;
548 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
549 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
550 }
551 } else {
552 int offset = crtc->y * pitch_pixels + crtc->x;
553 switch (fb->format->cpp[0] * 8) {
554 case 8:
555 default:
556 offset *= 1;
557 break;
558 case 15:
559 case 16:
560 offset *= 2;
561 break;
562 case 24:
563 offset *= 3;
564 break;
565 case 32:
566 offset *= 4;
567 break;
568 }
569 base += offset;
570 }
571 base &= ~7;
572 }
573 work->base = base;
574 work->target_vblank = target - drm_crtc_vblank_count(crtc) +
575 dev->driver->get_vblank_counter(dev, work->crtc_id);
576
577 /* We borrow the event spin lock for protecting flip_work */
578 spin_lock_irqsave(&crtc->dev->event_lock, flags);
579
580 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
581 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
582 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
583 r = -EBUSY;
584 goto pflip_cleanup;
585 }
586 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
587 radeon_crtc->flip_work = work;
588
589 /* update crtc fb */
590 crtc->primary->fb = fb;
591
592 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
593
594 queue_work(radeon_crtc->flip_queue, &work->flip_work);
595 return 0;
596
597 pflip_cleanup:
598 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
599 DRM_ERROR("failed to reserve new rbo in error path\n");
600 goto cleanup;
601 }
602 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
603 DRM_ERROR("failed to unpin new rbo in error path\n");
604 }
605 radeon_bo_unreserve(new_rbo);
606
607 cleanup:
608 drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
609 dma_fence_put(work->fence);
610 kfree(work);
611 return r;
612 }
613
614 static int
radeon_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)615 radeon_crtc_set_config(struct drm_mode_set *set,
616 struct drm_modeset_acquire_ctx *ctx)
617 {
618 struct drm_device *dev;
619 struct radeon_device *rdev;
620 struct drm_crtc *crtc;
621 bool active = false;
622 int ret;
623
624 if (!set || !set->crtc)
625 return -EINVAL;
626
627 dev = set->crtc->dev;
628
629 ret = pm_runtime_get_sync(dev->dev);
630 if (ret < 0)
631 return ret;
632
633 ret = drm_crtc_helper_set_config(set, ctx);
634
635 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
636 if (crtc->enabled)
637 active = true;
638
639 pm_runtime_mark_last_busy(dev->dev);
640
641 rdev = dev->dev_private;
642 /* if we have active crtcs and we don't have a power ref,
643 take the current one */
644 if (active && !rdev->have_disp_power_ref) {
645 rdev->have_disp_power_ref = true;
646 return ret;
647 }
648 /* if we have no active crtcs, then drop the power ref
649 we got before */
650 if (!active && rdev->have_disp_power_ref) {
651 pm_runtime_put_autosuspend(dev->dev);
652 rdev->have_disp_power_ref = false;
653 }
654
655 /* drop the power reference we got coming in here */
656 pm_runtime_put_autosuspend(dev->dev);
657 return ret;
658 }
659
660 static const struct drm_crtc_funcs radeon_crtc_funcs = {
661 .cursor_set2 = radeon_crtc_cursor_set2,
662 .cursor_move = radeon_crtc_cursor_move,
663 .gamma_set = radeon_crtc_gamma_set,
664 .set_config = radeon_crtc_set_config,
665 .destroy = radeon_crtc_destroy,
666 .page_flip_target = radeon_crtc_page_flip_target,
667 };
668
radeon_crtc_init(struct drm_device * dev,int index)669 static void radeon_crtc_init(struct drm_device *dev, int index)
670 {
671 struct radeon_device *rdev = dev->dev_private;
672 struct radeon_crtc *radeon_crtc;
673 int i;
674
675 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
676 if (radeon_crtc == NULL)
677 return;
678
679 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
680
681 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
682 radeon_crtc->crtc_id = index;
683 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
684 rdev->mode_info.crtcs[index] = radeon_crtc;
685
686 if (rdev->family >= CHIP_BONAIRE) {
687 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
688 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
689 } else {
690 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
691 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
692 }
693 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
694 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
695
696 #if 0
697 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
698 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
699 radeon_crtc->mode_set.num_connectors = 0;
700 #endif
701
702 for (i = 0; i < 256; i++) {
703 radeon_crtc->lut_r[i] = i << 2;
704 radeon_crtc->lut_g[i] = i << 2;
705 radeon_crtc->lut_b[i] = i << 2;
706 }
707
708 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
709 radeon_atombios_init_crtc(dev, radeon_crtc);
710 else
711 radeon_legacy_init_crtc(dev, radeon_crtc);
712 }
713
714 static const char *encoder_names[38] = {
715 "NONE",
716 "INTERNAL_LVDS",
717 "INTERNAL_TMDS1",
718 "INTERNAL_TMDS2",
719 "INTERNAL_DAC1",
720 "INTERNAL_DAC2",
721 "INTERNAL_SDVOA",
722 "INTERNAL_SDVOB",
723 "SI170B",
724 "CH7303",
725 "CH7301",
726 "INTERNAL_DVO1",
727 "EXTERNAL_SDVOA",
728 "EXTERNAL_SDVOB",
729 "TITFP513",
730 "INTERNAL_LVTM1",
731 "VT1623",
732 "HDMI_SI1930",
733 "HDMI_INTERNAL",
734 "INTERNAL_KLDSCP_TMDS1",
735 "INTERNAL_KLDSCP_DVO1",
736 "INTERNAL_KLDSCP_DAC1",
737 "INTERNAL_KLDSCP_DAC2",
738 "SI178",
739 "MVPU_FPGA",
740 "INTERNAL_DDI",
741 "VT1625",
742 "HDMI_SI1932",
743 "DP_AN9801",
744 "DP_DP501",
745 "INTERNAL_UNIPHY",
746 "INTERNAL_KLDSCP_LVTMA",
747 "INTERNAL_UNIPHY1",
748 "INTERNAL_UNIPHY2",
749 "NUTMEG",
750 "TRAVIS",
751 "INTERNAL_VCE",
752 "INTERNAL_UNIPHY3",
753 };
754
755 static const char *hpd_names[6] = {
756 "HPD1",
757 "HPD2",
758 "HPD3",
759 "HPD4",
760 "HPD5",
761 "HPD6",
762 };
763
radeon_print_display_setup(struct drm_device * dev)764 static void radeon_print_display_setup(struct drm_device *dev)
765 {
766 struct drm_connector *connector;
767 struct radeon_connector *radeon_connector;
768 struct drm_encoder *encoder;
769 struct radeon_encoder *radeon_encoder;
770 uint32_t devices;
771 int i = 0;
772
773 DRM_INFO("Radeon Display Connectors\n");
774 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
775 radeon_connector = to_radeon_connector(connector);
776 DRM_INFO("Connector %d:\n", i);
777 DRM_INFO(" %s\n", connector->name);
778 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
779 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
780 if (radeon_connector->ddc_bus) {
781 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
782 radeon_connector->ddc_bus->rec.mask_clk_reg,
783 radeon_connector->ddc_bus->rec.mask_data_reg,
784 radeon_connector->ddc_bus->rec.a_clk_reg,
785 radeon_connector->ddc_bus->rec.a_data_reg,
786 radeon_connector->ddc_bus->rec.en_clk_reg,
787 radeon_connector->ddc_bus->rec.en_data_reg,
788 radeon_connector->ddc_bus->rec.y_clk_reg,
789 radeon_connector->ddc_bus->rec.y_data_reg);
790 if (radeon_connector->router.ddc_valid)
791 DRM_INFO(" DDC Router 0x%x/0x%x\n",
792 radeon_connector->router.ddc_mux_control_pin,
793 radeon_connector->router.ddc_mux_state);
794 if (radeon_connector->router.cd_valid)
795 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
796 radeon_connector->router.cd_mux_control_pin,
797 radeon_connector->router.cd_mux_state);
798 } else {
799 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
800 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
801 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
802 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
803 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
804 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
805 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
806 }
807 DRM_INFO(" Encoders:\n");
808 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
809 radeon_encoder = to_radeon_encoder(encoder);
810 devices = radeon_encoder->devices & radeon_connector->devices;
811 if (devices) {
812 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
813 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
814 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
815 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
816 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
817 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
818 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
819 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
820 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
821 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
822 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
823 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
824 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
825 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
826 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
827 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
828 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
829 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
830 if (devices & ATOM_DEVICE_TV1_SUPPORT)
831 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
832 if (devices & ATOM_DEVICE_CV_SUPPORT)
833 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
834 }
835 }
836 i++;
837 }
838 }
839
radeon_setup_enc_conn(struct drm_device * dev)840 static bool radeon_setup_enc_conn(struct drm_device *dev)
841 {
842 struct radeon_device *rdev = dev->dev_private;
843 bool ret = false;
844
845 if (rdev->bios) {
846 if (rdev->is_atom_bios) {
847 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
848 if (ret == false)
849 ret = radeon_get_atom_connector_info_from_object_table(dev);
850 } else {
851 ret = radeon_get_legacy_connector_info_from_bios(dev);
852 if (ret == false)
853 ret = radeon_get_legacy_connector_info_from_table(dev);
854 }
855 } else {
856 if (!ASIC_IS_AVIVO(rdev))
857 ret = radeon_get_legacy_connector_info_from_table(dev);
858 }
859 if (ret) {
860 radeon_setup_encoder_clones(dev);
861 radeon_print_display_setup(dev);
862 }
863
864 return ret;
865 }
866
867 /* avivo */
868
869 /**
870 * avivo_reduce_ratio - fractional number reduction
871 *
872 * @nom: nominator
873 * @den: denominator
874 * @nom_min: minimum value for nominator
875 * @den_min: minimum value for denominator
876 *
877 * Find the greatest common divisor and apply it on both nominator and
878 * denominator, but make nominator and denominator are at least as large
879 * as their minimum values.
880 */
avivo_reduce_ratio(unsigned * nom,unsigned * den,unsigned nom_min,unsigned den_min)881 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
882 unsigned nom_min, unsigned den_min)
883 {
884 unsigned tmp;
885
886 /* reduce the numbers to a simpler ratio */
887 tmp = gcd(*nom, *den);
888 *nom /= tmp;
889 *den /= tmp;
890
891 /* make sure nominator is large enough */
892 if (*nom < nom_min) {
893 tmp = DIV_ROUND_UP(nom_min, *nom);
894 *nom *= tmp;
895 *den *= tmp;
896 }
897
898 /* make sure the denominator is large enough */
899 if (*den < den_min) {
900 tmp = DIV_ROUND_UP(den_min, *den);
901 *nom *= tmp;
902 *den *= tmp;
903 }
904 }
905
906 /**
907 * avivo_get_fb_ref_div - feedback and ref divider calculation
908 *
909 * @nom: nominator
910 * @den: denominator
911 * @post_div: post divider
912 * @fb_div_max: feedback divider maximum
913 * @ref_div_max: reference divider maximum
914 * @fb_div: resulting feedback divider
915 * @ref_div: resulting reference divider
916 *
917 * Calculate feedback and reference divider for a given post divider. Makes
918 * sure we stay within the limits.
919 */
avivo_get_fb_ref_div(unsigned nom,unsigned den,unsigned post_div,unsigned fb_div_max,unsigned ref_div_max,unsigned * fb_div,unsigned * ref_div)920 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
921 unsigned fb_div_max, unsigned ref_div_max,
922 unsigned *fb_div, unsigned *ref_div)
923 {
924 /* limit reference * post divider to a maximum */
925 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
926
927 /* get matching reference and feedback divider */
928 *ref_div = min(max(den/post_div, 1u), ref_div_max);
929 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
930
931 /* limit fb divider to its maximum */
932 if (*fb_div > fb_div_max) {
933 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
934 *fb_div = fb_div_max;
935 }
936 }
937
938 /**
939 * radeon_compute_pll_avivo - compute PLL paramaters
940 *
941 * @pll: information about the PLL
942 * @dot_clock_p: resulting pixel clock
943 * fb_div_p: resulting feedback divider
944 * frac_fb_div_p: fractional part of the feedback divider
945 * ref_div_p: resulting reference divider
946 * post_div_p: resulting reference divider
947 *
948 * Try to calculate the PLL parameters to generate the given frequency:
949 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
950 */
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)951 void radeon_compute_pll_avivo(struct radeon_pll *pll,
952 u32 freq,
953 u32 *dot_clock_p,
954 u32 *fb_div_p,
955 u32 *frac_fb_div_p,
956 u32 *ref_div_p,
957 u32 *post_div_p)
958 {
959 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
960 freq : freq / 10;
961
962 unsigned fb_div_min, fb_div_max, fb_div;
963 unsigned post_div_min, post_div_max, post_div;
964 unsigned ref_div_min, ref_div_max, ref_div;
965 unsigned post_div_best, diff_best;
966 unsigned nom, den;
967
968 /* determine allowed feedback divider range */
969 fb_div_min = pll->min_feedback_div;
970 fb_div_max = pll->max_feedback_div;
971
972 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
973 fb_div_min *= 10;
974 fb_div_max *= 10;
975 }
976
977 /* determine allowed ref divider range */
978 if (pll->flags & RADEON_PLL_USE_REF_DIV)
979 ref_div_min = pll->reference_div;
980 else
981 ref_div_min = pll->min_ref_div;
982
983 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
984 pll->flags & RADEON_PLL_USE_REF_DIV)
985 ref_div_max = pll->reference_div;
986 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
987 /* fix for problems on RS880 */
988 ref_div_max = min(pll->max_ref_div, 7u);
989 else
990 ref_div_max = pll->max_ref_div;
991
992 /* determine allowed post divider range */
993 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
994 post_div_min = pll->post_div;
995 post_div_max = pll->post_div;
996 } else {
997 unsigned vco_min, vco_max;
998
999 if (pll->flags & RADEON_PLL_IS_LCD) {
1000 vco_min = pll->lcd_pll_out_min;
1001 vco_max = pll->lcd_pll_out_max;
1002 } else {
1003 vco_min = pll->pll_out_min;
1004 vco_max = pll->pll_out_max;
1005 }
1006
1007 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1008 vco_min *= 10;
1009 vco_max *= 10;
1010 }
1011
1012 post_div_min = vco_min / target_clock;
1013 if ((target_clock * post_div_min) < vco_min)
1014 ++post_div_min;
1015 if (post_div_min < pll->min_post_div)
1016 post_div_min = pll->min_post_div;
1017
1018 post_div_max = vco_max / target_clock;
1019 if ((target_clock * post_div_max) > vco_max)
1020 --post_div_max;
1021 if (post_div_max > pll->max_post_div)
1022 post_div_max = pll->max_post_div;
1023 }
1024
1025 /* represent the searched ratio as fractional number */
1026 nom = target_clock;
1027 den = pll->reference_freq;
1028
1029 /* reduce the numbers to a simpler ratio */
1030 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1031
1032 /* now search for a post divider */
1033 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1034 post_div_best = post_div_min;
1035 else
1036 post_div_best = post_div_max;
1037 diff_best = ~0;
1038
1039 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1040 unsigned diff;
1041 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1042 ref_div_max, &fb_div, &ref_div);
1043 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1044 (ref_div * post_div));
1045
1046 if (diff < diff_best || (diff == diff_best &&
1047 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1048
1049 post_div_best = post_div;
1050 diff_best = diff;
1051 }
1052 }
1053 post_div = post_div_best;
1054
1055 /* get the feedback and reference divider for the optimal value */
1056 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1057 &fb_div, &ref_div);
1058
1059 /* reduce the numbers to a simpler ratio once more */
1060 /* this also makes sure that the reference divider is large enough */
1061 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1062
1063 /* avoid high jitter with small fractional dividers */
1064 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1065 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1066 if (fb_div < fb_div_min) {
1067 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1068 fb_div *= tmp;
1069 ref_div *= tmp;
1070 }
1071 }
1072
1073 /* and finally save the result */
1074 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1075 *fb_div_p = fb_div / 10;
1076 *frac_fb_div_p = fb_div % 10;
1077 } else {
1078 *fb_div_p = fb_div;
1079 *frac_fb_div_p = 0;
1080 }
1081
1082 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1083 (pll->reference_freq * *frac_fb_div_p)) /
1084 (ref_div * post_div * 10);
1085 *ref_div_p = ref_div;
1086 *post_div_p = post_div;
1087
1088 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1089 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1090 ref_div, post_div);
1091 }
1092
1093 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)1094 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1095 {
1096 uint64_t mod;
1097
1098 n += d / 2;
1099
1100 mod = do_div(n, d);
1101 return n;
1102 }
1103
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)1104 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1105 uint64_t freq,
1106 uint32_t *dot_clock_p,
1107 uint32_t *fb_div_p,
1108 uint32_t *frac_fb_div_p,
1109 uint32_t *ref_div_p,
1110 uint32_t *post_div_p)
1111 {
1112 uint32_t min_ref_div = pll->min_ref_div;
1113 uint32_t max_ref_div = pll->max_ref_div;
1114 uint32_t min_post_div = pll->min_post_div;
1115 uint32_t max_post_div = pll->max_post_div;
1116 uint32_t min_fractional_feed_div = 0;
1117 uint32_t max_fractional_feed_div = 0;
1118 uint32_t best_vco = pll->best_vco;
1119 uint32_t best_post_div = 1;
1120 uint32_t best_ref_div = 1;
1121 uint32_t best_feedback_div = 1;
1122 uint32_t best_frac_feedback_div = 0;
1123 uint32_t best_freq = -1;
1124 uint32_t best_error = 0xffffffff;
1125 uint32_t best_vco_diff = 1;
1126 uint32_t post_div;
1127 u32 pll_out_min, pll_out_max;
1128
1129 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1130 freq = freq * 1000;
1131
1132 if (pll->flags & RADEON_PLL_IS_LCD) {
1133 pll_out_min = pll->lcd_pll_out_min;
1134 pll_out_max = pll->lcd_pll_out_max;
1135 } else {
1136 pll_out_min = pll->pll_out_min;
1137 pll_out_max = pll->pll_out_max;
1138 }
1139
1140 if (pll_out_min > 64800)
1141 pll_out_min = 64800;
1142
1143 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1144 min_ref_div = max_ref_div = pll->reference_div;
1145 else {
1146 while (min_ref_div < max_ref_div-1) {
1147 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1148 uint32_t pll_in = pll->reference_freq / mid;
1149 if (pll_in < pll->pll_in_min)
1150 max_ref_div = mid;
1151 else if (pll_in > pll->pll_in_max)
1152 min_ref_div = mid;
1153 else
1154 break;
1155 }
1156 }
1157
1158 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1159 min_post_div = max_post_div = pll->post_div;
1160
1161 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1162 min_fractional_feed_div = pll->min_frac_feedback_div;
1163 max_fractional_feed_div = pll->max_frac_feedback_div;
1164 }
1165
1166 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1167 uint32_t ref_div;
1168
1169 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1170 continue;
1171
1172 /* legacy radeons only have a few post_divs */
1173 if (pll->flags & RADEON_PLL_LEGACY) {
1174 if ((post_div == 5) ||
1175 (post_div == 7) ||
1176 (post_div == 9) ||
1177 (post_div == 10) ||
1178 (post_div == 11) ||
1179 (post_div == 13) ||
1180 (post_div == 14) ||
1181 (post_div == 15))
1182 continue;
1183 }
1184
1185 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1186 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1187 uint32_t pll_in = pll->reference_freq / ref_div;
1188 uint32_t min_feed_div = pll->min_feedback_div;
1189 uint32_t max_feed_div = pll->max_feedback_div + 1;
1190
1191 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1192 continue;
1193
1194 while (min_feed_div < max_feed_div) {
1195 uint32_t vco;
1196 uint32_t min_frac_feed_div = min_fractional_feed_div;
1197 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1198 uint32_t frac_feedback_div;
1199 uint64_t tmp;
1200
1201 feedback_div = (min_feed_div + max_feed_div) / 2;
1202
1203 tmp = (uint64_t)pll->reference_freq * feedback_div;
1204 vco = radeon_div(tmp, ref_div);
1205
1206 if (vco < pll_out_min) {
1207 min_feed_div = feedback_div + 1;
1208 continue;
1209 } else if (vco > pll_out_max) {
1210 max_feed_div = feedback_div;
1211 continue;
1212 }
1213
1214 while (min_frac_feed_div < max_frac_feed_div) {
1215 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1216 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1217 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1218 current_freq = radeon_div(tmp, ref_div * post_div);
1219
1220 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1221 if (freq < current_freq)
1222 error = 0xffffffff;
1223 else
1224 error = freq - current_freq;
1225 } else
1226 error = abs(current_freq - freq);
1227 vco_diff = abs(vco - best_vco);
1228
1229 if ((best_vco == 0 && error < best_error) ||
1230 (best_vco != 0 &&
1231 ((best_error > 100 && error < best_error - 100) ||
1232 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1233 best_post_div = post_div;
1234 best_ref_div = ref_div;
1235 best_feedback_div = feedback_div;
1236 best_frac_feedback_div = frac_feedback_div;
1237 best_freq = current_freq;
1238 best_error = error;
1239 best_vco_diff = vco_diff;
1240 } else if (current_freq == freq) {
1241 if (best_freq == -1) {
1242 best_post_div = post_div;
1243 best_ref_div = ref_div;
1244 best_feedback_div = feedback_div;
1245 best_frac_feedback_div = frac_feedback_div;
1246 best_freq = current_freq;
1247 best_error = error;
1248 best_vco_diff = vco_diff;
1249 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1250 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1251 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1252 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1253 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1254 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1255 best_post_div = post_div;
1256 best_ref_div = ref_div;
1257 best_feedback_div = feedback_div;
1258 best_frac_feedback_div = frac_feedback_div;
1259 best_freq = current_freq;
1260 best_error = error;
1261 best_vco_diff = vco_diff;
1262 }
1263 }
1264 if (current_freq < freq)
1265 min_frac_feed_div = frac_feedback_div + 1;
1266 else
1267 max_frac_feed_div = frac_feedback_div;
1268 }
1269 if (current_freq < freq)
1270 min_feed_div = feedback_div + 1;
1271 else
1272 max_feed_div = feedback_div;
1273 }
1274 }
1275 }
1276
1277 *dot_clock_p = best_freq / 10000;
1278 *fb_div_p = best_feedback_div;
1279 *frac_fb_div_p = best_frac_feedback_div;
1280 *ref_div_p = best_ref_div;
1281 *post_div_p = best_post_div;
1282 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1283 (long long)freq,
1284 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1285 best_ref_div, best_post_div);
1286
1287 }
1288
radeon_user_framebuffer_destroy(struct drm_framebuffer * fb)1289 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1290 {
1291 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1292
1293 drm_gem_object_put_unlocked(radeon_fb->obj);
1294 drm_framebuffer_cleanup(fb);
1295 kfree(radeon_fb);
1296 }
1297
radeon_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)1298 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1299 struct drm_file *file_priv,
1300 unsigned int *handle)
1301 {
1302 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1303
1304 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1305 }
1306
1307 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1308 .destroy = radeon_user_framebuffer_destroy,
1309 .create_handle = radeon_user_framebuffer_create_handle,
1310 };
1311
1312 int
radeon_framebuffer_init(struct drm_device * dev,struct radeon_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1313 radeon_framebuffer_init(struct drm_device *dev,
1314 struct radeon_framebuffer *rfb,
1315 const struct drm_mode_fb_cmd2 *mode_cmd,
1316 struct drm_gem_object *obj)
1317 {
1318 int ret;
1319 rfb->obj = obj;
1320 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1321 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1322 if (ret) {
1323 rfb->obj = NULL;
1324 return ret;
1325 }
1326 return 0;
1327 }
1328
1329 static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1330 radeon_user_framebuffer_create(struct drm_device *dev,
1331 struct drm_file *file_priv,
1332 const struct drm_mode_fb_cmd2 *mode_cmd)
1333 {
1334 struct drm_gem_object *obj;
1335 struct radeon_framebuffer *radeon_fb;
1336 int ret;
1337
1338 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1339 if (obj == NULL) {
1340 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1341 "can't create framebuffer\n", mode_cmd->handles[0]);
1342 return ERR_PTR(-ENOENT);
1343 }
1344
1345 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1346 if (obj->import_attach) {
1347 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1348 return ERR_PTR(-EINVAL);
1349 }
1350
1351 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1352 if (radeon_fb == NULL) {
1353 drm_gem_object_put_unlocked(obj);
1354 return ERR_PTR(-ENOMEM);
1355 }
1356
1357 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1358 if (ret) {
1359 kfree(radeon_fb);
1360 drm_gem_object_put_unlocked(obj);
1361 return ERR_PTR(ret);
1362 }
1363
1364 return &radeon_fb->base;
1365 }
1366
radeon_output_poll_changed(struct drm_device * dev)1367 static void radeon_output_poll_changed(struct drm_device *dev)
1368 {
1369 struct radeon_device *rdev = dev->dev_private;
1370 radeon_fb_output_poll_changed(rdev);
1371 }
1372
1373 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1374 .fb_create = radeon_user_framebuffer_create,
1375 .output_poll_changed = radeon_output_poll_changed
1376 };
1377
1378 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1379 { { 0, "driver" },
1380 { 1, "bios" },
1381 };
1382
1383 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1384 { { TV_STD_NTSC, "ntsc" },
1385 { TV_STD_PAL, "pal" },
1386 { TV_STD_PAL_M, "pal-m" },
1387 { TV_STD_PAL_60, "pal-60" },
1388 { TV_STD_NTSC_J, "ntsc-j" },
1389 { TV_STD_SCART_PAL, "scart-pal" },
1390 { TV_STD_PAL_CN, "pal-cn" },
1391 { TV_STD_SECAM, "secam" },
1392 };
1393
1394 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1395 { { UNDERSCAN_OFF, "off" },
1396 { UNDERSCAN_ON, "on" },
1397 { UNDERSCAN_AUTO, "auto" },
1398 };
1399
1400 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1401 { { RADEON_AUDIO_DISABLE, "off" },
1402 { RADEON_AUDIO_ENABLE, "on" },
1403 { RADEON_AUDIO_AUTO, "auto" },
1404 };
1405
1406 /* XXX support different dither options? spatial, temporal, both, etc. */
1407 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1408 { { RADEON_FMT_DITHER_DISABLE, "off" },
1409 { RADEON_FMT_DITHER_ENABLE, "on" },
1410 };
1411
1412 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1413 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1414 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1415 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1416 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1417 };
1418
radeon_modeset_create_props(struct radeon_device * rdev)1419 static int radeon_modeset_create_props(struct radeon_device *rdev)
1420 {
1421 int sz;
1422
1423 if (rdev->is_atom_bios) {
1424 rdev->mode_info.coherent_mode_property =
1425 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1426 if (!rdev->mode_info.coherent_mode_property)
1427 return -ENOMEM;
1428 }
1429
1430 if (!ASIC_IS_AVIVO(rdev)) {
1431 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1432 rdev->mode_info.tmds_pll_property =
1433 drm_property_create_enum(rdev->ddev, 0,
1434 "tmds_pll",
1435 radeon_tmds_pll_enum_list, sz);
1436 }
1437
1438 rdev->mode_info.load_detect_property =
1439 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1440 if (!rdev->mode_info.load_detect_property)
1441 return -ENOMEM;
1442
1443 drm_mode_create_scaling_mode_property(rdev->ddev);
1444
1445 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1446 rdev->mode_info.tv_std_property =
1447 drm_property_create_enum(rdev->ddev, 0,
1448 "tv standard",
1449 radeon_tv_std_enum_list, sz);
1450
1451 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1452 rdev->mode_info.underscan_property =
1453 drm_property_create_enum(rdev->ddev, 0,
1454 "underscan",
1455 radeon_underscan_enum_list, sz);
1456
1457 rdev->mode_info.underscan_hborder_property =
1458 drm_property_create_range(rdev->ddev, 0,
1459 "underscan hborder", 0, 128);
1460 if (!rdev->mode_info.underscan_hborder_property)
1461 return -ENOMEM;
1462
1463 rdev->mode_info.underscan_vborder_property =
1464 drm_property_create_range(rdev->ddev, 0,
1465 "underscan vborder", 0, 128);
1466 if (!rdev->mode_info.underscan_vborder_property)
1467 return -ENOMEM;
1468
1469 sz = ARRAY_SIZE(radeon_audio_enum_list);
1470 rdev->mode_info.audio_property =
1471 drm_property_create_enum(rdev->ddev, 0,
1472 "audio",
1473 radeon_audio_enum_list, sz);
1474
1475 sz = ARRAY_SIZE(radeon_dither_enum_list);
1476 rdev->mode_info.dither_property =
1477 drm_property_create_enum(rdev->ddev, 0,
1478 "dither",
1479 radeon_dither_enum_list, sz);
1480
1481 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1482 rdev->mode_info.output_csc_property =
1483 drm_property_create_enum(rdev->ddev, 0,
1484 "output_csc",
1485 radeon_output_csc_enum_list, sz);
1486
1487 return 0;
1488 }
1489
radeon_update_display_priority(struct radeon_device * rdev)1490 void radeon_update_display_priority(struct radeon_device *rdev)
1491 {
1492 /* adjustment options for the display watermarks */
1493 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1494 /* set display priority to high for r3xx, rv515 chips
1495 * this avoids flickering due to underflow to the
1496 * display controllers during heavy acceleration.
1497 * Don't force high on rs4xx igp chips as it seems to
1498 * affect the sound card. See kernel bug 15982.
1499 */
1500 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1501 !(rdev->flags & RADEON_IS_IGP))
1502 rdev->disp_priority = 2;
1503 else
1504 rdev->disp_priority = 0;
1505 } else
1506 rdev->disp_priority = radeon_disp_priority;
1507
1508 }
1509
1510 /*
1511 * Allocate hdmi structs and determine register offsets
1512 */
radeon_afmt_init(struct radeon_device * rdev)1513 static void radeon_afmt_init(struct radeon_device *rdev)
1514 {
1515 int i;
1516
1517 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1518 rdev->mode_info.afmt[i] = NULL;
1519
1520 if (ASIC_IS_NODCE(rdev)) {
1521 /* nothing to do */
1522 } else if (ASIC_IS_DCE4(rdev)) {
1523 static uint32_t eg_offsets[] = {
1524 EVERGREEN_CRTC0_REGISTER_OFFSET,
1525 EVERGREEN_CRTC1_REGISTER_OFFSET,
1526 EVERGREEN_CRTC2_REGISTER_OFFSET,
1527 EVERGREEN_CRTC3_REGISTER_OFFSET,
1528 EVERGREEN_CRTC4_REGISTER_OFFSET,
1529 EVERGREEN_CRTC5_REGISTER_OFFSET,
1530 0x13830 - 0x7030,
1531 };
1532 int num_afmt;
1533
1534 /* DCE8 has 7 audio blocks tied to DIG encoders */
1535 /* DCE6 has 6 audio blocks tied to DIG encoders */
1536 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1537 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1538 if (ASIC_IS_DCE8(rdev))
1539 num_afmt = 7;
1540 else if (ASIC_IS_DCE6(rdev))
1541 num_afmt = 6;
1542 else if (ASIC_IS_DCE5(rdev))
1543 num_afmt = 6;
1544 else if (ASIC_IS_DCE41(rdev))
1545 num_afmt = 2;
1546 else /* DCE4 */
1547 num_afmt = 6;
1548
1549 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1550 for (i = 0; i < num_afmt; i++) {
1551 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1552 if (rdev->mode_info.afmt[i]) {
1553 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1554 rdev->mode_info.afmt[i]->id = i;
1555 }
1556 }
1557 } else if (ASIC_IS_DCE3(rdev)) {
1558 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1559 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1560 if (rdev->mode_info.afmt[0]) {
1561 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1562 rdev->mode_info.afmt[0]->id = 0;
1563 }
1564 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1565 if (rdev->mode_info.afmt[1]) {
1566 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1567 rdev->mode_info.afmt[1]->id = 1;
1568 }
1569 } else if (ASIC_IS_DCE2(rdev)) {
1570 /* DCE2 has at least 1 routable audio block */
1571 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1572 if (rdev->mode_info.afmt[0]) {
1573 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1574 rdev->mode_info.afmt[0]->id = 0;
1575 }
1576 /* r6xx has 2 routable audio blocks */
1577 if (rdev->family >= CHIP_R600) {
1578 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1579 if (rdev->mode_info.afmt[1]) {
1580 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1581 rdev->mode_info.afmt[1]->id = 1;
1582 }
1583 }
1584 }
1585 }
1586
radeon_afmt_fini(struct radeon_device * rdev)1587 static void radeon_afmt_fini(struct radeon_device *rdev)
1588 {
1589 int i;
1590
1591 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1592 kfree(rdev->mode_info.afmt[i]);
1593 rdev->mode_info.afmt[i] = NULL;
1594 }
1595 }
1596
radeon_modeset_init(struct radeon_device * rdev)1597 int radeon_modeset_init(struct radeon_device *rdev)
1598 {
1599 int i;
1600 int ret;
1601
1602 drm_mode_config_init(rdev->ddev);
1603 rdev->mode_info.mode_config_initialized = true;
1604
1605 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1606
1607 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1608 rdev->ddev->mode_config.async_page_flip = true;
1609
1610 if (ASIC_IS_DCE5(rdev)) {
1611 rdev->ddev->mode_config.max_width = 16384;
1612 rdev->ddev->mode_config.max_height = 16384;
1613 } else if (ASIC_IS_AVIVO(rdev)) {
1614 rdev->ddev->mode_config.max_width = 8192;
1615 rdev->ddev->mode_config.max_height = 8192;
1616 } else {
1617 rdev->ddev->mode_config.max_width = 4096;
1618 rdev->ddev->mode_config.max_height = 4096;
1619 }
1620
1621 rdev->ddev->mode_config.preferred_depth = 24;
1622 rdev->ddev->mode_config.prefer_shadow = 1;
1623
1624 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1625
1626 ret = radeon_modeset_create_props(rdev);
1627 if (ret) {
1628 return ret;
1629 }
1630
1631 /* init i2c buses */
1632 radeon_i2c_init(rdev);
1633
1634 /* check combios for a valid hardcoded EDID - Sun servers */
1635 if (!rdev->is_atom_bios) {
1636 /* check for hardcoded EDID in BIOS */
1637 radeon_combios_check_hardcoded_edid(rdev);
1638 }
1639
1640 /* allocate crtcs */
1641 for (i = 0; i < rdev->num_crtc; i++) {
1642 radeon_crtc_init(rdev->ddev, i);
1643 }
1644
1645 /* okay we should have all the bios connectors */
1646 ret = radeon_setup_enc_conn(rdev->ddev);
1647 if (!ret) {
1648 return ret;
1649 }
1650
1651 /* init dig PHYs, disp eng pll */
1652 if (rdev->is_atom_bios) {
1653 radeon_atom_encoder_init(rdev);
1654 radeon_atom_disp_eng_pll_init(rdev);
1655 }
1656
1657 /* initialize hpd */
1658 radeon_hpd_init(rdev);
1659
1660 /* setup afmt */
1661 radeon_afmt_init(rdev);
1662
1663 radeon_fbdev_init(rdev);
1664 drm_kms_helper_poll_init(rdev->ddev);
1665
1666 /* do pm late init */
1667 ret = radeon_pm_late_init(rdev);
1668
1669 return 0;
1670 }
1671
radeon_modeset_fini(struct radeon_device * rdev)1672 void radeon_modeset_fini(struct radeon_device *rdev)
1673 {
1674 if (rdev->mode_info.mode_config_initialized) {
1675 drm_kms_helper_poll_fini(rdev->ddev);
1676 radeon_hpd_fini(rdev);
1677 drm_crtc_force_disable_all(rdev->ddev);
1678 radeon_fbdev_fini(rdev);
1679 radeon_afmt_fini(rdev);
1680 drm_mode_config_cleanup(rdev->ddev);
1681 rdev->mode_info.mode_config_initialized = false;
1682 }
1683
1684 kfree(rdev->mode_info.bios_hardcoded_edid);
1685
1686 /* free i2c buses */
1687 radeon_i2c_fini(rdev);
1688 }
1689
is_hdtv_mode(const struct drm_display_mode * mode)1690 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1691 {
1692 /* try and guess if this is a tv or a monitor */
1693 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1694 (mode->vdisplay == 576) || /* 576p */
1695 (mode->vdisplay == 720) || /* 720p */
1696 (mode->vdisplay == 1080)) /* 1080p */
1697 return true;
1698 else
1699 return false;
1700 }
1701
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1702 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1703 const struct drm_display_mode *mode,
1704 struct drm_display_mode *adjusted_mode)
1705 {
1706 struct drm_device *dev = crtc->dev;
1707 struct radeon_device *rdev = dev->dev_private;
1708 struct drm_encoder *encoder;
1709 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1710 struct radeon_encoder *radeon_encoder;
1711 struct drm_connector *connector;
1712 struct radeon_connector *radeon_connector;
1713 bool first = true;
1714 u32 src_v = 1, dst_v = 1;
1715 u32 src_h = 1, dst_h = 1;
1716
1717 radeon_crtc->h_border = 0;
1718 radeon_crtc->v_border = 0;
1719
1720 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1721 if (encoder->crtc != crtc)
1722 continue;
1723 radeon_encoder = to_radeon_encoder(encoder);
1724 connector = radeon_get_connector_for_encoder(encoder);
1725 radeon_connector = to_radeon_connector(connector);
1726
1727 if (first) {
1728 /* set scaling */
1729 if (radeon_encoder->rmx_type == RMX_OFF)
1730 radeon_crtc->rmx_type = RMX_OFF;
1731 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1732 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1733 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1734 else
1735 radeon_crtc->rmx_type = RMX_OFF;
1736 /* copy native mode */
1737 memcpy(&radeon_crtc->native_mode,
1738 &radeon_encoder->native_mode,
1739 sizeof(struct drm_display_mode));
1740 src_v = crtc->mode.vdisplay;
1741 dst_v = radeon_crtc->native_mode.vdisplay;
1742 src_h = crtc->mode.hdisplay;
1743 dst_h = radeon_crtc->native_mode.hdisplay;
1744
1745 /* fix up for overscan on hdmi */
1746 if (ASIC_IS_AVIVO(rdev) &&
1747 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1748 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1749 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1750 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1751 is_hdtv_mode(mode)))) {
1752 if (radeon_encoder->underscan_hborder != 0)
1753 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1754 else
1755 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1756 if (radeon_encoder->underscan_vborder != 0)
1757 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1758 else
1759 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1760 radeon_crtc->rmx_type = RMX_FULL;
1761 src_v = crtc->mode.vdisplay;
1762 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1763 src_h = crtc->mode.hdisplay;
1764 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1765 }
1766 first = false;
1767 } else {
1768 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1769 /* WARNING: Right now this can't happen but
1770 * in the future we need to check that scaling
1771 * are consistent across different encoder
1772 * (ie all encoder can work with the same
1773 * scaling).
1774 */
1775 DRM_ERROR("Scaling not consistent across encoder.\n");
1776 return false;
1777 }
1778 }
1779 }
1780 if (radeon_crtc->rmx_type != RMX_OFF) {
1781 fixed20_12 a, b;
1782 a.full = dfixed_const(src_v);
1783 b.full = dfixed_const(dst_v);
1784 radeon_crtc->vsc.full = dfixed_div(a, b);
1785 a.full = dfixed_const(src_h);
1786 b.full = dfixed_const(dst_h);
1787 radeon_crtc->hsc.full = dfixed_div(a, b);
1788 } else {
1789 radeon_crtc->vsc.full = dfixed_const(1);
1790 radeon_crtc->hsc.full = dfixed_const(1);
1791 }
1792 return true;
1793 }
1794
1795 /*
1796 * Retrieve current video scanout position of crtc on a given gpu, and
1797 * an optional accurate timestamp of when query happened.
1798 *
1799 * \param dev Device to query.
1800 * \param crtc Crtc to query.
1801 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1802 * For driver internal use only also supports these flags:
1803 *
1804 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1805 * of a fudged earlier start of vblank.
1806 *
1807 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1808 * fudged earlier start of vblank in *vpos and the distance
1809 * to true start of vblank in *hpos.
1810 *
1811 * \param *vpos Location where vertical scanout position should be stored.
1812 * \param *hpos Location where horizontal scanout position should go.
1813 * \param *stime Target location for timestamp taken immediately before
1814 * scanout position query. Can be NULL to skip timestamp.
1815 * \param *etime Target location for timestamp taken immediately after
1816 * scanout position query. Can be NULL to skip timestamp.
1817 *
1818 * Returns vpos as a positive number while in active scanout area.
1819 * Returns vpos as a negative number inside vblank, counting the number
1820 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1821 * until start of active scanout / end of vblank."
1822 *
1823 * \return Flags, or'ed together as follows:
1824 *
1825 * DRM_SCANOUTPOS_VALID = Query successful.
1826 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1827 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1828 * this flag means that returned position may be offset by a constant but
1829 * unknown small number of scanlines wrt. real scanout position.
1830 *
1831 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1832 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1833 unsigned int flags, int *vpos, int *hpos,
1834 ktime_t *stime, ktime_t *etime,
1835 const struct drm_display_mode *mode)
1836 {
1837 u32 stat_crtc = 0, vbl = 0, position = 0;
1838 int vbl_start, vbl_end, vtotal, ret = 0;
1839 bool in_vbl = true;
1840
1841 struct radeon_device *rdev = dev->dev_private;
1842
1843 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1844
1845 /* Get optional system timestamp before query. */
1846 if (stime)
1847 *stime = ktime_get();
1848
1849 if (ASIC_IS_DCE4(rdev)) {
1850 if (pipe == 0) {
1851 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1852 EVERGREEN_CRTC0_REGISTER_OFFSET);
1853 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1854 EVERGREEN_CRTC0_REGISTER_OFFSET);
1855 ret |= DRM_SCANOUTPOS_VALID;
1856 }
1857 if (pipe == 1) {
1858 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1859 EVERGREEN_CRTC1_REGISTER_OFFSET);
1860 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1861 EVERGREEN_CRTC1_REGISTER_OFFSET);
1862 ret |= DRM_SCANOUTPOS_VALID;
1863 }
1864 if (pipe == 2) {
1865 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1866 EVERGREEN_CRTC2_REGISTER_OFFSET);
1867 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1868 EVERGREEN_CRTC2_REGISTER_OFFSET);
1869 ret |= DRM_SCANOUTPOS_VALID;
1870 }
1871 if (pipe == 3) {
1872 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1873 EVERGREEN_CRTC3_REGISTER_OFFSET);
1874 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1875 EVERGREEN_CRTC3_REGISTER_OFFSET);
1876 ret |= DRM_SCANOUTPOS_VALID;
1877 }
1878 if (pipe == 4) {
1879 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1880 EVERGREEN_CRTC4_REGISTER_OFFSET);
1881 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1882 EVERGREEN_CRTC4_REGISTER_OFFSET);
1883 ret |= DRM_SCANOUTPOS_VALID;
1884 }
1885 if (pipe == 5) {
1886 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1887 EVERGREEN_CRTC5_REGISTER_OFFSET);
1888 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1889 EVERGREEN_CRTC5_REGISTER_OFFSET);
1890 ret |= DRM_SCANOUTPOS_VALID;
1891 }
1892 } else if (ASIC_IS_AVIVO(rdev)) {
1893 if (pipe == 0) {
1894 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1895 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1896 ret |= DRM_SCANOUTPOS_VALID;
1897 }
1898 if (pipe == 1) {
1899 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1900 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1901 ret |= DRM_SCANOUTPOS_VALID;
1902 }
1903 } else {
1904 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1905 if (pipe == 0) {
1906 /* Assume vbl_end == 0, get vbl_start from
1907 * upper 16 bits.
1908 */
1909 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1910 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1911 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1912 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1913 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1914 if (!(stat_crtc & 1))
1915 in_vbl = false;
1916
1917 ret |= DRM_SCANOUTPOS_VALID;
1918 }
1919 if (pipe == 1) {
1920 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1921 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1922 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1923 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1924 if (!(stat_crtc & 1))
1925 in_vbl = false;
1926
1927 ret |= DRM_SCANOUTPOS_VALID;
1928 }
1929 }
1930
1931 /* Get optional system timestamp after query. */
1932 if (etime)
1933 *etime = ktime_get();
1934
1935 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1936
1937 /* Decode into vertical and horizontal scanout position. */
1938 *vpos = position & 0x1fff;
1939 *hpos = (position >> 16) & 0x1fff;
1940
1941 /* Valid vblank area boundaries from gpu retrieved? */
1942 if (vbl > 0) {
1943 /* Yes: Decode. */
1944 ret |= DRM_SCANOUTPOS_ACCURATE;
1945 vbl_start = vbl & 0x1fff;
1946 vbl_end = (vbl >> 16) & 0x1fff;
1947 }
1948 else {
1949 /* No: Fake something reasonable which gives at least ok results. */
1950 vbl_start = mode->crtc_vdisplay;
1951 vbl_end = 0;
1952 }
1953
1954 /* Called from driver internal vblank counter query code? */
1955 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1956 /* Caller wants distance from real vbl_start in *hpos */
1957 *hpos = *vpos - vbl_start;
1958 }
1959
1960 /* Fudge vblank to start a few scanlines earlier to handle the
1961 * problem that vblank irqs fire a few scanlines before start
1962 * of vblank. Some driver internal callers need the true vblank
1963 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1964 *
1965 * The cause of the "early" vblank irq is that the irq is triggered
1966 * by the line buffer logic when the line buffer read position enters
1967 * the vblank, whereas our crtc scanout position naturally lags the
1968 * line buffer read position.
1969 */
1970 if (!(flags & USE_REAL_VBLANKSTART))
1971 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1972
1973 /* Test scanout position against vblank region. */
1974 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1975 in_vbl = false;
1976
1977 /* In vblank? */
1978 if (in_vbl)
1979 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1980
1981 /* Called from driver internal vblank counter query code? */
1982 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1983 /* Caller wants distance from fudged earlier vbl_start */
1984 *vpos -= vbl_start;
1985 return ret;
1986 }
1987
1988 /* Check if inside vblank area and apply corrective offsets:
1989 * vpos will then be >=0 in video scanout area, but negative
1990 * within vblank area, counting down the number of lines until
1991 * start of scanout.
1992 */
1993
1994 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1995 if (in_vbl && (*vpos >= vbl_start)) {
1996 vtotal = mode->crtc_vtotal;
1997 *vpos = *vpos - vtotal;
1998 }
1999
2000 /* Correct for shifted end of vbl at vbl_end. */
2001 *vpos = *vpos - vbl_end;
2002
2003 return ret;
2004 }
2005