1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ser_defs_h 3 #define __ser_defs_h 4 5 /* 6 * This file is autogenerated from 7 * file: ../../inst/ser/rtl/ser_regs.r 8 * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp 9 * last modfied: Mon Apr 11 16:09:21 2005 10 * 11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r 12 * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ 13 * Any changes here will be lost. 14 * 15 * -*- buffer-read-only: t -*- 16 */ 17 /* Main access macros */ 18 #ifndef REG_RD 19 #define REG_RD( scope, inst, reg ) \ 20 REG_READ( reg_##scope##_##reg, \ 21 (inst) + REG_RD_ADDR_##scope##_##reg ) 22 #endif 23 24 #ifndef REG_WR 25 #define REG_WR( scope, inst, reg, val ) \ 26 REG_WRITE( reg_##scope##_##reg, \ 27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 28 #endif 29 30 #ifndef REG_RD_VECT 31 #define REG_RD_VECT( scope, inst, reg, index ) \ 32 REG_READ( reg_##scope##_##reg, \ 33 (inst) + REG_RD_ADDR_##scope##_##reg + \ 34 (index) * STRIDE_##scope##_##reg ) 35 #endif 36 37 #ifndef REG_WR_VECT 38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 39 REG_WRITE( reg_##scope##_##reg, \ 40 (inst) + REG_WR_ADDR_##scope##_##reg + \ 41 (index) * STRIDE_##scope##_##reg, (val) ) 42 #endif 43 44 #ifndef REG_RD_INT 45 #define REG_RD_INT( scope, inst, reg ) \ 46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 47 #endif 48 49 #ifndef REG_WR_INT 50 #define REG_WR_INT( scope, inst, reg, val ) \ 51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 52 #endif 53 54 #ifndef REG_RD_INT_VECT 55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 57 (index) * STRIDE_##scope##_##reg ) 58 #endif 59 60 #ifndef REG_WR_INT_VECT 61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 63 (index) * STRIDE_##scope##_##reg, (val) ) 64 #endif 65 66 #ifndef REG_TYPE_CONV 67 #define REG_TYPE_CONV( type, orgtype, val ) \ 68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 69 #endif 70 71 #ifndef reg_page_size 72 #define reg_page_size 8192 73 #endif 74 75 #ifndef REG_ADDR 76 #define REG_ADDR( scope, inst, reg ) \ 77 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 78 #endif 79 80 #ifndef REG_ADDR_VECT 81 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 83 (index) * STRIDE_##scope##_##reg ) 84 #endif 85 86 /* C-code for register scope ser */ 87 88 /* Register rw_tr_ctrl, scope ser, type rw */ 89 typedef struct { 90 unsigned int base_freq : 3; 91 unsigned int en : 1; 92 unsigned int par : 2; 93 unsigned int par_en : 1; 94 unsigned int data_bits : 1; 95 unsigned int stop_bits : 1; 96 unsigned int stop : 1; 97 unsigned int rts_delay : 3; 98 unsigned int rts_setup : 1; 99 unsigned int auto_rts : 1; 100 unsigned int txd : 1; 101 unsigned int auto_cts : 1; 102 unsigned int dummy1 : 15; 103 } reg_ser_rw_tr_ctrl; 104 #define REG_RD_ADDR_ser_rw_tr_ctrl 0 105 #define REG_WR_ADDR_ser_rw_tr_ctrl 0 106 107 /* Register rw_tr_dma_en, scope ser, type rw */ 108 typedef struct { 109 unsigned int en : 1; 110 unsigned int dummy1 : 31; 111 } reg_ser_rw_tr_dma_en; 112 #define REG_RD_ADDR_ser_rw_tr_dma_en 4 113 #define REG_WR_ADDR_ser_rw_tr_dma_en 4 114 115 /* Register rw_rec_ctrl, scope ser, type rw */ 116 typedef struct { 117 unsigned int base_freq : 3; 118 unsigned int en : 1; 119 unsigned int par : 2; 120 unsigned int par_en : 1; 121 unsigned int data_bits : 1; 122 unsigned int dma_mode : 1; 123 unsigned int dma_err : 1; 124 unsigned int sampling : 1; 125 unsigned int timeout : 3; 126 unsigned int auto_eop : 1; 127 unsigned int half_duplex : 1; 128 unsigned int rts_n : 1; 129 unsigned int loopback : 1; 130 unsigned int dummy1 : 14; 131 } reg_ser_rw_rec_ctrl; 132 #define REG_RD_ADDR_ser_rw_rec_ctrl 8 133 #define REG_WR_ADDR_ser_rw_rec_ctrl 8 134 135 /* Register rw_tr_baud_div, scope ser, type rw */ 136 typedef struct { 137 unsigned int div : 16; 138 unsigned int dummy1 : 16; 139 } reg_ser_rw_tr_baud_div; 140 #define REG_RD_ADDR_ser_rw_tr_baud_div 12 141 #define REG_WR_ADDR_ser_rw_tr_baud_div 12 142 143 /* Register rw_rec_baud_div, scope ser, type rw */ 144 typedef struct { 145 unsigned int div : 16; 146 unsigned int dummy1 : 16; 147 } reg_ser_rw_rec_baud_div; 148 #define REG_RD_ADDR_ser_rw_rec_baud_div 16 149 #define REG_WR_ADDR_ser_rw_rec_baud_div 16 150 151 /* Register rw_xoff, scope ser, type rw */ 152 typedef struct { 153 unsigned int chr : 8; 154 unsigned int automatic : 1; 155 unsigned int dummy1 : 23; 156 } reg_ser_rw_xoff; 157 #define REG_RD_ADDR_ser_rw_xoff 20 158 #define REG_WR_ADDR_ser_rw_xoff 20 159 160 /* Register rw_xoff_clr, scope ser, type rw */ 161 typedef struct { 162 unsigned int clr : 1; 163 unsigned int dummy1 : 31; 164 } reg_ser_rw_xoff_clr; 165 #define REG_RD_ADDR_ser_rw_xoff_clr 24 166 #define REG_WR_ADDR_ser_rw_xoff_clr 24 167 168 /* Register rw_dout, scope ser, type rw */ 169 typedef struct { 170 unsigned int data : 8; 171 unsigned int dummy1 : 24; 172 } reg_ser_rw_dout; 173 #define REG_RD_ADDR_ser_rw_dout 28 174 #define REG_WR_ADDR_ser_rw_dout 28 175 176 /* Register rs_stat_din, scope ser, type rs */ 177 typedef struct { 178 unsigned int data : 8; 179 unsigned int dummy1 : 8; 180 unsigned int dav : 1; 181 unsigned int framing_err : 1; 182 unsigned int par_err : 1; 183 unsigned int orun : 1; 184 unsigned int rec_err : 1; 185 unsigned int rxd : 1; 186 unsigned int tr_idle : 1; 187 unsigned int tr_empty : 1; 188 unsigned int tr_rdy : 1; 189 unsigned int cts_n : 1; 190 unsigned int xoff_detect : 1; 191 unsigned int rts_n : 1; 192 unsigned int txd : 1; 193 unsigned int dummy2 : 3; 194 } reg_ser_rs_stat_din; 195 #define REG_RD_ADDR_ser_rs_stat_din 32 196 197 /* Register r_stat_din, scope ser, type r */ 198 typedef struct { 199 unsigned int data : 8; 200 unsigned int dummy1 : 8; 201 unsigned int dav : 1; 202 unsigned int framing_err : 1; 203 unsigned int par_err : 1; 204 unsigned int orun : 1; 205 unsigned int rec_err : 1; 206 unsigned int rxd : 1; 207 unsigned int tr_idle : 1; 208 unsigned int tr_empty : 1; 209 unsigned int tr_rdy : 1; 210 unsigned int cts_n : 1; 211 unsigned int xoff_detect : 1; 212 unsigned int rts_n : 1; 213 unsigned int txd : 1; 214 unsigned int dummy2 : 3; 215 } reg_ser_r_stat_din; 216 #define REG_RD_ADDR_ser_r_stat_din 36 217 218 /* Register rw_rec_eop, scope ser, type rw */ 219 typedef struct { 220 unsigned int set : 1; 221 unsigned int dummy1 : 31; 222 } reg_ser_rw_rec_eop; 223 #define REG_RD_ADDR_ser_rw_rec_eop 40 224 #define REG_WR_ADDR_ser_rw_rec_eop 40 225 226 /* Register rw_intr_mask, scope ser, type rw */ 227 typedef struct { 228 unsigned int tr_rdy : 1; 229 unsigned int tr_empty : 1; 230 unsigned int tr_idle : 1; 231 unsigned int dav : 1; 232 unsigned int dummy1 : 28; 233 } reg_ser_rw_intr_mask; 234 #define REG_RD_ADDR_ser_rw_intr_mask 44 235 #define REG_WR_ADDR_ser_rw_intr_mask 44 236 237 /* Register rw_ack_intr, scope ser, type rw */ 238 typedef struct { 239 unsigned int tr_rdy : 1; 240 unsigned int tr_empty : 1; 241 unsigned int tr_idle : 1; 242 unsigned int dav : 1; 243 unsigned int dummy1 : 28; 244 } reg_ser_rw_ack_intr; 245 #define REG_RD_ADDR_ser_rw_ack_intr 48 246 #define REG_WR_ADDR_ser_rw_ack_intr 48 247 248 /* Register r_intr, scope ser, type r */ 249 typedef struct { 250 unsigned int tr_rdy : 1; 251 unsigned int tr_empty : 1; 252 unsigned int tr_idle : 1; 253 unsigned int dav : 1; 254 unsigned int dummy1 : 28; 255 } reg_ser_r_intr; 256 #define REG_RD_ADDR_ser_r_intr 52 257 258 /* Register r_masked_intr, scope ser, type r */ 259 typedef struct { 260 unsigned int tr_rdy : 1; 261 unsigned int tr_empty : 1; 262 unsigned int tr_idle : 1; 263 unsigned int dav : 1; 264 unsigned int dummy1 : 28; 265 } reg_ser_r_masked_intr; 266 #define REG_RD_ADDR_ser_r_masked_intr 56 267 268 269 /* Constants */ 270 enum { 271 regk_ser_active = 0x00000000, 272 regk_ser_bits1 = 0x00000000, 273 regk_ser_bits2 = 0x00000001, 274 regk_ser_bits7 = 0x00000001, 275 regk_ser_bits8 = 0x00000000, 276 regk_ser_del0_5 = 0x00000000, 277 regk_ser_del1 = 0x00000001, 278 regk_ser_del1_5 = 0x00000002, 279 regk_ser_del2 = 0x00000003, 280 regk_ser_del2_5 = 0x00000004, 281 regk_ser_del3 = 0x00000005, 282 regk_ser_del3_5 = 0x00000006, 283 regk_ser_del4 = 0x00000007, 284 regk_ser_even = 0x00000000, 285 regk_ser_ext = 0x00000001, 286 regk_ser_f100 = 0x00000007, 287 regk_ser_f29_493 = 0x00000004, 288 regk_ser_f32 = 0x00000005, 289 regk_ser_f32_768 = 0x00000006, 290 regk_ser_ignore = 0x00000001, 291 regk_ser_inactive = 0x00000001, 292 regk_ser_majority = 0x00000001, 293 regk_ser_mark = 0x00000002, 294 regk_ser_middle = 0x00000000, 295 regk_ser_no = 0x00000000, 296 regk_ser_odd = 0x00000001, 297 regk_ser_off = 0x00000000, 298 regk_ser_rw_intr_mask_default = 0x00000000, 299 regk_ser_rw_rec_baud_div_default = 0x00000000, 300 regk_ser_rw_rec_ctrl_default = 0x00010000, 301 regk_ser_rw_tr_baud_div_default = 0x00000000, 302 regk_ser_rw_tr_ctrl_default = 0x00008000, 303 regk_ser_rw_tr_dma_en_default = 0x00000000, 304 regk_ser_rw_xoff_default = 0x00000000, 305 regk_ser_space = 0x00000003, 306 regk_ser_stop = 0x00000000, 307 regk_ser_yes = 0x00000001 308 }; 309 #endif /* __ser_defs_h */ 310