1 /*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <linux/types.h>
19 #include <linux/uuid.h>
20
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
23
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
26
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
30
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33 #define NVME_RDMA_IP_PORT 4420
34
35 #define NVME_NSID_ALL 0xffffffff
36
37 enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40 };
41
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
43 enum {
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49 };
50
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
52 enum {
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56 NVMF_TRTYPE_MAX,
57 };
58
59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
60 enum {
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
64 };
65
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69 enum {
70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
72 };
73
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77 enum {
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
83 };
84
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88 enum {
89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
90 };
91
92 #define NVME_AQ_DEPTH 32
93
94 enum {
95 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
96 NVME_REG_VS = 0x0008, /* Version */
97 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
98 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
99 NVME_REG_CC = 0x0014, /* Controller Configuration */
100 NVME_REG_CSTS = 0x001c, /* Controller Status */
101 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
102 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
103 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
104 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
105 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
106 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
107 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
108 };
109
110 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
111 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
112 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
113 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
114 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
115 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
116
117 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
118 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
119 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
120 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
121
122 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
123 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
124 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
125 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
126 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
127
128 /*
129 * Submission and Completion Queue Entry Sizes for the NVM command set.
130 * (In bytes and specified as a power of two (2^n)).
131 */
132 #define NVME_NVM_IOSQES 6
133 #define NVME_NVM_IOCQES 4
134
135 enum {
136 NVME_CC_ENABLE = 1 << 0,
137 NVME_CC_CSS_NVM = 0 << 4,
138 NVME_CC_EN_SHIFT = 0,
139 NVME_CC_CSS_SHIFT = 4,
140 NVME_CC_MPS_SHIFT = 7,
141 NVME_CC_AMS_SHIFT = 11,
142 NVME_CC_SHN_SHIFT = 14,
143 NVME_CC_IOSQES_SHIFT = 16,
144 NVME_CC_IOCQES_SHIFT = 20,
145 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
146 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
147 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
148 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
149 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
150 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
151 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
152 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
153 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
154 NVME_CSTS_RDY = 1 << 0,
155 NVME_CSTS_CFS = 1 << 1,
156 NVME_CSTS_NSSRO = 1 << 4,
157 NVME_CSTS_PP = 1 << 5,
158 NVME_CSTS_SHST_NORMAL = 0 << 2,
159 NVME_CSTS_SHST_OCCUR = 1 << 2,
160 NVME_CSTS_SHST_CMPLT = 2 << 2,
161 NVME_CSTS_SHST_MASK = 3 << 2,
162 };
163
164 struct nvme_id_power_state {
165 __le16 max_power; /* centiwatts */
166 __u8 rsvd2;
167 __u8 flags;
168 __le32 entry_lat; /* microseconds */
169 __le32 exit_lat; /* microseconds */
170 __u8 read_tput;
171 __u8 read_lat;
172 __u8 write_tput;
173 __u8 write_lat;
174 __le16 idle_power;
175 __u8 idle_scale;
176 __u8 rsvd19;
177 __le16 active_power;
178 __u8 active_work_scale;
179 __u8 rsvd23[9];
180 };
181
182 enum {
183 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
184 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
185 };
186
187 struct nvme_id_ctrl {
188 __le16 vid;
189 __le16 ssvid;
190 char sn[20];
191 char mn[40];
192 char fr[8];
193 __u8 rab;
194 __u8 ieee[3];
195 __u8 cmic;
196 __u8 mdts;
197 __le16 cntlid;
198 __le32 ver;
199 __le32 rtd3r;
200 __le32 rtd3e;
201 __le32 oaes;
202 __le32 ctratt;
203 __u8 rsvd100[156];
204 __le16 oacs;
205 __u8 acl;
206 __u8 aerl;
207 __u8 frmw;
208 __u8 lpa;
209 __u8 elpe;
210 __u8 npss;
211 __u8 avscc;
212 __u8 apsta;
213 __le16 wctemp;
214 __le16 cctemp;
215 __le16 mtfa;
216 __le32 hmpre;
217 __le32 hmmin;
218 __u8 tnvmcap[16];
219 __u8 unvmcap[16];
220 __le32 rpmbs;
221 __le16 edstt;
222 __u8 dsto;
223 __u8 fwug;
224 __le16 kas;
225 __le16 hctma;
226 __le16 mntmt;
227 __le16 mxtmt;
228 __le32 sanicap;
229 __le32 hmminds;
230 __le16 hmmaxd;
231 __u8 rsvd338[174];
232 __u8 sqes;
233 __u8 cqes;
234 __le16 maxcmd;
235 __le32 nn;
236 __le16 oncs;
237 __le16 fuses;
238 __u8 fna;
239 __u8 vwc;
240 __le16 awun;
241 __le16 awupf;
242 __u8 nvscc;
243 __u8 rsvd531;
244 __le16 acwu;
245 __u8 rsvd534[2];
246 __le32 sgls;
247 __u8 rsvd540[228];
248 char subnqn[256];
249 __u8 rsvd1024[768];
250 __le32 ioccsz;
251 __le32 iorcsz;
252 __le16 icdoff;
253 __u8 ctrattr;
254 __u8 msdbd;
255 __u8 rsvd1804[244];
256 struct nvme_id_power_state psd[32];
257 __u8 vs[1024];
258 };
259
260 enum {
261 NVME_CTRL_ONCS_COMPARE = 1 << 0,
262 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
263 NVME_CTRL_ONCS_DSM = 1 << 2,
264 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
265 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
266 NVME_CTRL_VWC_PRESENT = 1 << 0,
267 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
268 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
269 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
270 };
271
272 struct nvme_lbaf {
273 __le16 ms;
274 __u8 ds;
275 __u8 rp;
276 };
277
278 struct nvme_id_ns {
279 __le64 nsze;
280 __le64 ncap;
281 __le64 nuse;
282 __u8 nsfeat;
283 __u8 nlbaf;
284 __u8 flbas;
285 __u8 mc;
286 __u8 dpc;
287 __u8 dps;
288 __u8 nmic;
289 __u8 rescap;
290 __u8 fpi;
291 __u8 rsvd33;
292 __le16 nawun;
293 __le16 nawupf;
294 __le16 nacwu;
295 __le16 nabsn;
296 __le16 nabo;
297 __le16 nabspf;
298 __le16 noiob;
299 __u8 nvmcap[16];
300 __u8 rsvd64[40];
301 __u8 nguid[16];
302 __u8 eui64[8];
303 struct nvme_lbaf lbaf[16];
304 __u8 rsvd192[192];
305 __u8 vs[3712];
306 };
307
308 enum {
309 NVME_ID_CNS_NS = 0x00,
310 NVME_ID_CNS_CTRL = 0x01,
311 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
312 NVME_ID_CNS_NS_DESC_LIST = 0x03,
313 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
314 NVME_ID_CNS_NS_PRESENT = 0x11,
315 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
316 NVME_ID_CNS_CTRL_LIST = 0x13,
317 };
318
319 enum {
320 NVME_DIR_IDENTIFY = 0x00,
321 NVME_DIR_STREAMS = 0x01,
322 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
323 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
324 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
325 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
326 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
327 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
328 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
329 NVME_DIR_ENDIR = 0x01,
330 };
331
332 enum {
333 NVME_NS_FEAT_THIN = 1 << 0,
334 NVME_NS_FLBAS_LBA_MASK = 0xf,
335 NVME_NS_FLBAS_META_EXT = 0x10,
336 NVME_LBAF_RP_BEST = 0,
337 NVME_LBAF_RP_BETTER = 1,
338 NVME_LBAF_RP_GOOD = 2,
339 NVME_LBAF_RP_DEGRADED = 3,
340 NVME_NS_DPC_PI_LAST = 1 << 4,
341 NVME_NS_DPC_PI_FIRST = 1 << 3,
342 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
343 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
344 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
345 NVME_NS_DPS_PI_FIRST = 1 << 3,
346 NVME_NS_DPS_PI_MASK = 0x7,
347 NVME_NS_DPS_PI_TYPE1 = 1,
348 NVME_NS_DPS_PI_TYPE2 = 2,
349 NVME_NS_DPS_PI_TYPE3 = 3,
350 };
351
352 struct nvme_ns_id_desc {
353 __u8 nidt;
354 __u8 nidl;
355 __le16 reserved;
356 };
357
358 #define NVME_NIDT_EUI64_LEN 8
359 #define NVME_NIDT_NGUID_LEN 16
360 #define NVME_NIDT_UUID_LEN 16
361
362 enum {
363 NVME_NIDT_EUI64 = 0x01,
364 NVME_NIDT_NGUID = 0x02,
365 NVME_NIDT_UUID = 0x03,
366 };
367
368 struct nvme_smart_log {
369 __u8 critical_warning;
370 __u8 temperature[2];
371 __u8 avail_spare;
372 __u8 spare_thresh;
373 __u8 percent_used;
374 __u8 rsvd6[26];
375 __u8 data_units_read[16];
376 __u8 data_units_written[16];
377 __u8 host_reads[16];
378 __u8 host_writes[16];
379 __u8 ctrl_busy_time[16];
380 __u8 power_cycles[16];
381 __u8 power_on_hours[16];
382 __u8 unsafe_shutdowns[16];
383 __u8 media_errors[16];
384 __u8 num_err_log_entries[16];
385 __le32 warning_temp_time;
386 __le32 critical_comp_time;
387 __le16 temp_sensor[8];
388 __u8 rsvd216[296];
389 };
390
391 struct nvme_fw_slot_info_log {
392 __u8 afi;
393 __u8 rsvd1[7];
394 __le64 frs[7];
395 __u8 rsvd64[448];
396 };
397
398 enum {
399 NVME_SMART_CRIT_SPARE = 1 << 0,
400 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
401 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
402 NVME_SMART_CRIT_MEDIA = 1 << 3,
403 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
404 };
405
406 enum {
407 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
408 NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
409 };
410
411 struct nvme_lba_range_type {
412 __u8 type;
413 __u8 attributes;
414 __u8 rsvd2[14];
415 __u64 slba;
416 __u64 nlb;
417 __u8 guid[16];
418 __u8 rsvd48[16];
419 };
420
421 enum {
422 NVME_LBART_TYPE_FS = 0x01,
423 NVME_LBART_TYPE_RAID = 0x02,
424 NVME_LBART_TYPE_CACHE = 0x03,
425 NVME_LBART_TYPE_SWAP = 0x04,
426
427 NVME_LBART_ATTRIB_TEMP = 1 << 0,
428 NVME_LBART_ATTRIB_HIDE = 1 << 1,
429 };
430
431 struct nvme_reservation_status {
432 __le32 gen;
433 __u8 rtype;
434 __u8 regctl[2];
435 __u8 resv5[2];
436 __u8 ptpls;
437 __u8 resv10[13];
438 struct {
439 __le16 cntlid;
440 __u8 rcsts;
441 __u8 resv3[5];
442 __le64 hostid;
443 __le64 rkey;
444 } regctl_ds[];
445 };
446
447 enum nvme_async_event_type {
448 NVME_AER_TYPE_ERROR = 0,
449 NVME_AER_TYPE_SMART = 1,
450 NVME_AER_TYPE_NOTICE = 2,
451 };
452
453 /* I/O commands */
454
455 enum nvme_opcode {
456 nvme_cmd_flush = 0x00,
457 nvme_cmd_write = 0x01,
458 nvme_cmd_read = 0x02,
459 nvme_cmd_write_uncor = 0x04,
460 nvme_cmd_compare = 0x05,
461 nvme_cmd_write_zeroes = 0x08,
462 nvme_cmd_dsm = 0x09,
463 nvme_cmd_resv_register = 0x0d,
464 nvme_cmd_resv_report = 0x0e,
465 nvme_cmd_resv_acquire = 0x11,
466 nvme_cmd_resv_release = 0x15,
467 };
468
469 /*
470 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
471 *
472 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
473 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
474 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
475 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
476 * request subtype
477 */
478 enum {
479 NVME_SGL_FMT_ADDRESS = 0x00,
480 NVME_SGL_FMT_OFFSET = 0x01,
481 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
482 NVME_SGL_FMT_INVALIDATE = 0x0f,
483 };
484
485 /*
486 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
487 *
488 * For struct nvme_sgl_desc:
489 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
490 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
491 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
492 *
493 * For struct nvme_keyed_sgl_desc:
494 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
495 *
496 * Transport-specific SGL types:
497 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
498 */
499 enum {
500 NVME_SGL_FMT_DATA_DESC = 0x00,
501 NVME_SGL_FMT_SEG_DESC = 0x02,
502 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
503 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
504 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
505 };
506
507 struct nvme_sgl_desc {
508 __le64 addr;
509 __le32 length;
510 __u8 rsvd[3];
511 __u8 type;
512 };
513
514 struct nvme_keyed_sgl_desc {
515 __le64 addr;
516 __u8 length[3];
517 __u8 key[4];
518 __u8 type;
519 };
520
521 union nvme_data_ptr {
522 struct {
523 __le64 prp1;
524 __le64 prp2;
525 };
526 struct nvme_sgl_desc sgl;
527 struct nvme_keyed_sgl_desc ksgl;
528 };
529
530 /*
531 * Lowest two bits of our flags field (FUSE field in the spec):
532 *
533 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
534 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
535 *
536 * Highest two bits in our flags field (PSDT field in the spec):
537 *
538 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
539 * If used, MPTR contains addr of single physical buffer (byte aligned).
540 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
541 * If used, MPTR contains an address of an SGL segment containing
542 * exactly 1 SGL descriptor (qword aligned).
543 */
544 enum {
545 NVME_CMD_FUSE_FIRST = (1 << 0),
546 NVME_CMD_FUSE_SECOND = (1 << 1),
547
548 NVME_CMD_SGL_METABUF = (1 << 6),
549 NVME_CMD_SGL_METASEG = (1 << 7),
550 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
551 };
552
553 struct nvme_common_command {
554 __u8 opcode;
555 __u8 flags;
556 __u16 command_id;
557 __le32 nsid;
558 __le32 cdw2[2];
559 __le64 metadata;
560 union nvme_data_ptr dptr;
561 __le32 cdw10[6];
562 };
563
564 struct nvme_rw_command {
565 __u8 opcode;
566 __u8 flags;
567 __u16 command_id;
568 __le32 nsid;
569 __u64 rsvd2;
570 __le64 metadata;
571 union nvme_data_ptr dptr;
572 __le64 slba;
573 __le16 length;
574 __le16 control;
575 __le32 dsmgmt;
576 __le32 reftag;
577 __le16 apptag;
578 __le16 appmask;
579 };
580
581 enum {
582 NVME_RW_LR = 1 << 15,
583 NVME_RW_FUA = 1 << 14,
584 NVME_RW_DSM_FREQ_UNSPEC = 0,
585 NVME_RW_DSM_FREQ_TYPICAL = 1,
586 NVME_RW_DSM_FREQ_RARE = 2,
587 NVME_RW_DSM_FREQ_READS = 3,
588 NVME_RW_DSM_FREQ_WRITES = 4,
589 NVME_RW_DSM_FREQ_RW = 5,
590 NVME_RW_DSM_FREQ_ONCE = 6,
591 NVME_RW_DSM_FREQ_PREFETCH = 7,
592 NVME_RW_DSM_FREQ_TEMP = 8,
593 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
594 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
595 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
596 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
597 NVME_RW_DSM_SEQ_REQ = 1 << 6,
598 NVME_RW_DSM_COMPRESSED = 1 << 7,
599 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
600 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
601 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
602 NVME_RW_PRINFO_PRACT = 1 << 13,
603 NVME_RW_DTYPE_STREAMS = 1 << 4,
604 };
605
606 struct nvme_dsm_cmd {
607 __u8 opcode;
608 __u8 flags;
609 __u16 command_id;
610 __le32 nsid;
611 __u64 rsvd2[2];
612 union nvme_data_ptr dptr;
613 __le32 nr;
614 __le32 attributes;
615 __u32 rsvd12[4];
616 };
617
618 enum {
619 NVME_DSMGMT_IDR = 1 << 0,
620 NVME_DSMGMT_IDW = 1 << 1,
621 NVME_DSMGMT_AD = 1 << 2,
622 };
623
624 #define NVME_DSM_MAX_RANGES 256
625
626 struct nvme_dsm_range {
627 __le32 cattr;
628 __le32 nlb;
629 __le64 slba;
630 };
631
632 struct nvme_write_zeroes_cmd {
633 __u8 opcode;
634 __u8 flags;
635 __u16 command_id;
636 __le32 nsid;
637 __u64 rsvd2;
638 __le64 metadata;
639 union nvme_data_ptr dptr;
640 __le64 slba;
641 __le16 length;
642 __le16 control;
643 __le32 dsmgmt;
644 __le32 reftag;
645 __le16 apptag;
646 __le16 appmask;
647 };
648
649 /* Features */
650
651 struct nvme_feat_auto_pst {
652 __le64 entries[32];
653 };
654
655 enum {
656 NVME_HOST_MEM_ENABLE = (1 << 0),
657 NVME_HOST_MEM_RETURN = (1 << 1),
658 };
659
660 /* Admin commands */
661
662 enum nvme_admin_opcode {
663 nvme_admin_delete_sq = 0x00,
664 nvme_admin_create_sq = 0x01,
665 nvme_admin_get_log_page = 0x02,
666 nvme_admin_delete_cq = 0x04,
667 nvme_admin_create_cq = 0x05,
668 nvme_admin_identify = 0x06,
669 nvme_admin_abort_cmd = 0x08,
670 nvme_admin_set_features = 0x09,
671 nvme_admin_get_features = 0x0a,
672 nvme_admin_async_event = 0x0c,
673 nvme_admin_ns_mgmt = 0x0d,
674 nvme_admin_activate_fw = 0x10,
675 nvme_admin_download_fw = 0x11,
676 nvme_admin_ns_attach = 0x15,
677 nvme_admin_keep_alive = 0x18,
678 nvme_admin_directive_send = 0x19,
679 nvme_admin_directive_recv = 0x1a,
680 nvme_admin_dbbuf = 0x7C,
681 nvme_admin_format_nvm = 0x80,
682 nvme_admin_security_send = 0x81,
683 nvme_admin_security_recv = 0x82,
684 };
685
686 enum {
687 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
688 NVME_CQ_IRQ_ENABLED = (1 << 1),
689 NVME_SQ_PRIO_URGENT = (0 << 1),
690 NVME_SQ_PRIO_HIGH = (1 << 1),
691 NVME_SQ_PRIO_MEDIUM = (2 << 1),
692 NVME_SQ_PRIO_LOW = (3 << 1),
693 NVME_FEAT_ARBITRATION = 0x01,
694 NVME_FEAT_POWER_MGMT = 0x02,
695 NVME_FEAT_LBA_RANGE = 0x03,
696 NVME_FEAT_TEMP_THRESH = 0x04,
697 NVME_FEAT_ERR_RECOVERY = 0x05,
698 NVME_FEAT_VOLATILE_WC = 0x06,
699 NVME_FEAT_NUM_QUEUES = 0x07,
700 NVME_FEAT_IRQ_COALESCE = 0x08,
701 NVME_FEAT_IRQ_CONFIG = 0x09,
702 NVME_FEAT_WRITE_ATOMIC = 0x0a,
703 NVME_FEAT_ASYNC_EVENT = 0x0b,
704 NVME_FEAT_AUTO_PST = 0x0c,
705 NVME_FEAT_HOST_MEM_BUF = 0x0d,
706 NVME_FEAT_TIMESTAMP = 0x0e,
707 NVME_FEAT_KATO = 0x0f,
708 NVME_FEAT_SW_PROGRESS = 0x80,
709 NVME_FEAT_HOST_ID = 0x81,
710 NVME_FEAT_RESV_MASK = 0x82,
711 NVME_FEAT_RESV_PERSIST = 0x83,
712 NVME_LOG_ERROR = 0x01,
713 NVME_LOG_SMART = 0x02,
714 NVME_LOG_FW_SLOT = 0x03,
715 NVME_LOG_DISC = 0x70,
716 NVME_LOG_RESERVATION = 0x80,
717 NVME_FWACT_REPL = (0 << 3),
718 NVME_FWACT_REPL_ACTV = (1 << 3),
719 NVME_FWACT_ACTV = (2 << 3),
720 };
721
722 struct nvme_identify {
723 __u8 opcode;
724 __u8 flags;
725 __u16 command_id;
726 __le32 nsid;
727 __u64 rsvd2[2];
728 union nvme_data_ptr dptr;
729 __u8 cns;
730 __u8 rsvd3;
731 __le16 ctrlid;
732 __u32 rsvd11[5];
733 };
734
735 #define NVME_IDENTIFY_DATA_SIZE 4096
736
737 struct nvme_features {
738 __u8 opcode;
739 __u8 flags;
740 __u16 command_id;
741 __le32 nsid;
742 __u64 rsvd2[2];
743 union nvme_data_ptr dptr;
744 __le32 fid;
745 __le32 dword11;
746 __le32 dword12;
747 __le32 dword13;
748 __le32 dword14;
749 __le32 dword15;
750 };
751
752 struct nvme_host_mem_buf_desc {
753 __le64 addr;
754 __le32 size;
755 __u32 rsvd;
756 };
757
758 struct nvme_create_cq {
759 __u8 opcode;
760 __u8 flags;
761 __u16 command_id;
762 __u32 rsvd1[5];
763 __le64 prp1;
764 __u64 rsvd8;
765 __le16 cqid;
766 __le16 qsize;
767 __le16 cq_flags;
768 __le16 irq_vector;
769 __u32 rsvd12[4];
770 };
771
772 struct nvme_create_sq {
773 __u8 opcode;
774 __u8 flags;
775 __u16 command_id;
776 __u32 rsvd1[5];
777 __le64 prp1;
778 __u64 rsvd8;
779 __le16 sqid;
780 __le16 qsize;
781 __le16 sq_flags;
782 __le16 cqid;
783 __u32 rsvd12[4];
784 };
785
786 struct nvme_delete_queue {
787 __u8 opcode;
788 __u8 flags;
789 __u16 command_id;
790 __u32 rsvd1[9];
791 __le16 qid;
792 __u16 rsvd10;
793 __u32 rsvd11[5];
794 };
795
796 struct nvme_abort_cmd {
797 __u8 opcode;
798 __u8 flags;
799 __u16 command_id;
800 __u32 rsvd1[9];
801 __le16 sqid;
802 __u16 cid;
803 __u32 rsvd11[5];
804 };
805
806 struct nvme_download_firmware {
807 __u8 opcode;
808 __u8 flags;
809 __u16 command_id;
810 __u32 rsvd1[5];
811 union nvme_data_ptr dptr;
812 __le32 numd;
813 __le32 offset;
814 __u32 rsvd12[4];
815 };
816
817 struct nvme_format_cmd {
818 __u8 opcode;
819 __u8 flags;
820 __u16 command_id;
821 __le32 nsid;
822 __u64 rsvd2[4];
823 __le32 cdw10;
824 __u32 rsvd11[5];
825 };
826
827 struct nvme_get_log_page_command {
828 __u8 opcode;
829 __u8 flags;
830 __u16 command_id;
831 __le32 nsid;
832 __u64 rsvd2[2];
833 union nvme_data_ptr dptr;
834 __u8 lid;
835 __u8 rsvd10;
836 __le16 numdl;
837 __le16 numdu;
838 __u16 rsvd11;
839 __le32 lpol;
840 __le32 lpou;
841 __u32 rsvd14[2];
842 };
843
844 struct nvme_directive_cmd {
845 __u8 opcode;
846 __u8 flags;
847 __u16 command_id;
848 __le32 nsid;
849 __u64 rsvd2[2];
850 union nvme_data_ptr dptr;
851 __le32 numd;
852 __u8 doper;
853 __u8 dtype;
854 __le16 dspec;
855 __u8 endir;
856 __u8 tdtype;
857 __u16 rsvd15;
858
859 __u32 rsvd16[3];
860 };
861
862 /*
863 * Fabrics subcommands.
864 */
865 enum nvmf_fabrics_opcode {
866 nvme_fabrics_command = 0x7f,
867 };
868
869 enum nvmf_capsule_command {
870 nvme_fabrics_type_property_set = 0x00,
871 nvme_fabrics_type_connect = 0x01,
872 nvme_fabrics_type_property_get = 0x04,
873 };
874
875 struct nvmf_common_command {
876 __u8 opcode;
877 __u8 resv1;
878 __u16 command_id;
879 __u8 fctype;
880 __u8 resv2[35];
881 __u8 ts[24];
882 };
883
884 /*
885 * The legal cntlid range a NVMe Target will provide.
886 * Note that cntlid of value 0 is considered illegal in the fabrics world.
887 * Devices based on earlier specs did not have the subsystem concept;
888 * therefore, those devices had their cntlid value set to 0 as a result.
889 */
890 #define NVME_CNTLID_MIN 1
891 #define NVME_CNTLID_MAX 0xffef
892 #define NVME_CNTLID_DYNAMIC 0xffff
893
894 #define MAX_DISC_LOGS 255
895
896 /* Discovery log page entry */
897 struct nvmf_disc_rsp_page_entry {
898 __u8 trtype;
899 __u8 adrfam;
900 __u8 subtype;
901 __u8 treq;
902 __le16 portid;
903 __le16 cntlid;
904 __le16 asqsz;
905 __u8 resv8[22];
906 char trsvcid[NVMF_TRSVCID_SIZE];
907 __u8 resv64[192];
908 char subnqn[NVMF_NQN_FIELD_LEN];
909 char traddr[NVMF_TRADDR_SIZE];
910 union tsas {
911 char common[NVMF_TSAS_SIZE];
912 struct rdma {
913 __u8 qptype;
914 __u8 prtype;
915 __u8 cms;
916 __u8 resv3[5];
917 __u16 pkey;
918 __u8 resv10[246];
919 } rdma;
920 } tsas;
921 };
922
923 /* Discovery log page header */
924 struct nvmf_disc_rsp_page_hdr {
925 __le64 genctr;
926 __le64 numrec;
927 __le16 recfmt;
928 __u8 resv14[1006];
929 struct nvmf_disc_rsp_page_entry entries[0];
930 };
931
932 struct nvmf_connect_command {
933 __u8 opcode;
934 __u8 resv1;
935 __u16 command_id;
936 __u8 fctype;
937 __u8 resv2[19];
938 union nvme_data_ptr dptr;
939 __le16 recfmt;
940 __le16 qid;
941 __le16 sqsize;
942 __u8 cattr;
943 __u8 resv3;
944 __le32 kato;
945 __u8 resv4[12];
946 };
947
948 struct nvmf_connect_data {
949 uuid_t hostid;
950 __le16 cntlid;
951 char resv4[238];
952 char subsysnqn[NVMF_NQN_FIELD_LEN];
953 char hostnqn[NVMF_NQN_FIELD_LEN];
954 char resv5[256];
955 };
956
957 struct nvmf_property_set_command {
958 __u8 opcode;
959 __u8 resv1;
960 __u16 command_id;
961 __u8 fctype;
962 __u8 resv2[35];
963 __u8 attrib;
964 __u8 resv3[3];
965 __le32 offset;
966 __le64 value;
967 __u8 resv4[8];
968 };
969
970 struct nvmf_property_get_command {
971 __u8 opcode;
972 __u8 resv1;
973 __u16 command_id;
974 __u8 fctype;
975 __u8 resv2[35];
976 __u8 attrib;
977 __u8 resv3[3];
978 __le32 offset;
979 __u8 resv4[16];
980 };
981
982 struct nvme_dbbuf {
983 __u8 opcode;
984 __u8 flags;
985 __u16 command_id;
986 __u32 rsvd1[5];
987 __le64 prp1;
988 __le64 prp2;
989 __u32 rsvd12[6];
990 };
991
992 struct streams_directive_params {
993 __le16 msl;
994 __le16 nssa;
995 __le16 nsso;
996 __u8 rsvd[10];
997 __le32 sws;
998 __le16 sgs;
999 __le16 nsa;
1000 __le16 nso;
1001 __u8 rsvd2[6];
1002 };
1003
1004 struct nvme_command {
1005 union {
1006 struct nvme_common_command common;
1007 struct nvme_rw_command rw;
1008 struct nvme_identify identify;
1009 struct nvme_features features;
1010 struct nvme_create_cq create_cq;
1011 struct nvme_create_sq create_sq;
1012 struct nvme_delete_queue delete_queue;
1013 struct nvme_download_firmware dlfw;
1014 struct nvme_format_cmd format;
1015 struct nvme_dsm_cmd dsm;
1016 struct nvme_write_zeroes_cmd write_zeroes;
1017 struct nvme_abort_cmd abort;
1018 struct nvme_get_log_page_command get_log_page;
1019 struct nvmf_common_command fabrics;
1020 struct nvmf_connect_command connect;
1021 struct nvmf_property_set_command prop_set;
1022 struct nvmf_property_get_command prop_get;
1023 struct nvme_dbbuf dbbuf;
1024 struct nvme_directive_cmd directive;
1025 };
1026 };
1027
nvme_is_write(struct nvme_command * cmd)1028 static inline bool nvme_is_write(struct nvme_command *cmd)
1029 {
1030 /*
1031 * What a mess...
1032 *
1033 * Why can't we simply have a Fabrics In and Fabrics out command?
1034 */
1035 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1036 return cmd->fabrics.fctype & 1;
1037 return cmd->common.opcode & 1;
1038 }
1039
1040 enum {
1041 /*
1042 * Generic Command Status:
1043 */
1044 NVME_SC_SUCCESS = 0x0,
1045 NVME_SC_INVALID_OPCODE = 0x1,
1046 NVME_SC_INVALID_FIELD = 0x2,
1047 NVME_SC_CMDID_CONFLICT = 0x3,
1048 NVME_SC_DATA_XFER_ERROR = 0x4,
1049 NVME_SC_POWER_LOSS = 0x5,
1050 NVME_SC_INTERNAL = 0x6,
1051 NVME_SC_ABORT_REQ = 0x7,
1052 NVME_SC_ABORT_QUEUE = 0x8,
1053 NVME_SC_FUSED_FAIL = 0x9,
1054 NVME_SC_FUSED_MISSING = 0xa,
1055 NVME_SC_INVALID_NS = 0xb,
1056 NVME_SC_CMD_SEQ_ERROR = 0xc,
1057 NVME_SC_SGL_INVALID_LAST = 0xd,
1058 NVME_SC_SGL_INVALID_COUNT = 0xe,
1059 NVME_SC_SGL_INVALID_DATA = 0xf,
1060 NVME_SC_SGL_INVALID_METADATA = 0x10,
1061 NVME_SC_SGL_INVALID_TYPE = 0x11,
1062
1063 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1064 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1065
1066 NVME_SC_LBA_RANGE = 0x80,
1067 NVME_SC_CAP_EXCEEDED = 0x81,
1068 NVME_SC_NS_NOT_READY = 0x82,
1069 NVME_SC_RESERVATION_CONFLICT = 0x83,
1070
1071 /*
1072 * Command Specific Status:
1073 */
1074 NVME_SC_CQ_INVALID = 0x100,
1075 NVME_SC_QID_INVALID = 0x101,
1076 NVME_SC_QUEUE_SIZE = 0x102,
1077 NVME_SC_ABORT_LIMIT = 0x103,
1078 NVME_SC_ABORT_MISSING = 0x104,
1079 NVME_SC_ASYNC_LIMIT = 0x105,
1080 NVME_SC_FIRMWARE_SLOT = 0x106,
1081 NVME_SC_FIRMWARE_IMAGE = 0x107,
1082 NVME_SC_INVALID_VECTOR = 0x108,
1083 NVME_SC_INVALID_LOG_PAGE = 0x109,
1084 NVME_SC_INVALID_FORMAT = 0x10a,
1085 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1086 NVME_SC_INVALID_QUEUE = 0x10c,
1087 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1088 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1089 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1090 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1091 NVME_SC_FW_NEEDS_RESET = 0x111,
1092 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1093 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1094 NVME_SC_OVERLAPPING_RANGE = 0x114,
1095 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1096 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1097 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1098 NVME_SC_NS_IS_PRIVATE = 0x119,
1099 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1100 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1101 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1102
1103 /*
1104 * I/O Command Set Specific - NVM commands:
1105 */
1106 NVME_SC_BAD_ATTRIBUTES = 0x180,
1107 NVME_SC_INVALID_PI = 0x181,
1108 NVME_SC_READ_ONLY = 0x182,
1109 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1110
1111 /*
1112 * I/O Command Set Specific - Fabrics commands:
1113 */
1114 NVME_SC_CONNECT_FORMAT = 0x180,
1115 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1116 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1117 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1118 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1119
1120 NVME_SC_DISCOVERY_RESTART = 0x190,
1121 NVME_SC_AUTH_REQUIRED = 0x191,
1122
1123 /*
1124 * Media and Data Integrity Errors:
1125 */
1126 NVME_SC_WRITE_FAULT = 0x280,
1127 NVME_SC_READ_ERROR = 0x281,
1128 NVME_SC_GUARD_CHECK = 0x282,
1129 NVME_SC_APPTAG_CHECK = 0x283,
1130 NVME_SC_REFTAG_CHECK = 0x284,
1131 NVME_SC_COMPARE_FAILED = 0x285,
1132 NVME_SC_ACCESS_DENIED = 0x286,
1133 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1134
1135 NVME_SC_DNR = 0x4000,
1136 };
1137
1138 struct nvme_completion {
1139 /*
1140 * Used by Admin and Fabrics commands to return data:
1141 */
1142 union nvme_result {
1143 __le16 u16;
1144 __le32 u32;
1145 __le64 u64;
1146 } result;
1147 __le16 sq_head; /* how much of this queue may be reclaimed */
1148 __le16 sq_id; /* submission queue that generated this entry */
1149 __u16 command_id; /* of the command which completed */
1150 __le16 status; /* did the command fail, and if so, why? */
1151 };
1152
1153 #define NVME_VS(major, minor, tertiary) \
1154 (((major) << 16) | ((minor) << 8) | (tertiary))
1155
1156 #define NVME_MAJOR(ver) ((ver) >> 16)
1157 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1158 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1159
1160 #endif /* _LINUX_NVME_H */
1161