1 /*
2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <rdma/ib_mad.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <linux/io.h>
51 #include <linux/module.h>
52 #include <linux/utsname.h>
53 #include <linux/rculist.h>
54 #include <linux/mm.h>
55 #include <linux/vmalloc.h>
56 #include <rdma/opa_addr.h>
57 #include <linux/nospec.h>
58
59 #include "hfi.h"
60 #include "common.h"
61 #include "device.h"
62 #include "trace.h"
63 #include "qp.h"
64 #include "verbs_txreq.h"
65 #include "debugfs.h"
66 #include "vnic.h"
67
68 static unsigned int hfi1_lkey_table_size = 16;
69 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
70 S_IRUGO);
71 MODULE_PARM_DESC(lkey_table_size,
72 "LKEY table size in bits (2^n, 1 <= n <= 23)");
73
74 static unsigned int hfi1_max_pds = 0xFFFF;
75 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
76 MODULE_PARM_DESC(max_pds,
77 "Maximum number of protection domains to support");
78
79 static unsigned int hfi1_max_ahs = 0xFFFF;
80 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
81 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
82
83 unsigned int hfi1_max_cqes = 0x2FFFFF;
84 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
85 MODULE_PARM_DESC(max_cqes,
86 "Maximum number of completion queue entries to support");
87
88 unsigned int hfi1_max_cqs = 0x1FFFF;
89 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
90 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
91
92 unsigned int hfi1_max_qp_wrs = 0x3FFF;
93 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
94 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
95
96 unsigned int hfi1_max_qps = 32768;
97 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
98 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
99
100 unsigned int hfi1_max_sges = 0x60;
101 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
102 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
103
104 unsigned int hfi1_max_mcast_grps = 16384;
105 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
106 MODULE_PARM_DESC(max_mcast_grps,
107 "Maximum number of multicast groups to support");
108
109 unsigned int hfi1_max_mcast_qp_attached = 16;
110 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
111 uint, S_IRUGO);
112 MODULE_PARM_DESC(max_mcast_qp_attached,
113 "Maximum number of attached QPs to support");
114
115 unsigned int hfi1_max_srqs = 1024;
116 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
117 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
118
119 unsigned int hfi1_max_srq_sges = 128;
120 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
121 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
122
123 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
124 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
125 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
126
127 unsigned short piothreshold = 256;
128 module_param(piothreshold, ushort, S_IRUGO);
129 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
130
131 #define COPY_CACHELESS 1
132 #define COPY_ADAPTIVE 2
133 static unsigned int sge_copy_mode;
134 module_param(sge_copy_mode, uint, S_IRUGO);
135 MODULE_PARM_DESC(sge_copy_mode,
136 "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
137
138 static void verbs_sdma_complete(
139 struct sdma_txreq *cookie,
140 int status);
141
142 static int pio_wait(struct rvt_qp *qp,
143 struct send_context *sc,
144 struct hfi1_pkt_state *ps,
145 u32 flag);
146
147 /* Length of buffer to create verbs txreq cache name */
148 #define TXREQ_NAME_LEN 24
149
150 static uint wss_threshold;
151 module_param(wss_threshold, uint, S_IRUGO);
152 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
153 static uint wss_clean_period = 256;
154 module_param(wss_clean_period, uint, S_IRUGO);
155 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
156
157 /* memory working set size */
158 struct hfi1_wss {
159 unsigned long *entries;
160 atomic_t total_count;
161 atomic_t clean_counter;
162 atomic_t clean_entry;
163
164 int threshold;
165 int num_entries;
166 long pages_mask;
167 };
168
169 static struct hfi1_wss wss;
170
hfi1_wss_init(void)171 int hfi1_wss_init(void)
172 {
173 long llc_size;
174 long llc_bits;
175 long table_size;
176 long table_bits;
177
178 /* check for a valid percent range - default to 80 if none or invalid */
179 if (wss_threshold < 1 || wss_threshold > 100)
180 wss_threshold = 80;
181 /* reject a wildly large period */
182 if (wss_clean_period > 1000000)
183 wss_clean_period = 256;
184 /* reject a zero period */
185 if (wss_clean_period == 0)
186 wss_clean_period = 1;
187
188 /*
189 * Calculate the table size - the next power of 2 larger than the
190 * LLC size. LLC size is in KiB.
191 */
192 llc_size = wss_llc_size() * 1024;
193 table_size = roundup_pow_of_two(llc_size);
194
195 /* one bit per page in rounded up table */
196 llc_bits = llc_size / PAGE_SIZE;
197 table_bits = table_size / PAGE_SIZE;
198 wss.pages_mask = table_bits - 1;
199 wss.num_entries = table_bits / BITS_PER_LONG;
200
201 wss.threshold = (llc_bits * wss_threshold) / 100;
202 if (wss.threshold == 0)
203 wss.threshold = 1;
204
205 atomic_set(&wss.clean_counter, wss_clean_period);
206
207 wss.entries = kcalloc(wss.num_entries, sizeof(*wss.entries),
208 GFP_KERNEL);
209 if (!wss.entries) {
210 hfi1_wss_exit();
211 return -ENOMEM;
212 }
213
214 return 0;
215 }
216
hfi1_wss_exit(void)217 void hfi1_wss_exit(void)
218 {
219 /* coded to handle partially initialized and repeat callers */
220 kfree(wss.entries);
221 wss.entries = NULL;
222 }
223
224 /*
225 * Advance the clean counter. When the clean period has expired,
226 * clean an entry.
227 *
228 * This is implemented in atomics to avoid locking. Because multiple
229 * variables are involved, it can be racy which can lead to slightly
230 * inaccurate information. Since this is only a heuristic, this is
231 * OK. Any innaccuracies will clean themselves out as the counter
232 * advances. That said, it is unlikely the entry clean operation will
233 * race - the next possible racer will not start until the next clean
234 * period.
235 *
236 * The clean counter is implemented as a decrement to zero. When zero
237 * is reached an entry is cleaned.
238 */
wss_advance_clean_counter(void)239 static void wss_advance_clean_counter(void)
240 {
241 int entry;
242 int weight;
243 unsigned long bits;
244
245 /* become the cleaner if we decrement the counter to zero */
246 if (atomic_dec_and_test(&wss.clean_counter)) {
247 /*
248 * Set, not add, the clean period. This avoids an issue
249 * where the counter could decrement below the clean period.
250 * Doing a set can result in lost decrements, slowing the
251 * clean advance. Since this a heuristic, this possible
252 * slowdown is OK.
253 *
254 * An alternative is to loop, advancing the counter by a
255 * clean period until the result is > 0. However, this could
256 * lead to several threads keeping another in the clean loop.
257 * This could be mitigated by limiting the number of times
258 * we stay in the loop.
259 */
260 atomic_set(&wss.clean_counter, wss_clean_period);
261
262 /*
263 * Uniquely grab the entry to clean and move to next.
264 * The current entry is always the lower bits of
265 * wss.clean_entry. The table size, wss.num_entries,
266 * is always a power-of-2.
267 */
268 entry = (atomic_inc_return(&wss.clean_entry) - 1)
269 & (wss.num_entries - 1);
270
271 /* clear the entry and count the bits */
272 bits = xchg(&wss.entries[entry], 0);
273 weight = hweight64((u64)bits);
274 /* only adjust the contended total count if needed */
275 if (weight)
276 atomic_sub(weight, &wss.total_count);
277 }
278 }
279
280 /*
281 * Insert the given address into the working set array.
282 */
wss_insert(void * address)283 static void wss_insert(void *address)
284 {
285 u32 page = ((unsigned long)address >> PAGE_SHIFT) & wss.pages_mask;
286 u32 entry = page / BITS_PER_LONG; /* assumes this ends up a shift */
287 u32 nr = page & (BITS_PER_LONG - 1);
288
289 if (!test_and_set_bit(nr, &wss.entries[entry]))
290 atomic_inc(&wss.total_count);
291
292 wss_advance_clean_counter();
293 }
294
295 /*
296 * Is the working set larger than the threshold?
297 */
wss_exceeds_threshold(void)298 static inline bool wss_exceeds_threshold(void)
299 {
300 return atomic_read(&wss.total_count) >= wss.threshold;
301 }
302
303 /*
304 * Translate ib_wr_opcode into ib_wc_opcode.
305 */
306 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
307 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
308 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
309 [IB_WR_SEND] = IB_WC_SEND,
310 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
311 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
312 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
313 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
314 [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
315 [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
316 [IB_WR_REG_MR] = IB_WC_REG_MR
317 };
318
319 /*
320 * Length of header by opcode, 0 --> not supported
321 */
322 const u8 hdr_len_by_opcode[256] = {
323 /* RC */
324 [IB_OPCODE_RC_SEND_FIRST] = 12 + 8,
325 [IB_OPCODE_RC_SEND_MIDDLE] = 12 + 8,
326 [IB_OPCODE_RC_SEND_LAST] = 12 + 8,
327 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
328 [IB_OPCODE_RC_SEND_ONLY] = 12 + 8,
329 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
330 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
331 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = 12 + 8,
332 [IB_OPCODE_RC_RDMA_WRITE_LAST] = 12 + 8,
333 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
334 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
335 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
336 [IB_OPCODE_RC_RDMA_READ_REQUEST] = 12 + 8 + 16,
337 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = 12 + 8 + 4,
338 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = 12 + 8,
339 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = 12 + 8 + 4,
340 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = 12 + 8 + 4,
341 [IB_OPCODE_RC_ACKNOWLEDGE] = 12 + 8 + 4,
342 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = 12 + 8 + 4 + 8,
343 [IB_OPCODE_RC_COMPARE_SWAP] = 12 + 8 + 28,
344 [IB_OPCODE_RC_FETCH_ADD] = 12 + 8 + 28,
345 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = 12 + 8 + 4,
346 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = 12 + 8 + 4,
347 /* UC */
348 [IB_OPCODE_UC_SEND_FIRST] = 12 + 8,
349 [IB_OPCODE_UC_SEND_MIDDLE] = 12 + 8,
350 [IB_OPCODE_UC_SEND_LAST] = 12 + 8,
351 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
352 [IB_OPCODE_UC_SEND_ONLY] = 12 + 8,
353 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
354 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
355 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = 12 + 8,
356 [IB_OPCODE_UC_RDMA_WRITE_LAST] = 12 + 8,
357 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
358 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
359 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
360 /* UD */
361 [IB_OPCODE_UD_SEND_ONLY] = 12 + 8 + 8,
362 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 12
363 };
364
365 static const opcode_handler opcode_handler_tbl[256] = {
366 /* RC */
367 [IB_OPCODE_RC_SEND_FIRST] = &hfi1_rc_rcv,
368 [IB_OPCODE_RC_SEND_MIDDLE] = &hfi1_rc_rcv,
369 [IB_OPCODE_RC_SEND_LAST] = &hfi1_rc_rcv,
370 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
371 [IB_OPCODE_RC_SEND_ONLY] = &hfi1_rc_rcv,
372 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
373 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = &hfi1_rc_rcv,
374 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = &hfi1_rc_rcv,
375 [IB_OPCODE_RC_RDMA_WRITE_LAST] = &hfi1_rc_rcv,
376 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
377 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = &hfi1_rc_rcv,
378 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
379 [IB_OPCODE_RC_RDMA_READ_REQUEST] = &hfi1_rc_rcv,
380 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = &hfi1_rc_rcv,
381 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = &hfi1_rc_rcv,
382 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = &hfi1_rc_rcv,
383 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = &hfi1_rc_rcv,
384 [IB_OPCODE_RC_ACKNOWLEDGE] = &hfi1_rc_rcv,
385 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = &hfi1_rc_rcv,
386 [IB_OPCODE_RC_COMPARE_SWAP] = &hfi1_rc_rcv,
387 [IB_OPCODE_RC_FETCH_ADD] = &hfi1_rc_rcv,
388 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = &hfi1_rc_rcv,
389 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = &hfi1_rc_rcv,
390 /* UC */
391 [IB_OPCODE_UC_SEND_FIRST] = &hfi1_uc_rcv,
392 [IB_OPCODE_UC_SEND_MIDDLE] = &hfi1_uc_rcv,
393 [IB_OPCODE_UC_SEND_LAST] = &hfi1_uc_rcv,
394 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
395 [IB_OPCODE_UC_SEND_ONLY] = &hfi1_uc_rcv,
396 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
397 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = &hfi1_uc_rcv,
398 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = &hfi1_uc_rcv,
399 [IB_OPCODE_UC_RDMA_WRITE_LAST] = &hfi1_uc_rcv,
400 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
401 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = &hfi1_uc_rcv,
402 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
403 /* UD */
404 [IB_OPCODE_UD_SEND_ONLY] = &hfi1_ud_rcv,
405 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_ud_rcv,
406 /* CNP */
407 [IB_OPCODE_CNP] = &hfi1_cnp_rcv
408 };
409
410 #define OPMASK 0x1f
411
412 static const u32 pio_opmask[BIT(3)] = {
413 /* RC */
414 [IB_OPCODE_RC >> 5] =
415 BIT(RC_OP(SEND_ONLY) & OPMASK) |
416 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
417 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
418 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
419 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
420 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
421 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
422 BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
423 BIT(RC_OP(FETCH_ADD) & OPMASK),
424 /* UC */
425 [IB_OPCODE_UC >> 5] =
426 BIT(UC_OP(SEND_ONLY) & OPMASK) |
427 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
428 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
429 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
430 };
431
432 /*
433 * System image GUID.
434 */
435 __be64 ib_hfi1_sys_image_guid;
436
437 /**
438 * hfi1_copy_sge - copy data to SGE memory
439 * @ss: the SGE state
440 * @data: the data to copy
441 * @length: the length of the data
442 * @release: boolean to release MR
443 * @copy_last: do a separate copy of the last 8 bytes
444 */
hfi1_copy_sge(struct rvt_sge_state * ss,void * data,u32 length,bool release,bool copy_last)445 void hfi1_copy_sge(
446 struct rvt_sge_state *ss,
447 void *data, u32 length,
448 bool release,
449 bool copy_last)
450 {
451 struct rvt_sge *sge = &ss->sge;
452 int i;
453 bool in_last = false;
454 bool cacheless_copy = false;
455
456 if (sge_copy_mode == COPY_CACHELESS) {
457 cacheless_copy = length >= PAGE_SIZE;
458 } else if (sge_copy_mode == COPY_ADAPTIVE) {
459 if (length >= PAGE_SIZE) {
460 /*
461 * NOTE: this *assumes*:
462 * o The first vaddr is the dest.
463 * o If multiple pages, then vaddr is sequential.
464 */
465 wss_insert(sge->vaddr);
466 if (length >= (2 * PAGE_SIZE))
467 wss_insert(sge->vaddr + PAGE_SIZE);
468
469 cacheless_copy = wss_exceeds_threshold();
470 } else {
471 wss_advance_clean_counter();
472 }
473 }
474 if (copy_last) {
475 if (length > 8) {
476 length -= 8;
477 } else {
478 copy_last = false;
479 in_last = true;
480 }
481 }
482
483 again:
484 while (length) {
485 u32 len = rvt_get_sge_length(sge, length);
486
487 WARN_ON_ONCE(len == 0);
488 if (unlikely(in_last)) {
489 /* enforce byte transfer ordering */
490 for (i = 0; i < len; i++)
491 ((u8 *)sge->vaddr)[i] = ((u8 *)data)[i];
492 } else if (cacheless_copy) {
493 cacheless_memcpy(sge->vaddr, data, len);
494 } else {
495 memcpy(sge->vaddr, data, len);
496 }
497 rvt_update_sge(ss, len, release);
498 data += len;
499 length -= len;
500 }
501
502 if (copy_last) {
503 copy_last = false;
504 in_last = true;
505 length = 8;
506 goto again;
507 }
508 }
509
510 /*
511 * Make sure the QP is ready and able to accept the given opcode.
512 */
qp_ok(struct hfi1_packet * packet)513 static inline opcode_handler qp_ok(struct hfi1_packet *packet)
514 {
515 if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
516 return NULL;
517 if (((packet->opcode & RVT_OPCODE_QP_MASK) ==
518 packet->qp->allowed_ops) ||
519 (packet->opcode == IB_OPCODE_CNP))
520 return opcode_handler_tbl[packet->opcode];
521
522 return NULL;
523 }
524
hfi1_fault_tx(struct rvt_qp * qp,u8 opcode,u64 pbc)525 static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc)
526 {
527 #ifdef CONFIG_FAULT_INJECTION
528 if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP)
529 /*
530 * In order to drop non-IB traffic we
531 * set PbcInsertHrc to NONE (0x2).
532 * The packet will still be delivered
533 * to the receiving node but a
534 * KHdrHCRCErr (KDETH packet with a bad
535 * HCRC) will be triggered and the
536 * packet will not be delivered to the
537 * correct context.
538 */
539 pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT;
540 else
541 /*
542 * In order to drop regular verbs
543 * traffic we set the PbcTestEbp
544 * flag. The packet will still be
545 * delivered to the receiving node but
546 * a 'late ebp error' will be
547 * triggered and will be dropped.
548 */
549 pbc |= PBC_TEST_EBP;
550 #endif
551 return pbc;
552 }
553
hfi1_do_pkey_check(struct hfi1_packet * packet)554 static int hfi1_do_pkey_check(struct hfi1_packet *packet)
555 {
556 struct hfi1_ctxtdata *rcd = packet->rcd;
557 struct hfi1_pportdata *ppd = rcd->ppd;
558 struct hfi1_16b_header *hdr = packet->hdr;
559 u16 pkey;
560
561 /* Pkey check needed only for bypass packets */
562 if (packet->etype != RHF_RCV_TYPE_BYPASS)
563 return 0;
564
565 /* Perform pkey check */
566 pkey = hfi1_16B_get_pkey(hdr);
567 return ingress_pkey_check(ppd, pkey, packet->sc,
568 packet->qp->s_pkey_index,
569 packet->slid, true);
570 }
571
hfi1_handle_packet(struct hfi1_packet * packet,bool is_mcast)572 static inline void hfi1_handle_packet(struct hfi1_packet *packet,
573 bool is_mcast)
574 {
575 u32 qp_num;
576 struct hfi1_ctxtdata *rcd = packet->rcd;
577 struct hfi1_pportdata *ppd = rcd->ppd;
578 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
579 struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
580 opcode_handler packet_handler;
581 unsigned long flags;
582
583 inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]);
584
585 if (unlikely(is_mcast)) {
586 struct rvt_mcast *mcast;
587 struct rvt_mcast_qp *p;
588
589 if (!packet->grh)
590 goto drop;
591 mcast = rvt_mcast_find(&ibp->rvp,
592 &packet->grh->dgid,
593 opa_get_lid(packet->dlid, 9B));
594 if (!mcast)
595 goto drop;
596 rcu_read_lock();
597 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
598 packet->qp = p->qp;
599 if (hfi1_do_pkey_check(packet))
600 goto unlock_drop;
601 spin_lock_irqsave(&packet->qp->r_lock, flags);
602 packet_handler = qp_ok(packet);
603 if (likely(packet_handler))
604 packet_handler(packet);
605 else
606 ibp->rvp.n_pkt_drops++;
607 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
608 }
609 rcu_read_unlock();
610 /*
611 * Notify rvt_multicast_detach() if it is waiting for us
612 * to finish.
613 */
614 if (atomic_dec_return(&mcast->refcount) <= 1)
615 wake_up(&mcast->wait);
616 } else {
617 /* Get the destination QP number. */
618 qp_num = ib_bth_get_qpn(packet->ohdr);
619 rcu_read_lock();
620 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
621 if (!packet->qp)
622 goto unlock_drop;
623
624 if (hfi1_do_pkey_check(packet))
625 goto unlock_drop;
626
627 if (unlikely(hfi1_dbg_fault_opcode(packet->qp, packet->opcode,
628 true)))
629 goto unlock_drop;
630
631 spin_lock_irqsave(&packet->qp->r_lock, flags);
632 packet_handler = qp_ok(packet);
633 if (likely(packet_handler))
634 packet_handler(packet);
635 else
636 ibp->rvp.n_pkt_drops++;
637 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
638 rcu_read_unlock();
639 }
640 return;
641 unlock_drop:
642 rcu_read_unlock();
643 drop:
644 ibp->rvp.n_pkt_drops++;
645 }
646
647 /**
648 * hfi1_ib_rcv - process an incoming packet
649 * @packet: data packet information
650 *
651 * This is called to process an incoming packet at interrupt level.
652 */
hfi1_ib_rcv(struct hfi1_packet * packet)653 void hfi1_ib_rcv(struct hfi1_packet *packet)
654 {
655 struct hfi1_ctxtdata *rcd = packet->rcd;
656
657 trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
658 hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
659 }
660
hfi1_16B_rcv(struct hfi1_packet * packet)661 void hfi1_16B_rcv(struct hfi1_packet *packet)
662 {
663 struct hfi1_ctxtdata *rcd = packet->rcd;
664
665 trace_input_ibhdr(rcd->dd, packet, false);
666 hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
667 }
668
669 /*
670 * This is called from a timer to check for QPs
671 * which need kernel memory in order to send a packet.
672 */
mem_timer(unsigned long data)673 static void mem_timer(unsigned long data)
674 {
675 struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
676 struct list_head *list = &dev->memwait;
677 struct rvt_qp *qp = NULL;
678 struct iowait *wait;
679 unsigned long flags;
680 struct hfi1_qp_priv *priv;
681
682 write_seqlock_irqsave(&dev->iowait_lock, flags);
683 if (!list_empty(list)) {
684 wait = list_first_entry(list, struct iowait, list);
685 qp = iowait_to_qp(wait);
686 priv = qp->priv;
687 list_del_init(&priv->s_iowait.list);
688 priv->s_iowait.lock = NULL;
689 /* refcount held until actual wake up */
690 if (!list_empty(list))
691 mod_timer(&dev->mem_timer, jiffies + 1);
692 }
693 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
694
695 if (qp)
696 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
697 }
698
699 /*
700 * This is called with progress side lock held.
701 */
702 /* New API */
verbs_sdma_complete(struct sdma_txreq * cookie,int status)703 static void verbs_sdma_complete(
704 struct sdma_txreq *cookie,
705 int status)
706 {
707 struct verbs_txreq *tx =
708 container_of(cookie, struct verbs_txreq, txreq);
709 struct rvt_qp *qp = tx->qp;
710
711 spin_lock(&qp->s_lock);
712 if (tx->wqe) {
713 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
714 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
715 struct hfi1_opa_header *hdr;
716
717 hdr = &tx->phdr.hdr;
718 hfi1_rc_send_complete(qp, hdr);
719 }
720 spin_unlock(&qp->s_lock);
721
722 hfi1_put_txreq(tx);
723 }
724
wait_kmem(struct hfi1_ibdev * dev,struct rvt_qp * qp,struct hfi1_pkt_state * ps)725 static int wait_kmem(struct hfi1_ibdev *dev,
726 struct rvt_qp *qp,
727 struct hfi1_pkt_state *ps)
728 {
729 struct hfi1_qp_priv *priv = qp->priv;
730 unsigned long flags;
731 int ret = 0;
732
733 spin_lock_irqsave(&qp->s_lock, flags);
734 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
735 write_seqlock(&dev->iowait_lock);
736 list_add_tail(&ps->s_txreq->txreq.list,
737 &priv->s_iowait.tx_head);
738 if (list_empty(&priv->s_iowait.list)) {
739 if (list_empty(&dev->memwait))
740 mod_timer(&dev->mem_timer, jiffies + 1);
741 qp->s_flags |= RVT_S_WAIT_KMEM;
742 list_add_tail(&priv->s_iowait.list, &dev->memwait);
743 priv->s_iowait.lock = &dev->iowait_lock;
744 trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
745 rvt_get_qp(qp);
746 }
747 write_sequnlock(&dev->iowait_lock);
748 qp->s_flags &= ~RVT_S_BUSY;
749 ret = -EBUSY;
750 }
751 spin_unlock_irqrestore(&qp->s_lock, flags);
752
753 return ret;
754 }
755
756 /*
757 * This routine calls txadds for each sg entry.
758 *
759 * Add failures will revert the sge cursor
760 */
build_verbs_ulp_payload(struct sdma_engine * sde,u32 length,struct verbs_txreq * tx)761 static noinline int build_verbs_ulp_payload(
762 struct sdma_engine *sde,
763 u32 length,
764 struct verbs_txreq *tx)
765 {
766 struct rvt_sge_state *ss = tx->ss;
767 struct rvt_sge *sg_list = ss->sg_list;
768 struct rvt_sge sge = ss->sge;
769 u8 num_sge = ss->num_sge;
770 u32 len;
771 int ret = 0;
772
773 while (length) {
774 len = ss->sge.length;
775 if (len > length)
776 len = length;
777 if (len > ss->sge.sge_length)
778 len = ss->sge.sge_length;
779 WARN_ON_ONCE(len == 0);
780 ret = sdma_txadd_kvaddr(
781 sde->dd,
782 &tx->txreq,
783 ss->sge.vaddr,
784 len);
785 if (ret)
786 goto bail_txadd;
787 rvt_update_sge(ss, len, false);
788 length -= len;
789 }
790 return ret;
791 bail_txadd:
792 /* unwind cursor */
793 ss->sge = sge;
794 ss->num_sge = num_sge;
795 ss->sg_list = sg_list;
796 return ret;
797 }
798
799 /*
800 * Build the number of DMA descriptors needed to send length bytes of data.
801 *
802 * NOTE: DMA mapping is held in the tx until completed in the ring or
803 * the tx desc is freed without having been submitted to the ring
804 *
805 * This routine ensures all the helper routine calls succeed.
806 */
807 /* New API */
build_verbs_tx_desc(struct sdma_engine * sde,u32 length,struct verbs_txreq * tx,struct hfi1_ahg_info * ahg_info,u64 pbc)808 static int build_verbs_tx_desc(
809 struct sdma_engine *sde,
810 u32 length,
811 struct verbs_txreq *tx,
812 struct hfi1_ahg_info *ahg_info,
813 u64 pbc)
814 {
815 int ret = 0;
816 struct hfi1_sdma_header *phdr = &tx->phdr;
817 u16 hdrbytes = tx->hdr_dwords << 2;
818 u32 *hdr;
819 u8 extra_bytes = 0;
820 static char trail_buf[12]; /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
821
822 if (tx->phdr.hdr.hdr_type) {
823 /*
824 * hdrbytes accounts for PBC. Need to subtract 8 bytes
825 * before calculating padding.
826 */
827 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) +
828 (SIZE_OF_CRC << 2) + SIZE_OF_LT;
829 hdr = (u32 *)&phdr->hdr.opah;
830 } else {
831 hdr = (u32 *)&phdr->hdr.ibh;
832 }
833 if (!ahg_info->ahgcount) {
834 ret = sdma_txinit_ahg(
835 &tx->txreq,
836 ahg_info->tx_flags,
837 hdrbytes + length +
838 extra_bytes,
839 ahg_info->ahgidx,
840 0,
841 NULL,
842 0,
843 verbs_sdma_complete);
844 if (ret)
845 goto bail_txadd;
846 phdr->pbc = cpu_to_le64(pbc);
847 ret = sdma_txadd_kvaddr(
848 sde->dd,
849 &tx->txreq,
850 phdr,
851 hdrbytes);
852 if (ret)
853 goto bail_txadd;
854 } else {
855 ret = sdma_txinit_ahg(
856 &tx->txreq,
857 ahg_info->tx_flags,
858 length,
859 ahg_info->ahgidx,
860 ahg_info->ahgcount,
861 ahg_info->ahgdesc,
862 hdrbytes,
863 verbs_sdma_complete);
864 if (ret)
865 goto bail_txadd;
866 }
867 /* add the ulp payload - if any. tx->ss can be NULL for acks */
868 if (tx->ss) {
869 ret = build_verbs_ulp_payload(sde, length, tx);
870 if (ret)
871 goto bail_txadd;
872 }
873
874 /* add icrc, lt byte, and padding to flit */
875 if (extra_bytes != 0)
876 ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq,
877 trail_buf, extra_bytes);
878
879 bail_txadd:
880 return ret;
881 }
882
hfi1_verbs_send_dma(struct rvt_qp * qp,struct hfi1_pkt_state * ps,u64 pbc)883 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
884 u64 pbc)
885 {
886 struct hfi1_qp_priv *priv = qp->priv;
887 struct hfi1_ahg_info *ahg_info = priv->s_ahg;
888 u32 hdrwords = qp->s_hdrwords;
889 u32 len = ps->s_txreq->s_cur_size;
890 u32 plen;
891 struct hfi1_ibdev *dev = ps->dev;
892 struct hfi1_pportdata *ppd = ps->ppd;
893 struct verbs_txreq *tx;
894 u8 sc5 = priv->s_sc;
895 int ret;
896 u32 dwords;
897 bool bypass = false;
898
899 if (ps->s_txreq->phdr.hdr.hdr_type) {
900 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len);
901
902 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) +
903 SIZE_OF_LT) >> 2;
904 bypass = true;
905 } else {
906 dwords = (len + 3) >> 2;
907 }
908 plen = hdrwords + dwords + 2;
909
910 tx = ps->s_txreq;
911 if (!sdma_txreq_built(&tx->txreq)) {
912 if (likely(pbc == 0)) {
913 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
914
915 /* No vl15 here */
916 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
917 if (ps->s_txreq->phdr.hdr.hdr_type)
918 pbc |= PBC_PACKET_BYPASS |
919 PBC_INSERT_BYPASS_ICRC;
920 else
921 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
922
923 if (unlikely(hfi1_dbg_fault_opcode(qp, ps->opcode,
924 false)))
925 pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
926 pbc = create_pbc(ppd,
927 pbc,
928 qp->srate_mbps,
929 vl,
930 plen);
931 }
932 tx->wqe = qp->s_wqe;
933 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
934 if (unlikely(ret))
935 goto bail_build;
936 }
937 ret = sdma_send_txreq(tx->sde, &priv->s_iowait, &tx->txreq,
938 ps->pkts_sent);
939 if (unlikely(ret < 0)) {
940 if (ret == -ECOMM)
941 goto bail_ecomm;
942 return ret;
943 }
944 trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
945 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
946 return ret;
947
948 bail_ecomm:
949 /* The current one got "sent" */
950 return 0;
951 bail_build:
952 ret = wait_kmem(dev, qp, ps);
953 if (!ret) {
954 /* free txreq - bad state */
955 hfi1_put_txreq(ps->s_txreq);
956 ps->s_txreq = NULL;
957 }
958 return ret;
959 }
960
961 /*
962 * If we are now in the error state, return zero to flush the
963 * send work request.
964 */
pio_wait(struct rvt_qp * qp,struct send_context * sc,struct hfi1_pkt_state * ps,u32 flag)965 static int pio_wait(struct rvt_qp *qp,
966 struct send_context *sc,
967 struct hfi1_pkt_state *ps,
968 u32 flag)
969 {
970 struct hfi1_qp_priv *priv = qp->priv;
971 struct hfi1_devdata *dd = sc->dd;
972 struct hfi1_ibdev *dev = &dd->verbs_dev;
973 unsigned long flags;
974 int ret = 0;
975
976 /*
977 * Note that as soon as want_buffer() is called and
978 * possibly before it returns, sc_piobufavail()
979 * could be called. Therefore, put QP on the I/O wait list before
980 * enabling the PIO avail interrupt.
981 */
982 spin_lock_irqsave(&qp->s_lock, flags);
983 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
984 write_seqlock(&dev->iowait_lock);
985 list_add_tail(&ps->s_txreq->txreq.list,
986 &priv->s_iowait.tx_head);
987 if (list_empty(&priv->s_iowait.list)) {
988 struct hfi1_ibdev *dev = &dd->verbs_dev;
989 int was_empty;
990
991 dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
992 dev->n_piodrain += !!(flag & RVT_S_WAIT_PIO_DRAIN);
993 qp->s_flags |= flag;
994 was_empty = list_empty(&sc->piowait);
995 iowait_queue(ps->pkts_sent, &priv->s_iowait,
996 &sc->piowait);
997 priv->s_iowait.lock = &dev->iowait_lock;
998 trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
999 rvt_get_qp(qp);
1000 /* counting: only call wantpiobuf_intr if first user */
1001 if (was_empty)
1002 hfi1_sc_wantpiobuf_intr(sc, 1);
1003 }
1004 write_sequnlock(&dev->iowait_lock);
1005 qp->s_flags &= ~RVT_S_BUSY;
1006 ret = -EBUSY;
1007 }
1008 spin_unlock_irqrestore(&qp->s_lock, flags);
1009 return ret;
1010 }
1011
verbs_pio_complete(void * arg,int code)1012 static void verbs_pio_complete(void *arg, int code)
1013 {
1014 struct rvt_qp *qp = (struct rvt_qp *)arg;
1015 struct hfi1_qp_priv *priv = qp->priv;
1016
1017 if (iowait_pio_dec(&priv->s_iowait))
1018 iowait_drain_wakeup(&priv->s_iowait);
1019 }
1020
hfi1_verbs_send_pio(struct rvt_qp * qp,struct hfi1_pkt_state * ps,u64 pbc)1021 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1022 u64 pbc)
1023 {
1024 struct hfi1_qp_priv *priv = qp->priv;
1025 u32 hdrwords = qp->s_hdrwords;
1026 struct rvt_sge_state *ss = ps->s_txreq->ss;
1027 u32 len = ps->s_txreq->s_cur_size;
1028 u32 dwords;
1029 u32 plen;
1030 struct hfi1_pportdata *ppd = ps->ppd;
1031 u32 *hdr;
1032 u8 sc5;
1033 unsigned long flags = 0;
1034 struct send_context *sc;
1035 struct pio_buf *pbuf;
1036 int wc_status = IB_WC_SUCCESS;
1037 int ret = 0;
1038 pio_release_cb cb = NULL;
1039 u32 lrh0_16b;
1040 bool bypass = false;
1041 u8 extra_bytes = 0;
1042
1043 if (ps->s_txreq->phdr.hdr.hdr_type) {
1044 u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len);
1045
1046 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT;
1047 dwords = (len + extra_bytes) >> 2;
1048 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah;
1049 lrh0_16b = ps->s_txreq->phdr.hdr.opah.lrh[0];
1050 bypass = true;
1051 } else {
1052 dwords = (len + 3) >> 2;
1053 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh;
1054 }
1055 plen = hdrwords + dwords + 2;
1056
1057 /* only RC/UC use complete */
1058 switch (qp->ibqp.qp_type) {
1059 case IB_QPT_RC:
1060 case IB_QPT_UC:
1061 cb = verbs_pio_complete;
1062 break;
1063 default:
1064 break;
1065 }
1066
1067 /* vl15 special case taken care of in ud.c */
1068 sc5 = priv->s_sc;
1069 sc = ps->s_txreq->psc;
1070
1071 if (likely(pbc == 0)) {
1072 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1073
1074 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
1075 if (ps->s_txreq->phdr.hdr.hdr_type)
1076 pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
1077 else
1078 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
1079 if (unlikely(hfi1_dbg_fault_opcode(qp, ps->opcode, false)))
1080 pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
1081 pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen);
1082 }
1083 if (cb)
1084 iowait_pio_inc(&priv->s_iowait);
1085 pbuf = sc_buffer_alloc(sc, plen, cb, qp);
1086 if (unlikely(!pbuf)) {
1087 if (cb)
1088 verbs_pio_complete(qp, 0);
1089 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1090 /*
1091 * If we have filled the PIO buffers to capacity and are
1092 * not in an active state this request is not going to
1093 * go out to so just complete it with an error or else a
1094 * ULP or the core may be stuck waiting.
1095 */
1096 hfi1_cdbg(
1097 PIO,
1098 "alloc failed. state not active, completing");
1099 wc_status = IB_WC_GENERAL_ERR;
1100 goto pio_bail;
1101 } else {
1102 /*
1103 * This is a normal occurrence. The PIO buffs are full
1104 * up but we are still happily sending, well we could be
1105 * so lets continue to queue the request.
1106 */
1107 hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1108 ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1109 if (!ret)
1110 /* txreq not queued - free */
1111 goto bail;
1112 /* tx consumed in wait */
1113 return ret;
1114 }
1115 }
1116
1117 if (dwords == 0) {
1118 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1119 } else {
1120 seg_pio_copy_start(pbuf, pbc,
1121 hdr, hdrwords * 4);
1122 if (ss) {
1123 while (len) {
1124 void *addr = ss->sge.vaddr;
1125 u32 slen = ss->sge.length;
1126
1127 if (slen > len)
1128 slen = len;
1129 if (slen > ss->sge.sge_length)
1130 slen = ss->sge.sge_length;
1131 rvt_update_sge(ss, slen, false);
1132 seg_pio_copy_mid(pbuf, addr, slen);
1133 len -= slen;
1134 }
1135 }
1136 /*
1137 * Bypass packet will need to copy additional
1138 * bytes to accommodate for CRC and LT bytes
1139 */
1140 if (extra_bytes) {
1141 u8 *empty_buf;
1142
1143 empty_buf = kcalloc(extra_bytes, sizeof(u8),
1144 GFP_KERNEL);
1145 seg_pio_copy_mid(pbuf, empty_buf, extra_bytes);
1146 kfree(empty_buf);
1147 }
1148 seg_pio_copy_end(pbuf);
1149 }
1150
1151 trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1152 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
1153
1154 pio_bail:
1155 if (qp->s_wqe) {
1156 spin_lock_irqsave(&qp->s_lock, flags);
1157 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1158 spin_unlock_irqrestore(&qp->s_lock, flags);
1159 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1160 spin_lock_irqsave(&qp->s_lock, flags);
1161 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1162 spin_unlock_irqrestore(&qp->s_lock, flags);
1163 }
1164
1165 ret = 0;
1166
1167 bail:
1168 hfi1_put_txreq(ps->s_txreq);
1169 return ret;
1170 }
1171
1172 /*
1173 * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1174 * being an entry from the partition key table), return 0
1175 * otherwise. Use the matching criteria for egress partition keys
1176 * specified in the OPAv1 spec., section 9.1l.7.
1177 */
egress_pkey_matches_entry(u16 pkey,u16 ent)1178 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1179 {
1180 u16 mkey = pkey & PKEY_LOW_15_MASK;
1181 u16 mentry = ent & PKEY_LOW_15_MASK;
1182
1183 if (mkey == mentry) {
1184 /*
1185 * If pkey[15] is set (full partition member),
1186 * is bit 15 in the corresponding table element
1187 * clear (limited member)?
1188 */
1189 if (pkey & PKEY_MEMBER_MASK)
1190 return !!(ent & PKEY_MEMBER_MASK);
1191 return 1;
1192 }
1193 return 0;
1194 }
1195
1196 /**
1197 * egress_pkey_check - check P_KEY of a packet
1198 * @ppd: Physical IB port data
1199 * @slid: SLID for packet
1200 * @bkey: PKEY for header
1201 * @sc5: SC for packet
1202 * @s_pkey_index: It will be used for look up optimization for kernel contexts
1203 * only. If it is negative value, then it means user contexts is calling this
1204 * function.
1205 *
1206 * It checks if hdr's pkey is valid.
1207 *
1208 * Return: 0 on success, otherwise, 1
1209 */
egress_pkey_check(struct hfi1_pportdata * ppd,u32 slid,u16 pkey,u8 sc5,int8_t s_pkey_index)1210 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1211 u8 sc5, int8_t s_pkey_index)
1212 {
1213 struct hfi1_devdata *dd;
1214 int i;
1215 int is_user_ctxt_mechanism = (s_pkey_index < 0);
1216
1217 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1218 return 0;
1219
1220 /* If SC15, pkey[0:14] must be 0x7fff */
1221 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1222 goto bad;
1223
1224 /* Is the pkey = 0x0, or 0x8000? */
1225 if ((pkey & PKEY_LOW_15_MASK) == 0)
1226 goto bad;
1227
1228 /*
1229 * For the kernel contexts only, if a qp is passed into the function,
1230 * the most likely matching pkey has index qp->s_pkey_index
1231 */
1232 if (!is_user_ctxt_mechanism &&
1233 egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1234 return 0;
1235 }
1236
1237 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1238 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1239 return 0;
1240 }
1241 bad:
1242 /*
1243 * For the user-context mechanism, the P_KEY check would only happen
1244 * once per SDMA request, not once per packet. Therefore, there's no
1245 * need to increment the counter for the user-context mechanism.
1246 */
1247 if (!is_user_ctxt_mechanism) {
1248 incr_cntr64(&ppd->port_xmit_constraint_errors);
1249 dd = ppd->dd;
1250 if (!(dd->err_info_xmit_constraint.status &
1251 OPA_EI_STATUS_SMASK)) {
1252 dd->err_info_xmit_constraint.status |=
1253 OPA_EI_STATUS_SMASK;
1254 dd->err_info_xmit_constraint.slid = slid;
1255 dd->err_info_xmit_constraint.pkey = pkey;
1256 }
1257 }
1258 return 1;
1259 }
1260
1261 /**
1262 * get_send_routine - choose an egress routine
1263 *
1264 * Choose an egress routine based on QP type
1265 * and size
1266 */
get_send_routine(struct rvt_qp * qp,struct hfi1_pkt_state * ps)1267 static inline send_routine get_send_routine(struct rvt_qp *qp,
1268 struct hfi1_pkt_state *ps)
1269 {
1270 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1271 struct hfi1_qp_priv *priv = qp->priv;
1272 struct verbs_txreq *tx = ps->s_txreq;
1273
1274 if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1275 return dd->process_pio_send;
1276 switch (qp->ibqp.qp_type) {
1277 case IB_QPT_SMI:
1278 return dd->process_pio_send;
1279 case IB_QPT_GSI:
1280 case IB_QPT_UD:
1281 break;
1282 case IB_QPT_UC:
1283 case IB_QPT_RC: {
1284 if (piothreshold &&
1285 tx->s_cur_size <= min(piothreshold, qp->pmtu) &&
1286 (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) &&
1287 iowait_sdma_pending(&priv->s_iowait) == 0 &&
1288 !sdma_txreq_built(&tx->txreq))
1289 return dd->process_pio_send;
1290 break;
1291 }
1292 default:
1293 break;
1294 }
1295 return dd->process_dma_send;
1296 }
1297
1298 /**
1299 * hfi1_verbs_send - send a packet
1300 * @qp: the QP to send on
1301 * @ps: the state of the packet to send
1302 *
1303 * Return zero if packet is sent or queued OK.
1304 * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1305 */
hfi1_verbs_send(struct rvt_qp * qp,struct hfi1_pkt_state * ps)1306 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1307 {
1308 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1309 struct hfi1_qp_priv *priv = qp->priv;
1310 struct ib_other_headers *ohdr;
1311 send_routine sr;
1312 int ret;
1313 u16 pkey;
1314 u32 slid;
1315
1316 /* locate the pkey within the headers */
1317 if (ps->s_txreq->phdr.hdr.hdr_type) {
1318 struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah;
1319 u8 l4 = hfi1_16B_get_l4(hdr);
1320
1321 if (l4 == OPA_16B_L4_IB_GLOBAL)
1322 ohdr = &hdr->u.l.oth;
1323 else
1324 ohdr = &hdr->u.oth;
1325 slid = hfi1_16B_get_slid(hdr);
1326 pkey = hfi1_16B_get_pkey(hdr);
1327 } else {
1328 struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh;
1329 u8 lnh = ib_get_lnh(hdr);
1330
1331 if (lnh == HFI1_LRH_GRH)
1332 ohdr = &hdr->u.l.oth;
1333 else
1334 ohdr = &hdr->u.oth;
1335 slid = ib_get_slid(hdr);
1336 pkey = ib_bth_get_pkey(ohdr);
1337 }
1338
1339 ps->opcode = ib_bth_get_opcode(ohdr);
1340 sr = get_send_routine(qp, ps);
1341 ret = egress_pkey_check(dd->pport, slid, pkey,
1342 priv->s_sc, qp->s_pkey_index);
1343 if (unlikely(ret)) {
1344 /*
1345 * The value we are returning here does not get propagated to
1346 * the verbs caller. Thus we need to complete the request with
1347 * error otherwise the caller could be sitting waiting on the
1348 * completion event. Only do this for PIO. SDMA has its own
1349 * mechanism for handling the errors. So for SDMA we can just
1350 * return.
1351 */
1352 if (sr == dd->process_pio_send) {
1353 unsigned long flags;
1354
1355 hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1356 __func__);
1357 spin_lock_irqsave(&qp->s_lock, flags);
1358 hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1359 spin_unlock_irqrestore(&qp->s_lock, flags);
1360 }
1361 return -EINVAL;
1362 }
1363 if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1364 return pio_wait(qp,
1365 ps->s_txreq->psc,
1366 ps,
1367 RVT_S_WAIT_PIO_DRAIN);
1368 return sr(qp, ps, 0);
1369 }
1370
1371 /**
1372 * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1373 * @dd: the device data structure
1374 */
hfi1_fill_device_attr(struct hfi1_devdata * dd)1375 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1376 {
1377 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1378 u32 ver = dd->dc8051_ver;
1379
1380 memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1381
1382 rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) |
1383 ((u64)(dc8051_ver_min(ver)) << 16) |
1384 (u64)dc8051_ver_patch(ver);
1385
1386 rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1387 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1388 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1389 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1390 IB_DEVICE_MEM_MGT_EXTENSIONS |
1391 IB_DEVICE_RDMA_NETDEV_OPA_VNIC;
1392 rdi->dparms.props.page_size_cap = PAGE_SIZE;
1393 rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1394 rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1395 rdi->dparms.props.hw_ver = dd->minrev;
1396 rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1397 rdi->dparms.props.max_mr_size = U64_MAX;
1398 rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1399 rdi->dparms.props.max_qp = hfi1_max_qps;
1400 rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs;
1401 rdi->dparms.props.max_sge = hfi1_max_sges;
1402 rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1403 rdi->dparms.props.max_cq = hfi1_max_cqs;
1404 rdi->dparms.props.max_ah = hfi1_max_ahs;
1405 rdi->dparms.props.max_cqe = hfi1_max_cqes;
1406 rdi->dparms.props.max_map_per_fmr = 32767;
1407 rdi->dparms.props.max_pd = hfi1_max_pds;
1408 rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1409 rdi->dparms.props.max_qp_init_rd_atom = 255;
1410 rdi->dparms.props.max_srq = hfi1_max_srqs;
1411 rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1412 rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1413 rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1414 rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1415 rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1416 rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1417 rdi->dparms.props.max_total_mcast_qp_attach =
1418 rdi->dparms.props.max_mcast_qp_attach *
1419 rdi->dparms.props.max_mcast_grp;
1420 }
1421
opa_speed_to_ib(u16 in)1422 static inline u16 opa_speed_to_ib(u16 in)
1423 {
1424 u16 out = 0;
1425
1426 if (in & OPA_LINK_SPEED_25G)
1427 out |= IB_SPEED_EDR;
1428 if (in & OPA_LINK_SPEED_12_5G)
1429 out |= IB_SPEED_FDR;
1430
1431 return out;
1432 }
1433
1434 /*
1435 * Convert a single OPA link width (no multiple flags) to an IB value.
1436 * A zero OPA link width means link down, which means the IB width value
1437 * is a don't care.
1438 */
opa_width_to_ib(u16 in)1439 static inline u16 opa_width_to_ib(u16 in)
1440 {
1441 switch (in) {
1442 case OPA_LINK_WIDTH_1X:
1443 /* map 2x and 3x to 1x as they don't exist in IB */
1444 case OPA_LINK_WIDTH_2X:
1445 case OPA_LINK_WIDTH_3X:
1446 return IB_WIDTH_1X;
1447 default: /* link down or unknown, return our largest width */
1448 case OPA_LINK_WIDTH_4X:
1449 return IB_WIDTH_4X;
1450 }
1451 }
1452
query_port(struct rvt_dev_info * rdi,u8 port_num,struct ib_port_attr * props)1453 static int query_port(struct rvt_dev_info *rdi, u8 port_num,
1454 struct ib_port_attr *props)
1455 {
1456 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1457 struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1458 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1459 u32 lid = ppd->lid;
1460
1461 /* props being zeroed by the caller, avoid zeroing it here */
1462 props->lid = lid ? lid : 0;
1463 props->lmc = ppd->lmc;
1464 /* OPA logical states match IB logical states */
1465 props->state = driver_lstate(ppd);
1466 props->phys_state = driver_pstate(ppd);
1467 props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1468 props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1469 /* see rate_show() in ib core/sysfs.c */
1470 props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1471 props->max_vl_num = ppd->vls_supported;
1472
1473 /* Once we are a "first class" citizen and have added the OPA MTUs to
1474 * the core we can advertise the larger MTU enum to the ULPs, for now
1475 * advertise only 4K.
1476 *
1477 * Those applications which are either OPA aware or pass the MTU enum
1478 * from the Path Records to us will get the new 8k MTU. Those that
1479 * attempt to process the MTU enum may fail in various ways.
1480 */
1481 props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1482 4096 : hfi1_max_mtu), IB_MTU_4096);
1483 props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1484 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1485
1486 /*
1487 * sm_lid of 0xFFFF needs special handling so that it can
1488 * be differentiated from a permissve LID of 0xFFFF.
1489 * We set the grh_required flag here so the SA can program
1490 * the DGID in the address handle appropriately
1491 */
1492 if (props->sm_lid == be16_to_cpu(IB_LID_PERMISSIVE))
1493 props->grh_required = true;
1494
1495 return 0;
1496 }
1497
modify_device(struct ib_device * device,int device_modify_mask,struct ib_device_modify * device_modify)1498 static int modify_device(struct ib_device *device,
1499 int device_modify_mask,
1500 struct ib_device_modify *device_modify)
1501 {
1502 struct hfi1_devdata *dd = dd_from_ibdev(device);
1503 unsigned i;
1504 int ret;
1505
1506 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1507 IB_DEVICE_MODIFY_NODE_DESC)) {
1508 ret = -EOPNOTSUPP;
1509 goto bail;
1510 }
1511
1512 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1513 memcpy(device->node_desc, device_modify->node_desc,
1514 IB_DEVICE_NODE_DESC_MAX);
1515 for (i = 0; i < dd->num_pports; i++) {
1516 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1517
1518 hfi1_node_desc_chg(ibp);
1519 }
1520 }
1521
1522 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1523 ib_hfi1_sys_image_guid =
1524 cpu_to_be64(device_modify->sys_image_guid);
1525 for (i = 0; i < dd->num_pports; i++) {
1526 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1527
1528 hfi1_sys_guid_chg(ibp);
1529 }
1530 }
1531
1532 ret = 0;
1533
1534 bail:
1535 return ret;
1536 }
1537
shut_down_port(struct rvt_dev_info * rdi,u8 port_num)1538 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1539 {
1540 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1541 struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1542 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1543 int ret;
1544
1545 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1546 OPA_LINKDOWN_REASON_UNKNOWN);
1547 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1548 return ret;
1549 }
1550
hfi1_get_guid_be(struct rvt_dev_info * rdi,struct rvt_ibport * rvp,int guid_index,__be64 * guid)1551 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1552 int guid_index, __be64 *guid)
1553 {
1554 struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1555
1556 if (guid_index >= HFI1_GUIDS_PER_PORT)
1557 return -EINVAL;
1558
1559 *guid = get_sguid(ibp, guid_index);
1560 return 0;
1561 }
1562
1563 /*
1564 * convert ah port,sl to sc
1565 */
ah_to_sc(struct ib_device * ibdev,struct rdma_ah_attr * ah)1566 u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah)
1567 {
1568 struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah));
1569
1570 return ibp->sl_to_sc[rdma_ah_get_sl(ah)];
1571 }
1572
hfi1_check_ah(struct ib_device * ibdev,struct rdma_ah_attr * ah_attr)1573 static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1574 {
1575 struct hfi1_ibport *ibp;
1576 struct hfi1_pportdata *ppd;
1577 struct hfi1_devdata *dd;
1578 u8 sc5;
1579 u8 sl;
1580
1581 if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) &&
1582 !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
1583 return -EINVAL;
1584
1585 /* test the mapping for validity */
1586 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1587 ppd = ppd_from_ibp(ibp);
1588 dd = dd_from_ppd(ppd);
1589
1590 sl = rdma_ah_get_sl(ah_attr);
1591 if (sl >= ARRAY_SIZE(ibp->sl_to_sc))
1592 return -EINVAL;
1593 sl = array_index_nospec(sl, ARRAY_SIZE(ibp->sl_to_sc));
1594
1595 sc5 = ibp->sl_to_sc[sl];
1596 if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1597 return -EINVAL;
1598 return 0;
1599 }
1600
hfi1_notify_new_ah(struct ib_device * ibdev,struct rdma_ah_attr * ah_attr,struct rvt_ah * ah)1601 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1602 struct rdma_ah_attr *ah_attr,
1603 struct rvt_ah *ah)
1604 {
1605 struct hfi1_ibport *ibp;
1606 struct hfi1_pportdata *ppd;
1607 struct hfi1_devdata *dd;
1608 u8 sc5;
1609 struct rdma_ah_attr *attr = &ah->attr;
1610
1611 /*
1612 * Do not trust reading anything from rvt_ah at this point as it is not
1613 * done being setup. We can however modify things which we need to set.
1614 */
1615
1616 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1617 ppd = ppd_from_ibp(ibp);
1618 sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)];
1619 hfi1_update_ah_attr(ibdev, attr);
1620 hfi1_make_opa_lid(attr);
1621 dd = dd_from_ppd(ppd);
1622 ah->vl = sc_to_vlt(dd, sc5);
1623 if (ah->vl < num_vls || ah->vl == 15)
1624 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1625 }
1626
1627 /**
1628 * hfi1_get_npkeys - return the size of the PKEY table for context 0
1629 * @dd: the hfi1_ib device
1630 */
hfi1_get_npkeys(struct hfi1_devdata * dd)1631 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1632 {
1633 return ARRAY_SIZE(dd->pport[0].pkeys);
1634 }
1635
init_ibport(struct hfi1_pportdata * ppd)1636 static void init_ibport(struct hfi1_pportdata *ppd)
1637 {
1638 struct hfi1_ibport *ibp = &ppd->ibport_data;
1639 size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1640 int i;
1641
1642 for (i = 0; i < sz; i++) {
1643 ibp->sl_to_sc[i] = i;
1644 ibp->sc_to_sl[i] = i;
1645 }
1646
1647 for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++)
1648 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list);
1649 setup_timer(&ibp->rvp.trap_timer, hfi1_handle_trap_timer,
1650 (unsigned long)ibp);
1651
1652 spin_lock_init(&ibp->rvp.lock);
1653 /* Set the prefix to the default value (see ch. 4.1.1) */
1654 ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1655 ibp->rvp.sm_lid = 0;
1656 /*
1657 * Below should only set bits defined in OPA PortInfo.CapabilityMask
1658 * and PortInfo.CapabilityMask3
1659 */
1660 ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1661 IB_PORT_CAP_MASK_NOTICE_SUP;
1662 ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported;
1663 ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1664 ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1665 ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1666 ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1667 ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1668
1669 RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1670 RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1671 }
1672
hfi1_get_dev_fw_str(struct ib_device * ibdev,char * str)1673 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str)
1674 {
1675 struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1676 struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1677 u32 ver = dd_from_dev(dev)->dc8051_ver;
1678
1679 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver),
1680 dc8051_ver_min(ver), dc8051_ver_patch(ver));
1681 }
1682
1683 static const char * const driver_cntr_names[] = {
1684 /* must be element 0*/
1685 "DRIVER_KernIntr",
1686 "DRIVER_ErrorIntr",
1687 "DRIVER_Tx_Errs",
1688 "DRIVER_Rcv_Errs",
1689 "DRIVER_HW_Errs",
1690 "DRIVER_NoPIOBufs",
1691 "DRIVER_CtxtsOpen",
1692 "DRIVER_RcvLen_Errs",
1693 "DRIVER_EgrBufFull",
1694 "DRIVER_EgrHdrFull"
1695 };
1696
1697 static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */
1698 static const char **dev_cntr_names;
1699 static const char **port_cntr_names;
1700 int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1701 static int num_dev_cntrs;
1702 static int num_port_cntrs;
1703 static int cntr_names_initialized;
1704
1705 /*
1706 * Convert a list of names separated by '\n' into an array of NULL terminated
1707 * strings. Optionally some entries can be reserved in the array to hold extra
1708 * external strings.
1709 */
init_cntr_names(const char * names_in,const size_t names_len,int num_extra_names,int * num_cntrs,const char *** cntr_names)1710 static int init_cntr_names(const char *names_in,
1711 const size_t names_len,
1712 int num_extra_names,
1713 int *num_cntrs,
1714 const char ***cntr_names)
1715 {
1716 char *names_out, *p, **q;
1717 int i, n;
1718
1719 n = 0;
1720 for (i = 0; i < names_len; i++)
1721 if (names_in[i] == '\n')
1722 n++;
1723
1724 names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len,
1725 GFP_KERNEL);
1726 if (!names_out) {
1727 *num_cntrs = 0;
1728 *cntr_names = NULL;
1729 return -ENOMEM;
1730 }
1731
1732 p = names_out + (n + num_extra_names) * sizeof(char *);
1733 memcpy(p, names_in, names_len);
1734
1735 q = (char **)names_out;
1736 for (i = 0; i < n; i++) {
1737 q[i] = p;
1738 p = strchr(p, '\n');
1739 *p++ = '\0';
1740 }
1741
1742 *num_cntrs = n;
1743 *cntr_names = (const char **)names_out;
1744 return 0;
1745 }
1746
alloc_hw_stats(struct ib_device * ibdev,u8 port_num)1747 static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev,
1748 u8 port_num)
1749 {
1750 int i, err;
1751
1752 mutex_lock(&cntr_names_lock);
1753 if (!cntr_names_initialized) {
1754 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1755
1756 err = init_cntr_names(dd->cntrnames,
1757 dd->cntrnameslen,
1758 num_driver_cntrs,
1759 &num_dev_cntrs,
1760 &dev_cntr_names);
1761 if (err) {
1762 mutex_unlock(&cntr_names_lock);
1763 return NULL;
1764 }
1765
1766 for (i = 0; i < num_driver_cntrs; i++)
1767 dev_cntr_names[num_dev_cntrs + i] =
1768 driver_cntr_names[i];
1769
1770 err = init_cntr_names(dd->portcntrnames,
1771 dd->portcntrnameslen,
1772 0,
1773 &num_port_cntrs,
1774 &port_cntr_names);
1775 if (err) {
1776 kfree(dev_cntr_names);
1777 dev_cntr_names = NULL;
1778 mutex_unlock(&cntr_names_lock);
1779 return NULL;
1780 }
1781 cntr_names_initialized = 1;
1782 }
1783 mutex_unlock(&cntr_names_lock);
1784
1785 if (!port_num)
1786 return rdma_alloc_hw_stats_struct(
1787 dev_cntr_names,
1788 num_dev_cntrs + num_driver_cntrs,
1789 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1790 else
1791 return rdma_alloc_hw_stats_struct(
1792 port_cntr_names,
1793 num_port_cntrs,
1794 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1795 }
1796
hfi1_sps_ints(void)1797 static u64 hfi1_sps_ints(void)
1798 {
1799 unsigned long flags;
1800 struct hfi1_devdata *dd;
1801 u64 sps_ints = 0;
1802
1803 spin_lock_irqsave(&hfi1_devs_lock, flags);
1804 list_for_each_entry(dd, &hfi1_dev_list, list) {
1805 sps_ints += get_all_cpu_total(dd->int_counter);
1806 }
1807 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1808 return sps_ints;
1809 }
1810
get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port,int index)1811 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1812 u8 port, int index)
1813 {
1814 u64 *values;
1815 int count;
1816
1817 if (!port) {
1818 u64 *stats = (u64 *)&hfi1_stats;
1819 int i;
1820
1821 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1822 values[num_dev_cntrs] = hfi1_sps_ints();
1823 for (i = 1; i < num_driver_cntrs; i++)
1824 values[num_dev_cntrs + i] = stats[i];
1825 count = num_dev_cntrs + num_driver_cntrs;
1826 } else {
1827 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1828
1829 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1830 count = num_port_cntrs;
1831 }
1832
1833 memcpy(stats->value, values, count * sizeof(u64));
1834 return count;
1835 }
1836
1837 /**
1838 * hfi1_register_ib_device - register our device with the infiniband core
1839 * @dd: the device data structure
1840 * Return 0 if successful, errno if unsuccessful.
1841 */
hfi1_register_ib_device(struct hfi1_devdata * dd)1842 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1843 {
1844 struct hfi1_ibdev *dev = &dd->verbs_dev;
1845 struct ib_device *ibdev = &dev->rdi.ibdev;
1846 struct hfi1_pportdata *ppd = dd->pport;
1847 struct hfi1_ibport *ibp = &ppd->ibport_data;
1848 unsigned i;
1849 int ret;
1850 size_t lcpysz = IB_DEVICE_NAME_MAX;
1851
1852 for (i = 0; i < dd->num_pports; i++)
1853 init_ibport(ppd + i);
1854
1855 /* Only need to initialize non-zero fields. */
1856
1857 setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev);
1858
1859 seqlock_init(&dev->iowait_lock);
1860 seqlock_init(&dev->txwait_lock);
1861 INIT_LIST_HEAD(&dev->txwait);
1862 INIT_LIST_HEAD(&dev->memwait);
1863
1864 ret = verbs_txreq_init(dev);
1865 if (ret)
1866 goto err_verbs_txreq;
1867
1868 /* Use first-port GUID as node guid */
1869 ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1870
1871 /*
1872 * The system image GUID is supposed to be the same for all
1873 * HFIs in a single system but since there can be other
1874 * device types in the system, we can't be sure this is unique.
1875 */
1876 if (!ib_hfi1_sys_image_guid)
1877 ib_hfi1_sys_image_guid = ibdev->node_guid;
1878 lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1879 strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1880 ibdev->owner = THIS_MODULE;
1881 ibdev->phys_port_cnt = dd->num_pports;
1882 ibdev->dev.parent = &dd->pcidev->dev;
1883 ibdev->modify_device = modify_device;
1884 ibdev->alloc_hw_stats = alloc_hw_stats;
1885 ibdev->get_hw_stats = get_hw_stats;
1886 ibdev->alloc_rdma_netdev = hfi1_vnic_alloc_rn;
1887
1888 /* keep process mad in the driver */
1889 ibdev->process_mad = hfi1_process_mad;
1890 ibdev->get_dev_fw_str = hfi1_get_dev_fw_str;
1891
1892 strncpy(ibdev->node_desc, init_utsname()->nodename,
1893 sizeof(ibdev->node_desc));
1894
1895 /*
1896 * Fill in rvt info object.
1897 */
1898 dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files;
1899 dd->verbs_dev.rdi.driver_f.get_card_name = get_card_name;
1900 dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1901 dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1902 dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1903 dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1904 dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1905 dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1906 dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1907 /*
1908 * Fill in rvt info device attributes.
1909 */
1910 hfi1_fill_device_attr(dd);
1911
1912 /* queue pair */
1913 dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1914 dd->verbs_dev.rdi.dparms.qpn_start = 0;
1915 dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1916 dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1917 dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16;
1918 dd->verbs_dev.rdi.dparms.qpn_res_end =
1919 dd->verbs_dev.rdi.dparms.qpn_res_start + 65535;
1920 dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1921 dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1922 dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1923 dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1924 dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA |
1925 RDMA_CORE_CAP_OPA_AH;
1926 dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1927
1928 dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1929 dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1930 dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1931 dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1932 dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt;
1933 dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1934 dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1935 dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1936 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1937 dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1938 dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1939 dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1940 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1941 dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1942 dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1943 dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1944 dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1945 dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc;
1946 dd->verbs_dev.rdi.driver_f.check_send_wqe = hfi1_check_send_wqe;
1947
1948 /* completeion queue */
1949 snprintf(dd->verbs_dev.rdi.dparms.cq_name,
1950 sizeof(dd->verbs_dev.rdi.dparms.cq_name),
1951 "hfi1_cq%d", dd->unit);
1952 dd->verbs_dev.rdi.dparms.node = dd->node;
1953
1954 /* misc settings */
1955 dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1956 dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1957 dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1958 dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1959
1960 /* post send table */
1961 dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1962
1963 ppd = dd->pport;
1964 for (i = 0; i < dd->num_pports; i++, ppd++)
1965 rvt_init_port(&dd->verbs_dev.rdi,
1966 &ppd->ibport_data.rvp,
1967 i,
1968 ppd->pkeys);
1969
1970 ret = rvt_register_device(&dd->verbs_dev.rdi);
1971 if (ret)
1972 goto err_verbs_txreq;
1973
1974 ret = hfi1_verbs_register_sysfs(dd);
1975 if (ret)
1976 goto err_class;
1977
1978 return ret;
1979
1980 err_class:
1981 rvt_unregister_device(&dd->verbs_dev.rdi);
1982 err_verbs_txreq:
1983 verbs_txreq_exit(dev);
1984 dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1985 return ret;
1986 }
1987
hfi1_unregister_ib_device(struct hfi1_devdata * dd)1988 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1989 {
1990 struct hfi1_ibdev *dev = &dd->verbs_dev;
1991
1992 hfi1_verbs_unregister_sysfs(dd);
1993
1994 rvt_unregister_device(&dd->verbs_dev.rdi);
1995
1996 if (!list_empty(&dev->txwait))
1997 dd_dev_err(dd, "txwait list not empty!\n");
1998 if (!list_empty(&dev->memwait))
1999 dd_dev_err(dd, "memwait list not empty!\n");
2000
2001 del_timer_sync(&dev->mem_timer);
2002 verbs_txreq_exit(dev);
2003
2004 mutex_lock(&cntr_names_lock);
2005 kfree(dev_cntr_names);
2006 kfree(port_cntr_names);
2007 dev_cntr_names = NULL;
2008 port_cntr_names = NULL;
2009 cntr_names_initialized = 0;
2010 mutex_unlock(&cntr_names_lock);
2011 }
2012
hfi1_cnp_rcv(struct hfi1_packet * packet)2013 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2014 {
2015 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
2016 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2017 struct ib_header *hdr = packet->hdr;
2018 struct rvt_qp *qp = packet->qp;
2019 u32 lqpn, rqpn = 0;
2020 u16 rlid = 0;
2021 u8 sl, sc5, svc_type;
2022
2023 switch (packet->qp->ibqp.qp_type) {
2024 case IB_QPT_UC:
2025 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
2026 rqpn = qp->remote_qpn;
2027 svc_type = IB_CC_SVCTYPE_UC;
2028 break;
2029 case IB_QPT_RC:
2030 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
2031 rqpn = qp->remote_qpn;
2032 svc_type = IB_CC_SVCTYPE_RC;
2033 break;
2034 case IB_QPT_SMI:
2035 case IB_QPT_GSI:
2036 case IB_QPT_UD:
2037 svc_type = IB_CC_SVCTYPE_UD;
2038 break;
2039 default:
2040 ibp->rvp.n_pkt_drops++;
2041 return;
2042 }
2043
2044 sc5 = hfi1_9B_get_sc5(hdr, packet->rhf);
2045 sl = ibp->sc_to_sl[sc5];
2046 lqpn = qp->ibqp.qp_num;
2047
2048 process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
2049 }
2050