1 /*
2 * bfin_twi.h - interface to Blackfin TWIs
3 *
4 * Copyright 2005-2014 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #ifndef __ASM_BFIN_TWI_H__
10 #define __ASM_BFIN_TWI_H__
11
12 #include <asm/blackfin.h>
13 #include <linux/types.h>
14 #include <linux/i2c.h>
15
16 /*
17 * ADI twi registers layout
18 */
19 struct bfin_twi_regs {
20 u16 clkdiv;
21 u16 dummy1;
22 u16 control;
23 u16 dummy2;
24 u16 slave_ctl;
25 u16 dummy3;
26 u16 slave_stat;
27 u16 dummy4;
28 u16 slave_addr;
29 u16 dummy5;
30 u16 master_ctl;
31 u16 dummy6;
32 u16 master_stat;
33 u16 dummy7;
34 u16 master_addr;
35 u16 dummy8;
36 u16 int_stat;
37 u16 dummy9;
38 u16 int_mask;
39 u16 dummy10;
40 u16 fifo_ctl;
41 u16 dummy11;
42 u16 fifo_stat;
43 u16 dummy12;
44 u32 __pad[20];
45 u16 xmt_data8;
46 u16 dummy13;
47 u16 xmt_data16;
48 u16 dummy14;
49 u16 rcv_data8;
50 u16 dummy15;
51 u16 rcv_data16;
52 u16 dummy16;
53 };
54
55 struct bfin_twi_iface {
56 int irq;
57 spinlock_t lock;
58 char read_write;
59 u8 command;
60 u8 *transPtr;
61 int readNum;
62 int writeNum;
63 int cur_mode;
64 int manual_stop;
65 int result;
66 struct i2c_adapter adap;
67 struct completion complete;
68 struct i2c_msg *pmsg;
69 int msg_num;
70 int cur_msg;
71 u16 saved_clkdiv;
72 u16 saved_control;
73 struct bfin_twi_regs __iomem *regs_base;
74 };
75
76 /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/
77 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
78 #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
79 #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
80
81 /* TWI_PRESCALE Masks */
82 #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
83 #define TWI_ENA 0x0080 /* TWI Enable */
84 #define SCCB 0x0200 /* SCCB Compatibility Enable */
85
86 /* TWI_SLAVE_CTL Masks */
87 #define SEN 0x0001 /* Slave Enable */
88 #define SADD_LEN 0x0002 /* Slave Address Length */
89 #define STDVAL 0x0004 /* Slave Transmit Data Valid */
90 #define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */
91 #define GEN 0x0010 /* General Call Address Matching Enabled */
92
93 /* TWI_SLAVE_STAT Masks */
94 #define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */
95 #define GCALL 0x0002 /* General Call Indicator */
96
97 /* TWI_MASTER_CTL Masks */
98 #define MEN 0x0001 /* Master Mode Enable */
99 #define MADD_LEN 0x0002 /* Master Address Length */
100 #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
101 #define FAST 0x0008 /* Use Fast Mode Timing Specs */
102 #define STOP 0x0010 /* Issue Stop Condition */
103 #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
104 #define DCNT 0x3FC0 /* Data Bytes To Transfer */
105 #define SDAOVR 0x4000 /* Serial Data Override */
106 #define SCLOVR 0x8000 /* Serial Clock Override */
107
108 /* TWI_MASTER_STAT Masks */
109 #define MPROG 0x0001 /* Master Transfer In Progress */
110 #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
111 #define ANAK 0x0004 /* Address Not Acknowledged */
112 #define DNAK 0x0008 /* Data Not Acknowledged */
113 #define BUFRDERR 0x0010 /* Buffer Read Error */
114 #define BUFWRERR 0x0020 /* Buffer Write Error */
115 #define SDASEN 0x0040 /* Serial Data Sense */
116 #define SCLSEN 0x0080 /* Serial Clock Sense */
117 #define BUSBUSY 0x0100 /* Bus Busy Indicator */
118
119 /* TWI_INT_SRC and TWI_INT_ENABLE Masks */
120 #define SINIT 0x0001 /* Slave Transfer Initiated */
121 #define SCOMP 0x0002 /* Slave Transfer Complete */
122 #define SERR 0x0004 /* Slave Transfer Error */
123 #define SOVF 0x0008 /* Slave Overflow */
124 #define MCOMP 0x0010 /* Master Transfer Complete */
125 #define MERR 0x0020 /* Master Transfer Error */
126 #define XMTSERV 0x0040 /* Transmit FIFO Service */
127 #define RCVSERV 0x0080 /* Receive FIFO Service */
128
129 /* TWI_FIFO_CTRL Masks */
130 #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
131 #define RCVFLUSH 0x0002 /* Receive Buffer Flush */
132 #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
133 #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
134
135 /* TWI_FIFO_STAT Masks */
136 #define XMTSTAT 0x0003 /* Transmit FIFO Status */
137 #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
138 #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
139 #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
140
141 #define RCVSTAT 0x000C /* Receive FIFO Status */
142 #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
143 #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
144 #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
145
146 #define DEFINE_TWI_REG(reg_name, reg) \
147 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
148 { return bfin_read16(&iface->regs_base->reg); } \
149 static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
150 { bfin_write16(&iface->regs_base->reg, v); }
151
DEFINE_TWI_REG(CLKDIV,clkdiv)152 DEFINE_TWI_REG(CLKDIV, clkdiv)
153 DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
154 DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
155 DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
156 DEFINE_TWI_REG(MASTER_CTL, master_ctl)
157 DEFINE_TWI_REG(MASTER_STAT, master_stat)
158 DEFINE_TWI_REG(MASTER_ADDR, master_addr)
159 DEFINE_TWI_REG(INT_STAT, int_stat)
160 DEFINE_TWI_REG(INT_MASK, int_mask)
161 DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
162 DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
163 DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
164 #if !ANOMALY_16000030
165 DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
166 DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
167 #else
168 static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
169 {
170 u16 ret;
171 unsigned long flags;
172
173 flags = hard_local_irq_save();
174 ret = bfin_read16(&iface->regs_base->rcv_data8);
175 hard_local_irq_restore(flags);
176
177 return ret;
178 }
179
180 static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
181 {
182 u16 ret;
183 unsigned long flags;
184
185 flags = hard_local_irq_save();
186 ret = bfin_read16(&iface->regs_base->rcv_data16);
187 hard_local_irq_restore(flags);
188
189 return ret;
190 }
191 #endif
192
193 static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
194 {
195 return bfin_read16(&iface->regs_base->fifo_ctl);
196 }
197
write_FIFO_CTL(struct bfin_twi_iface * iface,u16 v)198 static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
199 {
200 bfin_write16(&iface->regs_base->fifo_ctl, v);
201 SSYNC();
202 }
203
read_CONTROL(struct bfin_twi_iface * iface)204 static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
205 {
206 return bfin_read16(&iface->regs_base->control);
207 }
208
write_CONTROL(struct bfin_twi_iface * iface,u16 v)209 static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
210 {
211 SSYNC();
212 bfin_write16(&iface->regs_base->control, v);
213 }
214 #endif
215