1 /*
2 * PowerPC64 SLB support.
3 *
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 * Based on earlier code written by:
6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
7 * Copyright (c) 2001 Dave Engebretsen
8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17 #include <asm/pgtable.h>
18 #include <asm/mmu.h>
19 #include <asm/mmu_context.h>
20 #include <asm/paca.h>
21 #include <asm/cputable.h>
22 #include <asm/cacheflush.h>
23 #include <asm/smp.h>
24 #include <linux/compiler.h>
25 #include <linux/mm_types.h>
26
27 #include <asm/udbg.h>
28 #include <asm/code-patching.h>
29
30 enum slb_index {
31 LINEAR_INDEX = 0, /* Kernel linear map (0xc000000000000000) */
32 VMALLOC_INDEX = 1, /* Kernel virtual map (0xd000000000000000) */
33 KSTACK_INDEX = 2, /* Kernel stack map */
34 };
35
36 extern void slb_allocate(unsigned long ea);
37
38 #define slb_esid_mask(ssize) \
39 (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
40
mk_esid_data(unsigned long ea,int ssize,enum slb_index index)41 static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
42 enum slb_index index)
43 {
44 return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
45 }
46
mk_vsid_data(unsigned long ea,int ssize,unsigned long flags)47 static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
48 unsigned long flags)
49 {
50 return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
51 ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
52 }
53
slb_shadow_update(unsigned long ea,int ssize,unsigned long flags,enum slb_index index)54 static inline void slb_shadow_update(unsigned long ea, int ssize,
55 unsigned long flags,
56 enum slb_index index)
57 {
58 struct slb_shadow *p = get_slb_shadow();
59
60 /*
61 * Clear the ESID first so the entry is not valid while we are
62 * updating it. No write barriers are needed here, provided
63 * we only update the current CPU's SLB shadow buffer.
64 */
65 WRITE_ONCE(p->save_area[index].esid, 0);
66 WRITE_ONCE(p->save_area[index].vsid, cpu_to_be64(mk_vsid_data(ea, ssize, flags)));
67 WRITE_ONCE(p->save_area[index].esid, cpu_to_be64(mk_esid_data(ea, ssize, index)));
68 }
69
slb_shadow_clear(enum slb_index index)70 static inline void slb_shadow_clear(enum slb_index index)
71 {
72 WRITE_ONCE(get_slb_shadow()->save_area[index].esid, 0);
73 }
74
create_shadowed_slbe(unsigned long ea,int ssize,unsigned long flags,enum slb_index index)75 static inline void create_shadowed_slbe(unsigned long ea, int ssize,
76 unsigned long flags,
77 enum slb_index index)
78 {
79 /*
80 * Updating the shadow buffer before writing the SLB ensures
81 * we don't get a stale entry here if we get preempted by PHYP
82 * between these two statements.
83 */
84 slb_shadow_update(ea, ssize, flags, index);
85
86 asm volatile("slbmte %0,%1" :
87 : "r" (mk_vsid_data(ea, ssize, flags)),
88 "r" (mk_esid_data(ea, ssize, index))
89 : "memory" );
90 }
91
__slb_flush_and_rebolt(void)92 static void __slb_flush_and_rebolt(void)
93 {
94 /* If you change this make sure you change SLB_NUM_BOLTED
95 * and PR KVM appropriately too. */
96 unsigned long linear_llp, vmalloc_llp, lflags, vflags;
97 unsigned long ksp_esid_data, ksp_vsid_data;
98
99 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
100 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
101 lflags = SLB_VSID_KERNEL | linear_llp;
102 vflags = SLB_VSID_KERNEL | vmalloc_llp;
103
104 ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, KSTACK_INDEX);
105 if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) {
106 ksp_esid_data &= ~SLB_ESID_V;
107 ksp_vsid_data = 0;
108 slb_shadow_clear(KSTACK_INDEX);
109 } else {
110 /* Update stack entry; others don't change */
111 slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, KSTACK_INDEX);
112 ksp_vsid_data =
113 be64_to_cpu(get_slb_shadow()->save_area[KSTACK_INDEX].vsid);
114 }
115
116 /* We need to do this all in asm, so we're sure we don't touch
117 * the stack between the slbia and rebolting it. */
118 asm volatile("isync\n"
119 "slbia\n"
120 /* Slot 1 - first VMALLOC segment */
121 "slbmte %0,%1\n"
122 /* Slot 2 - kernel stack */
123 "slbmte %2,%3\n"
124 "isync"
125 :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)),
126 "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, VMALLOC_INDEX)),
127 "r"(ksp_vsid_data),
128 "r"(ksp_esid_data)
129 : "memory");
130 }
131
slb_flush_and_rebolt(void)132 void slb_flush_and_rebolt(void)
133 {
134
135 WARN_ON(!irqs_disabled());
136
137 /*
138 * We can't take a PMU exception in the following code, so hard
139 * disable interrupts.
140 */
141 hard_irq_disable();
142
143 __slb_flush_and_rebolt();
144 get_paca()->slb_cache_ptr = 0;
145 }
146
slb_vmalloc_update(void)147 void slb_vmalloc_update(void)
148 {
149 unsigned long vflags;
150
151 vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
152 slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
153 slb_flush_and_rebolt();
154 }
155
156 /* Helper function to compare esids. There are four cases to handle.
157 * 1. The system is not 1T segment size capable. Use the GET_ESID compare.
158 * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare.
159 * 3. The system is 1T capable, only one of the two addresses is > 1T. This is not a match.
160 * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare.
161 */
esids_match(unsigned long addr1,unsigned long addr2)162 static inline int esids_match(unsigned long addr1, unsigned long addr2)
163 {
164 int esid_1t_count;
165
166 /* System is not 1T segment size capable. */
167 if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
168 return (GET_ESID(addr1) == GET_ESID(addr2));
169
170 esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
171 ((addr2 >> SID_SHIFT_1T) != 0));
172
173 /* both addresses are < 1T */
174 if (esid_1t_count == 0)
175 return (GET_ESID(addr1) == GET_ESID(addr2));
176
177 /* One address < 1T, the other > 1T. Not a match */
178 if (esid_1t_count == 1)
179 return 0;
180
181 /* Both addresses are > 1T. */
182 return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
183 }
184
185 /* Flush all user entries from the segment table of the current processor. */
switch_slb(struct task_struct * tsk,struct mm_struct * mm)186 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
187 {
188 unsigned long offset;
189 unsigned long slbie_data = 0;
190 unsigned long pc = KSTK_EIP(tsk);
191 unsigned long stack = KSTK_ESP(tsk);
192 unsigned long exec_base;
193
194 /*
195 * We need interrupts hard-disabled here, not just soft-disabled,
196 * so that a PMU interrupt can't occur, which might try to access
197 * user memory (to get a stack trace) and possible cause an SLB miss
198 * which would update the slb_cache/slb_cache_ptr fields in the PACA.
199 */
200 hard_irq_disable();
201 offset = get_paca()->slb_cache_ptr;
202 if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
203 offset <= SLB_CACHE_ENTRIES) {
204 int i;
205 asm volatile("isync" : : : "memory");
206 for (i = 0; i < offset; i++) {
207 slbie_data = (unsigned long)get_paca()->slb_cache[i]
208 << SID_SHIFT; /* EA */
209 slbie_data |= user_segment_size(slbie_data)
210 << SLBIE_SSIZE_SHIFT;
211 slbie_data |= SLBIE_C; /* C set for user addresses */
212 asm volatile("slbie %0" : : "r" (slbie_data));
213 }
214 asm volatile("isync" : : : "memory");
215 } else {
216 __slb_flush_and_rebolt();
217 }
218
219 /* Workaround POWER5 < DD2.1 issue */
220 if (offset == 1 || offset > SLB_CACHE_ENTRIES)
221 asm volatile("slbie %0" : : "r" (slbie_data));
222
223 get_paca()->slb_cache_ptr = 0;
224 copy_mm_to_paca(mm);
225
226 /*
227 * preload some userspace segments into the SLB.
228 * Almost all 32 and 64bit PowerPC executables are linked at
229 * 0x10000000 so it makes sense to preload this segment.
230 */
231 exec_base = 0x10000000;
232
233 if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
234 is_kernel_addr(exec_base))
235 return;
236
237 slb_allocate(pc);
238
239 if (!esids_match(pc, stack))
240 slb_allocate(stack);
241
242 if (!esids_match(pc, exec_base) &&
243 !esids_match(stack, exec_base))
244 slb_allocate(exec_base);
245 }
246
patch_slb_encoding(unsigned int * insn_addr,unsigned int immed)247 static inline void patch_slb_encoding(unsigned int *insn_addr,
248 unsigned int immed)
249 {
250
251 /*
252 * This function patches either an li or a cmpldi instruction with
253 * a new immediate value. This relies on the fact that both li
254 * (which is actually addi) and cmpldi both take a 16-bit immediate
255 * value, and it is situated in the same location in the instruction,
256 * ie. bits 16-31 (Big endian bit order) or the lower 16 bits.
257 * The signedness of the immediate operand differs between the two
258 * instructions however this code is only ever patching a small value,
259 * much less than 1 << 15, so we can get away with it.
260 * To patch the value we read the existing instruction, clear the
261 * immediate value, and or in our new value, then write the instruction
262 * back.
263 */
264 unsigned int insn = (*insn_addr & 0xffff0000) | immed;
265 patch_instruction(insn_addr, insn);
266 }
267
268 extern u32 slb_miss_kernel_load_linear[];
269 extern u32 slb_miss_kernel_load_io[];
270 extern u32 slb_compare_rr_to_size[];
271 extern u32 slb_miss_kernel_load_vmemmap[];
272
slb_set_size(u16 size)273 void slb_set_size(u16 size)
274 {
275 if (mmu_slb_size == size)
276 return;
277
278 mmu_slb_size = size;
279 patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
280 }
281
slb_initialize(void)282 void slb_initialize(void)
283 {
284 unsigned long linear_llp, vmalloc_llp, io_llp;
285 unsigned long lflags, vflags;
286 static int slb_encoding_inited;
287 #ifdef CONFIG_SPARSEMEM_VMEMMAP
288 unsigned long vmemmap_llp;
289 #endif
290
291 /* Prepare our SLB miss handler based on our page size */
292 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
293 io_llp = mmu_psize_defs[mmu_io_psize].sllp;
294 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
295 get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
296 #ifdef CONFIG_SPARSEMEM_VMEMMAP
297 vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
298 #endif
299 if (!slb_encoding_inited) {
300 slb_encoding_inited = 1;
301 patch_slb_encoding(slb_miss_kernel_load_linear,
302 SLB_VSID_KERNEL | linear_llp);
303 patch_slb_encoding(slb_miss_kernel_load_io,
304 SLB_VSID_KERNEL | io_llp);
305 patch_slb_encoding(slb_compare_rr_to_size,
306 mmu_slb_size);
307
308 pr_devel("SLB: linear LLP = %04lx\n", linear_llp);
309 pr_devel("SLB: io LLP = %04lx\n", io_llp);
310
311 #ifdef CONFIG_SPARSEMEM_VMEMMAP
312 patch_slb_encoding(slb_miss_kernel_load_vmemmap,
313 SLB_VSID_KERNEL | vmemmap_llp);
314 pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
315 #endif
316 }
317
318 get_paca()->stab_rr = SLB_NUM_BOLTED - 1;
319
320 lflags = SLB_VSID_KERNEL | linear_llp;
321 vflags = SLB_VSID_KERNEL | vmalloc_llp;
322
323 /* Invalidate the entire SLB (even entry 0) & all the ERATS */
324 asm volatile("isync":::"memory");
325 asm volatile("slbmte %0,%0"::"r" (0) : "memory");
326 asm volatile("isync; slbia; isync":::"memory");
327 create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
328 create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
329
330 /* For the boot cpu, we're running on the stack in init_thread_union,
331 * which is in the first segment of the linear mapping, and also
332 * get_paca()->kstack hasn't been initialized yet.
333 * For secondary cpus, we need to bolt the kernel stack entry now.
334 */
335 slb_shadow_clear(KSTACK_INDEX);
336 if (raw_smp_processor_id() != boot_cpuid &&
337 (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
338 create_shadowed_slbe(get_paca()->kstack,
339 mmu_kernel_ssize, lflags, KSTACK_INDEX);
340
341 asm volatile("isync":::"memory");
342 }
343