1 /*
2 * SN2 Platform specific SMP Support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/threads.h>
15 #include <linux/sched.h>
16 #include <linux/mm_types.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/mmzone.h>
21 #include <linux/module.h>
22 #include <linux/bitops.h>
23 #include <linux/nodemask.h>
24 #include <linux/proc_fs.h>
25 #include <linux/seq_file.h>
26
27 #include <asm/processor.h>
28 #include <asm/irq.h>
29 #include <asm/sal.h>
30 #include <asm/delay.h>
31 #include <asm/io.h>
32 #include <asm/smp.h>
33 #include <asm/tlb.h>
34 #include <asm/numa.h>
35 #include <asm/hw_irq.h>
36 #include <asm/current.h>
37 #include <asm/sn/sn_cpuid.h>
38 #include <asm/sn/sn_sal.h>
39 #include <asm/sn/addrs.h>
40 #include <asm/sn/shub_mmr.h>
41 #include <asm/sn/nodepda.h>
42 #include <asm/sn/rw_mmr.h>
43 #include <asm/sn/sn_feature_sets.h>
44
45 DEFINE_PER_CPU(struct ptc_stats, ptcstats);
46 DECLARE_PER_CPU(struct ptc_stats, ptcstats);
47
48 static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
49
50 /* 0 = old algorithm (no IPI flushes), 1 = ipi deadlock flush, 2 = ipi instead of SHUB ptc, >2 = always ipi */
51 static int sn2_flush_opt = 0;
52
53 extern unsigned long
54 sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
55 volatile unsigned long *, unsigned long,
56 volatile unsigned long *, unsigned long);
57 void
58 sn2_ptc_deadlock_recovery(nodemask_t, short, short, int,
59 volatile unsigned long *, unsigned long,
60 volatile unsigned long *, unsigned long);
61
62 /*
63 * Note: some is the following is captured here to make degugging easier
64 * (the macros make more sense if you see the debug patch - not posted)
65 */
66 #define sn2_ptctest 0
67 #define local_node_uses_ptc_ga(sh1) ((sh1) ? 1 : 0)
68 #define max_active_pio(sh1) ((sh1) ? 32 : 7)
69 #define reset_max_active_on_deadlock() 1
70 #define PTC_LOCK(sh1) ((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
71
72 struct ptc_stats {
73 unsigned long ptc_l;
74 unsigned long change_rid;
75 unsigned long shub_ptc_flushes;
76 unsigned long nodes_flushed;
77 unsigned long deadlocks;
78 unsigned long deadlocks2;
79 unsigned long lock_itc_clocks;
80 unsigned long shub_itc_clocks;
81 unsigned long shub_itc_clocks_max;
82 unsigned long shub_ptc_flushes_not_my_mm;
83 unsigned long shub_ipi_flushes;
84 unsigned long shub_ipi_flushes_itc_clocks;
85 };
86
87 #define sn2_ptctest 0
88
wait_piowc(void)89 static inline unsigned long wait_piowc(void)
90 {
91 volatile unsigned long *piows;
92 unsigned long zeroval, ws;
93
94 piows = pda->pio_write_status_addr;
95 zeroval = pda->pio_write_status_val;
96 do {
97 cpu_relax();
98 } while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
99 return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
100 }
101
102 /**
103 * sn_migrate - SN-specific task migration actions
104 * @task: Task being migrated to new CPU
105 *
106 * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
107 * Context switching user threads which have memory-mapped MMIO may cause
108 * PIOs to issue from separate CPUs, thus the PIO writes must be drained
109 * from the previous CPU's Shub before execution resumes on the new CPU.
110 */
sn_migrate(struct task_struct * task)111 void sn_migrate(struct task_struct *task)
112 {
113 pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
114 volatile unsigned long *adr = last_pda->pio_write_status_addr;
115 unsigned long val = last_pda->pio_write_status_val;
116
117 /* Drain PIO writes from old CPU's Shub */
118 while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
119 != val))
120 cpu_relax();
121 }
122
sn_tlb_migrate_finish(struct mm_struct * mm)123 void sn_tlb_migrate_finish(struct mm_struct *mm)
124 {
125 /* flush_tlb_mm is inefficient if more than 1 users of mm */
126 if (mm == current->mm && mm && atomic_read(&mm->mm_users) == 1)
127 flush_tlb_mm(mm);
128 }
129
130 static void
sn2_ipi_flush_all_tlb(struct mm_struct * mm)131 sn2_ipi_flush_all_tlb(struct mm_struct *mm)
132 {
133 unsigned long itc;
134
135 itc = ia64_get_itc();
136 smp_flush_tlb_cpumask(*mm_cpumask(mm));
137 itc = ia64_get_itc() - itc;
138 __this_cpu_add(ptcstats.shub_ipi_flushes_itc_clocks, itc);
139 __this_cpu_inc(ptcstats.shub_ipi_flushes);
140 }
141
142 /**
143 * sn2_global_tlb_purge - globally purge translation cache of virtual address range
144 * @mm: mm_struct containing virtual address range
145 * @start: start of virtual address range
146 * @end: end of virtual address range
147 * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
148 *
149 * Purges the translation caches of all processors of the given virtual address
150 * range.
151 *
152 * Note:
153 * - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
154 * - cpu_vm_mask is converted into a nodemask of the nodes containing the
155 * cpus in cpu_vm_mask.
156 * - if only one bit is set in cpu_vm_mask & it is the current cpu & the
157 * process is purging its own virtual address range, then only the
158 * local TLB needs to be flushed. This flushing can be done using
159 * ptc.l. This is the common case & avoids the global spinlock.
160 * - if multiple cpus have loaded the context, then flushing has to be
161 * done with ptc.g/MMRs under protection of the global ptc_lock.
162 */
163
164 void
sn2_global_tlb_purge(struct mm_struct * mm,unsigned long start,unsigned long end,unsigned long nbits)165 sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
166 unsigned long end, unsigned long nbits)
167 {
168 int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
169 int mymm = (mm == current->active_mm && mm == current->mm);
170 int use_cpu_ptcga;
171 volatile unsigned long *ptc0, *ptc1;
172 unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
173 short nix;
174 nodemask_t nodes_flushed;
175 int active, max_active, deadlock, flush_opt = sn2_flush_opt;
176
177 if (flush_opt > 2) {
178 sn2_ipi_flush_all_tlb(mm);
179 return;
180 }
181
182 nodes_clear(nodes_flushed);
183 i = 0;
184
185 for_each_cpu(cpu, mm_cpumask(mm)) {
186 cnode = cpu_to_node(cpu);
187 node_set(cnode, nodes_flushed);
188 lcpu = cpu;
189 i++;
190 }
191
192 if (i == 0)
193 return;
194
195 preempt_disable();
196
197 if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
198 do {
199 ia64_ptcl(start, nbits << 2);
200 start += (1UL << nbits);
201 } while (start < end);
202 ia64_srlz_i();
203 __this_cpu_inc(ptcstats.ptc_l);
204 preempt_enable();
205 return;
206 }
207
208 if (atomic_read(&mm->mm_users) == 1 && mymm) {
209 flush_tlb_mm(mm);
210 __this_cpu_inc(ptcstats.change_rid);
211 preempt_enable();
212 return;
213 }
214
215 if (flush_opt == 2) {
216 sn2_ipi_flush_all_tlb(mm);
217 preempt_enable();
218 return;
219 }
220
221 itc = ia64_get_itc();
222 nix = nodes_weight(nodes_flushed);
223
224 rr_value = (mm->context << 3) | REGION_NUMBER(start);
225
226 shub1 = is_shub1();
227 if (shub1) {
228 data0 = (1UL << SH1_PTC_0_A_SHFT) |
229 (nbits << SH1_PTC_0_PS_SHFT) |
230 (rr_value << SH1_PTC_0_RID_SHFT) |
231 (1UL << SH1_PTC_0_START_SHFT);
232 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
233 ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
234 } else {
235 data0 = (1UL << SH2_PTC_A_SHFT) |
236 (nbits << SH2_PTC_PS_SHFT) |
237 (1UL << SH2_PTC_START_SHFT);
238 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
239 (rr_value << SH2_PTC_RID_SHFT));
240 ptc1 = NULL;
241 }
242
243
244 mynasid = get_nasid();
245 use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
246 max_active = max_active_pio(shub1);
247
248 itc = ia64_get_itc();
249 spin_lock_irqsave(PTC_LOCK(shub1), flags);
250 itc2 = ia64_get_itc();
251
252 __this_cpu_add(ptcstats.lock_itc_clocks, itc2 - itc);
253 __this_cpu_inc(ptcstats.shub_ptc_flushes);
254 __this_cpu_add(ptcstats.nodes_flushed, nix);
255 if (!mymm)
256 __this_cpu_inc(ptcstats.shub_ptc_flushes_not_my_mm);
257
258 if (use_cpu_ptcga && !mymm) {
259 old_rr = ia64_get_rr(start);
260 ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
261 ia64_srlz_d();
262 }
263
264 wait_piowc();
265 do {
266 if (shub1)
267 data1 = start | (1UL << SH1_PTC_1_START_SHFT);
268 else
269 data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
270 deadlock = 0;
271 active = 0;
272 ibegin = 0;
273 i = 0;
274 for_each_node_mask(cnode, nodes_flushed) {
275 nasid = cnodeid_to_nasid(cnode);
276 if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
277 ia64_ptcga(start, nbits << 2);
278 ia64_srlz_i();
279 } else {
280 ptc0 = CHANGE_NASID(nasid, ptc0);
281 if (ptc1)
282 ptc1 = CHANGE_NASID(nasid, ptc1);
283 pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
284 active++;
285 }
286 if (active >= max_active || i == (nix - 1)) {
287 if ((deadlock = wait_piowc())) {
288 if (flush_opt == 1)
289 goto done;
290 sn2_ptc_deadlock_recovery(nodes_flushed, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
291 if (reset_max_active_on_deadlock())
292 max_active = 1;
293 }
294 active = 0;
295 ibegin = i + 1;
296 }
297 i++;
298 }
299 start += (1UL << nbits);
300 } while (start < end);
301
302 done:
303 itc2 = ia64_get_itc() - itc2;
304 __this_cpu_add(ptcstats.shub_itc_clocks, itc2);
305 if (itc2 > __this_cpu_read(ptcstats.shub_itc_clocks_max))
306 __this_cpu_write(ptcstats.shub_itc_clocks_max, itc2);
307
308 if (old_rr) {
309 ia64_set_rr(start, old_rr);
310 ia64_srlz_d();
311 }
312
313 spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
314
315 if (flush_opt == 1 && deadlock) {
316 __this_cpu_inc(ptcstats.deadlocks);
317 sn2_ipi_flush_all_tlb(mm);
318 }
319
320 preempt_enable();
321 }
322
323 /*
324 * sn2_ptc_deadlock_recovery
325 *
326 * Recover from PTC deadlocks conditions. Recovery requires stepping thru each
327 * TLB flush transaction. The recovery sequence is somewhat tricky & is
328 * coded in assembly language.
329 */
330
331 void
sn2_ptc_deadlock_recovery(nodemask_t nodes,short ib,short ie,int mynasid,volatile unsigned long * ptc0,unsigned long data0,volatile unsigned long * ptc1,unsigned long data1)332 sn2_ptc_deadlock_recovery(nodemask_t nodes, short ib, short ie, int mynasid,
333 volatile unsigned long *ptc0, unsigned long data0,
334 volatile unsigned long *ptc1, unsigned long data1)
335 {
336 short nasid, i;
337 int cnode;
338 unsigned long *piows, zeroval, n;
339
340 __this_cpu_inc(ptcstats.deadlocks);
341
342 piows = (unsigned long *) pda->pio_write_status_addr;
343 zeroval = pda->pio_write_status_val;
344
345 i = 0;
346 for_each_node_mask(cnode, nodes) {
347 if (i < ib)
348 goto next;
349
350 if (i > ie)
351 break;
352
353 nasid = cnodeid_to_nasid(cnode);
354 if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
355 goto next;
356
357 ptc0 = CHANGE_NASID(nasid, ptc0);
358 if (ptc1)
359 ptc1 = CHANGE_NASID(nasid, ptc1);
360
361 n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
362 __this_cpu_add(ptcstats.deadlocks2, n);
363 next:
364 i++;
365 }
366
367 }
368
369 /**
370 * sn_send_IPI_phys - send an IPI to a Nasid and slice
371 * @nasid: nasid to receive the interrupt (may be outside partition)
372 * @physid: physical cpuid to receive the interrupt.
373 * @vector: command to send
374 * @delivery_mode: delivery mechanism
375 *
376 * Sends an IPI (interprocessor interrupt) to the processor specified by
377 * @physid
378 *
379 * @delivery_mode can be one of the following
380 *
381 * %IA64_IPI_DM_INT - pend an interrupt
382 * %IA64_IPI_DM_PMI - pend a PMI
383 * %IA64_IPI_DM_NMI - pend an NMI
384 * %IA64_IPI_DM_INIT - pend an INIT interrupt
385 */
sn_send_IPI_phys(int nasid,long physid,int vector,int delivery_mode)386 void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
387 {
388 long val;
389 unsigned long flags = 0;
390 volatile long *p;
391
392 p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
393 val = (1UL << SH_IPI_INT_SEND_SHFT) |
394 (physid << SH_IPI_INT_PID_SHFT) |
395 ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
396 ((long)vector << SH_IPI_INT_IDX_SHFT) |
397 (0x000feeUL << SH_IPI_INT_BASE_SHFT);
398
399 mb();
400 if (enable_shub_wars_1_1()) {
401 spin_lock_irqsave(&sn2_global_ptc_lock, flags);
402 }
403 pio_phys_write_mmr(p, val);
404 if (enable_shub_wars_1_1()) {
405 wait_piowc();
406 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
407 }
408
409 }
410
411 EXPORT_SYMBOL(sn_send_IPI_phys);
412
413 /**
414 * sn2_send_IPI - send an IPI to a processor
415 * @cpuid: target of the IPI
416 * @vector: command to send
417 * @delivery_mode: delivery mechanism
418 * @redirect: redirect the IPI?
419 *
420 * Sends an IPI (InterProcessor Interrupt) to the processor specified by
421 * @cpuid. @vector specifies the command to send, while @delivery_mode can
422 * be one of the following
423 *
424 * %IA64_IPI_DM_INT - pend an interrupt
425 * %IA64_IPI_DM_PMI - pend a PMI
426 * %IA64_IPI_DM_NMI - pend an NMI
427 * %IA64_IPI_DM_INIT - pend an INIT interrupt
428 */
sn2_send_IPI(int cpuid,int vector,int delivery_mode,int redirect)429 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
430 {
431 long physid;
432 int nasid;
433
434 physid = cpu_physical_id(cpuid);
435 nasid = cpuid_to_nasid(cpuid);
436
437 /* the following is used only when starting cpus at boot time */
438 if (unlikely(nasid == -1))
439 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
440
441 sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
442 }
443
444 #ifdef CONFIG_HOTPLUG_CPU
445 /**
446 * sn_cpu_disable_allowed - Determine if a CPU can be disabled.
447 * @cpu - CPU that is requested to be disabled.
448 *
449 * CPU disable is only allowed on SHub2 systems running with a PROM
450 * that supports CPU disable. It is not permitted to disable the boot processor.
451 */
sn_cpu_disable_allowed(int cpu)452 bool sn_cpu_disable_allowed(int cpu)
453 {
454 if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) {
455 if (cpu != 0)
456 return true;
457 else
458 printk(KERN_WARNING
459 "Disabling the boot processor is not allowed.\n");
460
461 } else
462 printk(KERN_WARNING
463 "CPU disable is not supported on this system.\n");
464
465 return false;
466 }
467 #endif /* CONFIG_HOTPLUG_CPU */
468
469 #ifdef CONFIG_PROC_FS
470
471 #define PTC_BASENAME "sgi_sn/ptc_statistics"
472
sn2_ptc_seq_start(struct seq_file * file,loff_t * offset)473 static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
474 {
475 if (*offset < nr_cpu_ids)
476 return offset;
477 return NULL;
478 }
479
sn2_ptc_seq_next(struct seq_file * file,void * data,loff_t * offset)480 static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
481 {
482 (*offset)++;
483 if (*offset < nr_cpu_ids)
484 return offset;
485 return NULL;
486 }
487
sn2_ptc_seq_stop(struct seq_file * file,void * data)488 static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
489 {
490 }
491
sn2_ptc_seq_show(struct seq_file * file,void * data)492 static int sn2_ptc_seq_show(struct seq_file *file, void *data)
493 {
494 struct ptc_stats *stat;
495 int cpu;
496
497 cpu = *(loff_t *) data;
498
499 if (!cpu) {
500 seq_printf(file,
501 "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2 ipi_fluches ipi_nsec\n");
502 seq_printf(file, "# ptctest %d, flushopt %d\n", sn2_ptctest, sn2_flush_opt);
503 }
504
505 if (cpu < nr_cpu_ids && cpu_online(cpu)) {
506 stat = &per_cpu(ptcstats, cpu);
507 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
508 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
509 stat->deadlocks,
510 1000 * stat->lock_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
511 1000 * stat->shub_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
512 1000 * stat->shub_itc_clocks_max / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
513 stat->shub_ptc_flushes_not_my_mm,
514 stat->deadlocks2,
515 stat->shub_ipi_flushes,
516 1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec);
517 }
518 return 0;
519 }
520
sn2_ptc_proc_write(struct file * file,const char __user * user,size_t count,loff_t * data)521 static ssize_t sn2_ptc_proc_write(struct file *file, const char __user *user, size_t count, loff_t *data)
522 {
523 int cpu;
524 char optstr[64];
525
526 if (count == 0 || count > sizeof(optstr))
527 return -EINVAL;
528 if (copy_from_user(optstr, user, count))
529 return -EFAULT;
530 optstr[count - 1] = '\0';
531 sn2_flush_opt = simple_strtoul(optstr, NULL, 0);
532
533 for_each_online_cpu(cpu)
534 memset(&per_cpu(ptcstats, cpu), 0, sizeof(struct ptc_stats));
535
536 return count;
537 }
538
539 static const struct seq_operations sn2_ptc_seq_ops = {
540 .start = sn2_ptc_seq_start,
541 .next = sn2_ptc_seq_next,
542 .stop = sn2_ptc_seq_stop,
543 .show = sn2_ptc_seq_show
544 };
545
sn2_ptc_proc_open(struct inode * inode,struct file * file)546 static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
547 {
548 return seq_open(file, &sn2_ptc_seq_ops);
549 }
550
551 static const struct file_operations proc_sn2_ptc_operations = {
552 .open = sn2_ptc_proc_open,
553 .read = seq_read,
554 .write = sn2_ptc_proc_write,
555 .llseek = seq_lseek,
556 .release = seq_release,
557 };
558
559 static struct proc_dir_entry *proc_sn2_ptc;
560
sn2_ptc_init(void)561 static int __init sn2_ptc_init(void)
562 {
563 if (!ia64_platform_is("sn2"))
564 return 0;
565
566 proc_sn2_ptc = proc_create(PTC_BASENAME, 0444,
567 NULL, &proc_sn2_ptc_operations);
568 if (!proc_sn2_ptc) {
569 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
570 return -EINVAL;
571 }
572 spin_lock_init(&sn2_global_ptc_lock);
573 return 0;
574 }
575
sn2_ptc_exit(void)576 static void __exit sn2_ptc_exit(void)
577 {
578 remove_proc_entry(PTC_BASENAME, NULL);
579 }
580
581 module_init(sn2_ptc_init);
582 module_exit(sn2_ptc_exit);
583 #endif /* CONFIG_PROC_FS */
584
585