1 /*
2 * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
3 *
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
5 *
6 * This file add support for MD5 and SHA1.
7 *
8 * You could find the datasheet in Documentation/arm/sunxi/README
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15 #include "sun4i-ss.h"
16 #include <linux/scatterlist.h>
17
18 /* This is a totally arbitrary value */
19 #define SS_TIMEOUT 100
20
sun4i_hash_crainit(struct crypto_tfm * tfm)21 int sun4i_hash_crainit(struct crypto_tfm *tfm)
22 {
23 struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
24 struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
25 struct sun4i_ss_alg_template *algt;
26
27 memset(op, 0, sizeof(struct sun4i_tfm_ctx));
28
29 algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
30 op->ss = algt->ss;
31
32 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
33 sizeof(struct sun4i_req_ctx));
34 return 0;
35 }
36
37 /* sun4i_hash_init: initialize request context */
sun4i_hash_init(struct ahash_request * areq)38 int sun4i_hash_init(struct ahash_request *areq)
39 {
40 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
41 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
42 struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
43 struct sun4i_ss_alg_template *algt;
44
45 memset(op, 0, sizeof(struct sun4i_req_ctx));
46
47 algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
48 op->mode = algt->mode;
49
50 return 0;
51 }
52
sun4i_hash_export_md5(struct ahash_request * areq,void * out)53 int sun4i_hash_export_md5(struct ahash_request *areq, void *out)
54 {
55 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
56 struct md5_state *octx = out;
57 int i;
58
59 octx->byte_count = op->byte_count + op->len;
60
61 memcpy(octx->block, op->buf, op->len);
62
63 if (op->byte_count) {
64 for (i = 0; i < 4; i++)
65 octx->hash[i] = op->hash[i];
66 } else {
67 octx->hash[0] = SHA1_H0;
68 octx->hash[1] = SHA1_H1;
69 octx->hash[2] = SHA1_H2;
70 octx->hash[3] = SHA1_H3;
71 }
72
73 return 0;
74 }
75
sun4i_hash_import_md5(struct ahash_request * areq,const void * in)76 int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
77 {
78 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
79 const struct md5_state *ictx = in;
80 int i;
81
82 sun4i_hash_init(areq);
83
84 op->byte_count = ictx->byte_count & ~0x3F;
85 op->len = ictx->byte_count & 0x3F;
86
87 memcpy(op->buf, ictx->block, op->len);
88
89 for (i = 0; i < 4; i++)
90 op->hash[i] = ictx->hash[i];
91
92 return 0;
93 }
94
sun4i_hash_export_sha1(struct ahash_request * areq,void * out)95 int sun4i_hash_export_sha1(struct ahash_request *areq, void *out)
96 {
97 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
98 struct sha1_state *octx = out;
99 int i;
100
101 octx->count = op->byte_count + op->len;
102
103 memcpy(octx->buffer, op->buf, op->len);
104
105 if (op->byte_count) {
106 for (i = 0; i < 5; i++)
107 octx->state[i] = op->hash[i];
108 } else {
109 octx->state[0] = SHA1_H0;
110 octx->state[1] = SHA1_H1;
111 octx->state[2] = SHA1_H2;
112 octx->state[3] = SHA1_H3;
113 octx->state[4] = SHA1_H4;
114 }
115
116 return 0;
117 }
118
sun4i_hash_import_sha1(struct ahash_request * areq,const void * in)119 int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
120 {
121 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
122 const struct sha1_state *ictx = in;
123 int i;
124
125 sun4i_hash_init(areq);
126
127 op->byte_count = ictx->count & ~0x3F;
128 op->len = ictx->count & 0x3F;
129
130 memcpy(op->buf, ictx->buffer, op->len);
131
132 for (i = 0; i < 5; i++)
133 op->hash[i] = ictx->state[i];
134
135 return 0;
136 }
137
138 #define SS_HASH_UPDATE 1
139 #define SS_HASH_FINAL 2
140
141 /*
142 * sun4i_hash_update: update hash engine
143 *
144 * Could be used for both SHA1 and MD5
145 * Write data by step of 32bits and put then in the SS.
146 *
147 * Since we cannot leave partial data and hash state in the engine,
148 * we need to get the hash state at the end of this function.
149 * We can get the hash state every 64 bytes
150 *
151 * So the first work is to get the number of bytes to write to SS modulo 64
152 * The extra bytes will go to a temporary buffer op->buf storing op->len bytes
153 *
154 * So at the begin of update()
155 * if op->len + areq->nbytes < 64
156 * => all data will be written to wait buffer (op->buf) and end=0
157 * if not, write all data from op->buf to the device and position end to
158 * complete to 64bytes
159 *
160 * example 1:
161 * update1 60o => op->len=60
162 * update2 60o => need one more word to have 64 bytes
163 * end=4
164 * so write all data from op->buf and one word of SGs
165 * write remaining data in op->buf
166 * final state op->len=56
167 */
sun4i_hash(struct ahash_request * areq)168 static int sun4i_hash(struct ahash_request *areq)
169 {
170 /*
171 * i is the total bytes read from SGs, to be compared to areq->nbytes
172 * i is important because we cannot rely on SG length since the sum of
173 * SG->length could be greater than areq->nbytes
174 *
175 * end is the position when we need to stop writing to the device,
176 * to be compared to i
177 *
178 * in_i: advancement in the current SG
179 */
180 unsigned int i = 0, end, fill, min_fill, nwait, nbw = 0, j = 0, todo;
181 unsigned int in_i = 0;
182 u32 spaces, rx_cnt = SS_RX_DEFAULT, bf[32] = {0}, v, ivmode = 0;
183 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
184 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
185 struct sun4i_tfm_ctx *tfmctx = crypto_ahash_ctx(tfm);
186 struct sun4i_ss_ctx *ss = tfmctx->ss;
187 struct scatterlist *in_sg = areq->src;
188 struct sg_mapping_iter mi;
189 int in_r, err = 0;
190 size_t copied = 0;
191 __le32 wb = 0;
192
193 dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
194 __func__, crypto_tfm_alg_name(areq->base.tfm),
195 op->byte_count, areq->nbytes, op->mode,
196 op->len, op->hash[0]);
197
198 if (unlikely(!areq->nbytes) && !(op->flags & SS_HASH_FINAL))
199 return 0;
200
201 /* protect against overflow */
202 if (unlikely(areq->nbytes > UINT_MAX - op->len)) {
203 dev_err(ss->dev, "Cannot process too large request\n");
204 return -EINVAL;
205 }
206
207 if (op->len + areq->nbytes < 64 && !(op->flags & SS_HASH_FINAL)) {
208 /* linearize data to op->buf */
209 copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
210 op->buf + op->len, areq->nbytes, 0);
211 op->len += copied;
212 return 0;
213 }
214
215 spin_lock_bh(&ss->slock);
216
217 /*
218 * if some data have been processed before,
219 * we need to restore the partial hash state
220 */
221 if (op->byte_count) {
222 ivmode = SS_IV_ARBITRARY;
223 for (i = 0; i < 5; i++)
224 writel(op->hash[i], ss->base + SS_IV0 + i * 4);
225 }
226 /* Enable the device */
227 writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
228
229 if (!(op->flags & SS_HASH_UPDATE))
230 goto hash_final;
231
232 /* start of handling data */
233 if (!(op->flags & SS_HASH_FINAL)) {
234 end = ((areq->nbytes + op->len) / 64) * 64 - op->len;
235
236 if (end > areq->nbytes || areq->nbytes - end > 63) {
237 dev_err(ss->dev, "ERROR: Bound error %u %u\n",
238 end, areq->nbytes);
239 err = -EINVAL;
240 goto release_ss;
241 }
242 } else {
243 /* Since we have the flag final, we can go up to modulo 4 */
244 if (areq->nbytes < 4)
245 end = 0;
246 else
247 end = ((areq->nbytes + op->len) / 4) * 4 - op->len;
248 }
249
250 /* TODO if SGlen % 4 and !op->len then DMA */
251 i = 1;
252 while (in_sg && i == 1) {
253 if (in_sg->length % 4)
254 i = 0;
255 in_sg = sg_next(in_sg);
256 }
257 if (i == 1 && !op->len && areq->nbytes)
258 dev_dbg(ss->dev, "We can DMA\n");
259
260 i = 0;
261 sg_miter_start(&mi, areq->src, sg_nents(areq->src),
262 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
263 sg_miter_next(&mi);
264 in_i = 0;
265
266 do {
267 /*
268 * we need to linearize in two case:
269 * - the buffer is already used
270 * - the SG does not have enough byte remaining ( < 4)
271 */
272 if (op->len || (mi.length - in_i) < 4) {
273 /*
274 * if we have entered here we have two reason to stop
275 * - the buffer is full
276 * - reach the end
277 */
278 while (op->len < 64 && i < end) {
279 /* how many bytes we can read from current SG */
280 in_r = min(end - i, 64 - op->len);
281 in_r = min_t(size_t, mi.length - in_i, in_r);
282 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
283 op->len += in_r;
284 i += in_r;
285 in_i += in_r;
286 if (in_i == mi.length) {
287 sg_miter_next(&mi);
288 in_i = 0;
289 }
290 }
291 if (op->len > 3 && !(op->len % 4)) {
292 /* write buf to the device */
293 writesl(ss->base + SS_RXFIFO, op->buf,
294 op->len / 4);
295 op->byte_count += op->len;
296 op->len = 0;
297 }
298 }
299 if (mi.length - in_i > 3 && i < end) {
300 /* how many bytes we can read from current SG */
301 in_r = min_t(size_t, mi.length - in_i, areq->nbytes - i);
302 in_r = min_t(size_t, ((mi.length - in_i) / 4) * 4, in_r);
303 /* how many bytes we can write in the device*/
304 todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
305 writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
306 op->byte_count += todo * 4;
307 i += todo * 4;
308 in_i += todo * 4;
309 rx_cnt -= todo;
310 if (!rx_cnt) {
311 spaces = readl(ss->base + SS_FCSR);
312 rx_cnt = SS_RXFIFO_SPACES(spaces);
313 }
314 if (in_i == mi.length) {
315 sg_miter_next(&mi);
316 in_i = 0;
317 }
318 }
319 } while (i < end);
320
321 /*
322 * Now we have written to the device all that we can,
323 * store the remaining bytes in op->buf
324 */
325 if ((areq->nbytes - i) < 64) {
326 while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
327 /* how many bytes we can read from current SG */
328 in_r = min(areq->nbytes - i, 64 - op->len);
329 in_r = min_t(size_t, mi.length - in_i, in_r);
330 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
331 op->len += in_r;
332 i += in_r;
333 in_i += in_r;
334 if (in_i == mi.length) {
335 sg_miter_next(&mi);
336 in_i = 0;
337 }
338 }
339 }
340
341 sg_miter_stop(&mi);
342
343 /*
344 * End of data process
345 * Now if we have the flag final go to finalize part
346 * If not, store the partial hash
347 */
348 if (op->flags & SS_HASH_FINAL)
349 goto hash_final;
350
351 writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
352 i = 0;
353 do {
354 v = readl(ss->base + SS_CTL);
355 i++;
356 } while (i < SS_TIMEOUT && (v & SS_DATA_END));
357 if (unlikely(i >= SS_TIMEOUT)) {
358 dev_err_ratelimited(ss->dev,
359 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
360 i, SS_TIMEOUT, v, areq->nbytes);
361 err = -EIO;
362 goto release_ss;
363 }
364
365 /*
366 * The datasheet isn't very clear about when to retrieve the digest. The
367 * bit SS_DATA_END is cleared when the engine has processed the data and
368 * when the digest is computed *but* it doesn't mean the digest is
369 * available in the digest registers. Hence the delay to be sure we can
370 * read it.
371 */
372 ndelay(1);
373
374 for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
375 op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
376
377 goto release_ss;
378
379 /*
380 * hash_final: finalize hashing operation
381 *
382 * If we have some remaining bytes, we write them.
383 * Then ask the SS for finalizing the hashing operation
384 *
385 * I do not check RX FIFO size in this function since the size is 32
386 * after each enabling and this function neither write more than 32 words.
387 * If we come from the update part, we cannot have more than
388 * 3 remaining bytes to write and SS is fast enough to not care about it.
389 */
390
391 hash_final:
392
393 /* write the remaining words of the wait buffer */
394 if (op->len) {
395 nwait = op->len / 4;
396 if (nwait) {
397 writesl(ss->base + SS_RXFIFO, op->buf, nwait);
398 op->byte_count += 4 * nwait;
399 }
400
401 nbw = op->len - 4 * nwait;
402 if (nbw) {
403 wb = cpu_to_le32(*(u32 *)(op->buf + nwait * 4));
404 wb &= GENMASK((nbw * 8) - 1, 0);
405
406 op->byte_count += nbw;
407 }
408 }
409
410 /* write the remaining bytes of the nbw buffer */
411 wb |= ((1 << 7) << (nbw * 8));
412 bf[j++] = le32_to_cpu(wb);
413
414 /*
415 * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
416 * I take the operations from other MD5/SHA1 implementations
417 */
418
419 /* last block size */
420 fill = 64 - (op->byte_count % 64);
421 min_fill = 2 * sizeof(u32) + (nbw ? 0 : sizeof(u32));
422
423 /* if we can't fill all data, jump to the next 64 block */
424 if (fill < min_fill)
425 fill += 64;
426
427 j += (fill - min_fill) / sizeof(u32);
428
429 /* write the length of data */
430 if (op->mode == SS_OP_SHA1) {
431 __be64 *bits = (__be64 *)&bf[j];
432 *bits = cpu_to_be64(op->byte_count << 3);
433 j += 2;
434 } else {
435 __le64 *bits = (__le64 *)&bf[j];
436 *bits = cpu_to_le64(op->byte_count << 3);
437 j += 2;
438 }
439 writesl(ss->base + SS_RXFIFO, bf, j);
440
441 /* Tell the SS to stop the hashing */
442 writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
443
444 /*
445 * Wait for SS to finish the hash.
446 * The timeout could happen only in case of bad overclocking
447 * or driver bug.
448 */
449 i = 0;
450 do {
451 v = readl(ss->base + SS_CTL);
452 i++;
453 } while (i < SS_TIMEOUT && (v & SS_DATA_END));
454 if (unlikely(i >= SS_TIMEOUT)) {
455 dev_err_ratelimited(ss->dev,
456 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
457 i, SS_TIMEOUT, v, areq->nbytes);
458 err = -EIO;
459 goto release_ss;
460 }
461
462 /*
463 * The datasheet isn't very clear about when to retrieve the digest. The
464 * bit SS_DATA_END is cleared when the engine has processed the data and
465 * when the digest is computed *but* it doesn't mean the digest is
466 * available in the digest registers. Hence the delay to be sure we can
467 * read it.
468 */
469 ndelay(1);
470
471 /* Get the hash from the device */
472 if (op->mode == SS_OP_SHA1) {
473 for (i = 0; i < 5; i++) {
474 v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
475 memcpy(areq->result + i * 4, &v, 4);
476 }
477 } else {
478 for (i = 0; i < 4; i++) {
479 v = cpu_to_le32(readl(ss->base + SS_MD0 + i * 4));
480 memcpy(areq->result + i * 4, &v, 4);
481 }
482 }
483
484 release_ss:
485 writel(0, ss->base + SS_CTL);
486 spin_unlock_bh(&ss->slock);
487 return err;
488 }
489
sun4i_hash_final(struct ahash_request * areq)490 int sun4i_hash_final(struct ahash_request *areq)
491 {
492 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
493
494 op->flags = SS_HASH_FINAL;
495 return sun4i_hash(areq);
496 }
497
sun4i_hash_update(struct ahash_request * areq)498 int sun4i_hash_update(struct ahash_request *areq)
499 {
500 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
501
502 op->flags = SS_HASH_UPDATE;
503 return sun4i_hash(areq);
504 }
505
506 /* sun4i_hash_finup: finalize hashing operation after an update */
sun4i_hash_finup(struct ahash_request * areq)507 int sun4i_hash_finup(struct ahash_request *areq)
508 {
509 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
510
511 op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
512 return sun4i_hash(areq);
513 }
514
515 /* combo of init/update/final functions */
sun4i_hash_digest(struct ahash_request * areq)516 int sun4i_hash_digest(struct ahash_request *areq)
517 {
518 int err;
519 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
520
521 err = sun4i_hash_init(areq);
522 if (err)
523 return err;
524
525 op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
526 return sun4i_hash(areq);
527 }
528