Home
last modified time | relevance | path

Searched defs:val (Results 1 – 25 of 4009) sorted by relevance

12345678910>>...161

/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dtypes.h133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
[all …]
/drivers/net/ethernet/neterion/vxge/
Dvxge-reg.h25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) argument
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) argument
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) argument
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) argument
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) argument
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) argument
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) argument
62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) argument
[all …]
/drivers/gpu/drm/msm/adreno/
Da2xx.xml.h265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
295 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR()
301 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR()
307 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR()
313 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR()
319 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR()
[all …]
Da3xx.xml.h944 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
952 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
958 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
966 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET()
974 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE()
982 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) in A3XX_GRAS_CL_VPORT_YOFFSET()
990 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) in A3XX_GRAS_CL_VPORT_YSCALE()
998 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) in A3XX_GRAS_CL_VPORT_ZOFFSET()
1006 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) in A3XX_GRAS_CL_VPORT_ZSCALE()
1014 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) in A3XX_GRAS_SU_POINT_MINMAX_MIN()
[all …]
Dadreno_pm4.xml.h314 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF()
320 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC()
326 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK()
332 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT()
340 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE()
346 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) in CP_LOAD_STATE_1_EXT_SRC_ADDR()
354 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) in CP_LOAD_STATE4_0_DST_OFF()
360 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) in CP_LOAD_STATE4_0_STATE_SRC()
366 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) in CP_LOAD_STATE4_0_STATE_BLOCK()
372 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE4_0_NUM_UNIT()
[all …]
Da4xx.xml.h851 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
914 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH()
936 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT()
950 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) in A4XX_RB_MSAA_CONTROL_SAMPLES()
965 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) in A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES()
981 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) in A4XX_RB_MRT_CONTROL_ROP_CODE()
987 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) in A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE()
995 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) in A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT()
[all …]
Da5xx.xml.h1001 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR()
1007 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN()
1914 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) in A5XX_VSC_BIN_SIZE_WIDTH()
1920 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) in A5XX_VSC_BIN_SIZE_HEIGHT()
1938 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) in A5XX_VSC_PIPE_CONFIG_REG_X()
1944 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) in A5XX_VSC_PIPE_CONFIG_REG_Y()
1950 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) in A5XX_VSC_PIPE_CONFIG_REG_W()
1956 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) in A5XX_VSC_PIPE_CONFIG_REG_H()
1979 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) in A5XX_VSC_RESOLVE_CNTL_X()
1985 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) in A5XX_VSC_RESOLVE_CNTL_Y()
[all …]
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5.xml.h180 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
186 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
192 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
207 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
213 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
219 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
227 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
233 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
[all …]
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4.xml.h113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
183 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
[all …]
/drivers/gpu/drm/i915/
Dintel_sideband.c43 u32 port, u32 opcode, u32 addr, u32 *val) in vlv_sideband_rw()
82 u32 val = 0; in vlv_punit_read() local
94 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) in vlv_punit_write()
110 u32 val = 0; in vlv_bunit_read() local
118 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) in vlv_bunit_write()
126 u32 val = 0; in vlv_nc_read() local
140 u32 val = 0; in vlv_iosf_sb_read() local
147 u8 port, u32 reg, u32 val) in vlv_iosf_sb_write()
155 u32 val = 0; in vlv_cck_read() local
161 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) in vlv_cck_write()
[all …]
/drivers/hwtracing/coresight/
Dcoresight-etm3x-sysfs.c26 unsigned long val; in nr_addr_cmp_show() local
36 { unsigned long val; in nr_cntr_show() local
47 unsigned long val; in nr_ctxid_cmp_show() local
58 unsigned long flags, val; in etmsr_show() local
80 unsigned long val; in reset_store() local
108 unsigned long val; in mode_show() local
121 unsigned long val; in mode_store() local
193 unsigned long val; in trigger_event_show() local
206 unsigned long val; in trigger_event_store() local
223 unsigned long val; in enable_event_show() local
[all …]
Dcoresight-etm4x-sysfs.c70 unsigned long val; in nr_pe_cmp_show() local
82 unsigned long val; in nr_addr_cmp_show() local
94 unsigned long val; in nr_cntr_show() local
106 unsigned long val; in nr_ext_inp_show() local
118 unsigned long val; in numcidc_show() local
130 unsigned long val; in numvmidc_show() local
142 unsigned long val; in nrseqstate_show() local
154 unsigned long val; in nr_resource_show() local
166 unsigned long val; in nr_ss_cmp_show() local
179 unsigned long val; in reset_store() local
[all …]
/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_tc_u32_parse.h41 int (*val)(struct ch_filter_specification *f, u32 val, u32 mask); member
46 u32 val, u32 mask) in cxgb4_fill_ipv4_tos()
55 u32 val, u32 mask) in cxgb4_fill_ipv4_frag()
77 u32 val, u32 mask) in cxgb4_fill_ipv4_proto()
86 u32 val, u32 mask) in cxgb4_fill_ipv4_src_ip()
95 u32 val, u32 mask) in cxgb4_fill_ipv4_dst_ip()
114 u32 val, u32 mask) in cxgb4_fill_ipv6_tos()
123 u32 val, u32 mask) in cxgb4_fill_ipv6_proto()
132 u32 val, u32 mask) in cxgb4_fill_ipv6_src_ip0()
141 u32 val, u32 mask) in cxgb4_fill_ipv6_src_ip1()
[all …]
/drivers/power/supply/
Dpm2301_charger.c129 static int pm2xxx_reg_read(struct pm2xxx_charger *pm2, int reg, u8 *val) in pm2xxx_reg_read()
148 static int pm2xxx_reg_write(struct pm2xxx_charger *pm2, int reg, u8 val) in pm2xxx_reg_write()
200 static int pm2xxx_charger_batt_therm_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_batt_therm_mngt()
208 static int pm2xxx_charger_die_therm_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_die_therm_mngt()
215 static int pm2xxx_charger_ovv_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_ovv_mngt()
227 static int pm2xxx_charger_wd_exp_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_wd_exp_mngt()
237 static int pm2xxx_charger_vbat_lsig_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_vbat_lsig_mngt()
271 static int pm2xxx_charger_bat_disc_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_bat_disc_mngt()
278 static int pm2xxx_charger_detection(struct pm2xxx_charger *pm2, u8 *val) in pm2xxx_charger_detection()
295 static int pm2xxx_charger_itv_pwr_plug_mngt(struct pm2xxx_charger *pm2, int val) in pm2xxx_charger_itv_pwr_plug_mngt()
[all …]
/drivers/staging/irda/drivers/
Dvia-ircc.h160 #define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1) argument
162 #define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit)) argument
164 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit)) argument
318 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC argument
325 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val) argument
326 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val) argument
327 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val) argument
328 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val) argument
330 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val) argument
331 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val) argument
[all …]
/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP()
156 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL()
162 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT()
168 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) in DSI_VID_CFG0_TRAFFIC_MODE()
185 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) in DSI_VID_CFG1_RGB_SWAP()
193 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) in DSI_ACTIVE_H_START()
199 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) in DSI_ACTIVE_H_END()
207 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) in DSI_ACTIVE_V_START()
[all …]
/drivers/media/pci/cx18/
Dcx18-io.h39 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel_noretry()
44 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel()
61 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel_noretry()
66 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel()
77 void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, in cx18_writel_expect()
99 void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) in cx18_writew_noretry()
104 static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) in cx18_writew()
120 void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) in cx18_writeb_noretry()
125 static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) in cx18_writeb()
146 static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) in cx18_write_reg_noretry()
[all …]
Dcx18-io.c22 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) in cx18_memset_io()
53 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) in cx18_sw1_irq_enable()
60 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) in cx18_sw1_irq_disable()
66 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) in cx18_sw2_irq_enable()
73 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) in cx18_sw2_irq_disable()
79 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) in cx18_sw2_irq_disable_cpu()
88 u32 val; in cx18_setup_page() local
/drivers/staging/media/davinci_vpfe/
Ddm365_ipipe_hw.c40 u32 val; in rsz_set_common_params() local
76 u32 val; in rsz_set_rsz_regs() local
321 u32 val; in rsz_set_y_address() local
336 u32 val; in rsz_set_c_address() local
362 unsigned int val; in resizer_set_outaddr() local
419 u32 val; in ipipe_set_lutdpc_regs() local
475 u32 val; in ipipe_set_otfdpc_regs() local
532 u32 val; in ipipe_set_d2f_regs() local
576 u32 val; in ipipe_set_gic_regs() local
614 u32 val; in ipipe_set_wb_regs() local
[all …]
/drivers/media/dvb-frontends/
Dlg2160.c63 static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val) in lg216x_write_reg()
87 static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val) in lg216x_read_reg()
115 u8 val; member
136 u8 val; in lg216x_set_reg_bit() local
248 u8 val; in lg216x_set_if() local
273 u8 val; in lg2160_agc_fix() local
315 u8 val; in lg2160_agc_polarity() local
335 u8 val; in lg2160_tuner_pwr_save_polarity() local
354 u8 val; in lg2160_spectrum_polarity() local
372 u8 val; in lg2160_tuner_pwr_save() local
[all …]
/drivers/input/mouse/
Delan_i2c_i2c.c71 u16 reg, u8 *val, u16 len) in elan_i2c_read_block()
96 static int elan_i2c_read_cmd(struct i2c_client *client, u16 reg, u8 *val) in elan_i2c_read_cmd()
139 u8 val[256]; in elan_i2c_initialize() local
182 u8 val[2]; in elan_i2c_power_control() local
222 static int elan_i2c_calibrate_result(struct i2c_client *client, u8 *val) in elan_i2c_calibrate_result()
231 u8 val[3]; in elan_i2c_get_baseline_data() local
248 u8 val[3]; in elan_i2c_get_pattern() local
265 u8 val[3]; in elan_i2c_get_version() local
296 u8 val[3]; in elan_i2c_get_sm_version() local
348 u8 val[3]; in elan_i2c_get_product_id() local
[all …]
/drivers/pci/dwc/
Dpcie-designware.c26 int dw_pcie_read(void __iomem *addr, int size, u32 *val) in dw_pcie_read()
47 int dw_pcie_write(void __iomem *addr, int size, u32 val) in dw_pcie_write()
68 u32 val; in __dw_pcie_read_dbi() local
81 size_t size, u32 val) in __dw_pcie_write_dbi()
103 u32 val) in dw_pcie_writel_ob_unroll()
114 u32 retries, val; in dw_pcie_prog_outbound_atu_unroll() local
149 u32 retries, val; in dw_pcie_prog_outbound_atu() local
197 u32 val) in dw_pcie_writel_ib_unroll()
209 u32 retries, val; in dw_pcie_prog_inbound_atu_unroll() local
253 u32 retries, val; in dw_pcie_prog_inbound_atu() local
[all …]
/drivers/staging/iio/meter/
Dade7758_core.c27 int ade7758_spi_write_reg_8(struct device *dev, u8 reg_address, u8 val) in ade7758_spi_write_reg_8()
94 int ade7758_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val) in ade7758_spi_read_reg_8()
132 u16 *val) in ade7758_spi_read_reg_16()
172 u32 *val) in ade7758_spi_read_reg_24()
215 u8 val = 0; in ade7758_read_8bit() local
229 u16 val = 0; in ade7758_read_16bit() local
243 u32 val = 0; in ade7758_read_24bit() local
259 u8 val; in ade7758_write_8bit() local
276 u16 val; in ade7758_write_16bit() local
290 u8 val; in ade7758_reset() local
[all …]
/drivers/clocksource/
Dmtk_timer.c33 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) argument
35 #define GPT_IRQ_ACK(val) BIT((val) - 1) argument
37 #define TIMER_CTRL_REG(val) (0x10 * (val)) argument
38 #define TIMER_CTRL_OP(val) (((val) & 0x3) << 4) argument
46 #define TIMER_CLK_REG(val) (0x04 + (0x10 * (val))) argument
47 #define TIMER_CLK_SRC(val) (((val) & 0x1) << 4) argument
53 #define TIMER_CNT_REG(val) (0x08 + (0x10 * (val))) argument
54 #define TIMER_CMP_REG(val) (0x0C + (0x10 * (val))) argument
80 u32 val; in mtk_clkevt_time_stop() local
96 u32 val; in mtk_clkevt_time_start() local
[all …]
/drivers/tty/serial/
Dbcm63xx_uart.c97 unsigned int val; in bcm_uart_tx_empty() local
108 unsigned int val; in bcm_uart_set_mctrl() local
132 unsigned int val, mctrl; in bcm_uart_get_mctrl() local
152 unsigned int val; in bcm_uart_stop_tx() local
168 unsigned int val; in bcm_uart_start_tx() local
184 unsigned int val; in bcm_uart_stop_rx() local
196 unsigned int val; in bcm_uart_enable_ms() local
209 unsigned int val; in bcm_uart_break_ctl() local
252 unsigned int val; in bcm_uart_do_rx() local
316 unsigned int val, max_count; in bcm_uart_do_tx() local
[all …]

12345678910>>...161