1 /* 2 * Copyright (C) 2015 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ARM64_KVM_HYP_H__ 19 #define __ARM64_KVM_HYP_H__ 20 21 #include <linux/compiler.h> 22 #include <linux/kvm_host.h> 23 #include <asm/kvm_mmu.h> 24 #include <asm/sysreg.h> 25 26 #define __hyp_text __section(.hyp.text) notrace 27 28 #define read_sysreg_elx(r,nvh,vh) \ 29 ({ \ 30 u64 reg; \ 31 asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##nvh),\ 32 DEFINE_MRS_S \ 33 "mrs_s %0, " __stringify(r##vh) "\n"\ 34 UNDEFINE_MRS_S, \ 35 ARM64_HAS_VIRT_HOST_EXTN) \ 36 : "=r" (reg)); \ 37 reg; \ 38 }) 39 40 #define write_sysreg_elx(v,r,nvh,vh) \ 41 do { \ 42 u64 __val = (u64)(v); \ 43 asm volatile(ALTERNATIVE("msr " __stringify(r##nvh) ", %x0",\ 44 DEFINE_MSR_S \ 45 "msr_s " __stringify(r##vh) ", %x0\n"\ 46 UNDEFINE_MSR_S, \ 47 ARM64_HAS_VIRT_HOST_EXTN) \ 48 : : "rZ" (__val)); \ 49 } while (0) 50 51 /* 52 * Unified accessors for registers that have a different encoding 53 * between VHE and non-VHE. They must be specified without their "ELx" 54 * encoding. 55 */ 56 #define read_sysreg_el2(r) \ 57 ({ \ 58 u64 reg; \ 59 asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##_EL2),\ 60 "mrs %0, " __stringify(r##_EL1),\ 61 ARM64_HAS_VIRT_HOST_EXTN) \ 62 : "=r" (reg)); \ 63 reg; \ 64 }) 65 66 #define write_sysreg_el2(v,r) \ 67 do { \ 68 u64 __val = (u64)(v); \ 69 asm volatile(ALTERNATIVE("msr " __stringify(r##_EL2) ", %x0",\ 70 "msr " __stringify(r##_EL1) ", %x0",\ 71 ARM64_HAS_VIRT_HOST_EXTN) \ 72 : : "rZ" (__val)); \ 73 } while (0) 74 75 #define read_sysreg_el0(r) read_sysreg_elx(r, _EL0, _EL02) 76 #define write_sysreg_el0(v,r) write_sysreg_elx(v, r, _EL0, _EL02) 77 #define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12) 78 #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12) 79 80 /* The VHE specific system registers and their encoding */ 81 #define sctlr_EL12 sys_reg(3, 5, 1, 0, 0) 82 #define cpacr_EL12 sys_reg(3, 5, 1, 0, 2) 83 #define ttbr0_EL12 sys_reg(3, 5, 2, 0, 0) 84 #define ttbr1_EL12 sys_reg(3, 5, 2, 0, 1) 85 #define tcr_EL12 sys_reg(3, 5, 2, 0, 2) 86 #define afsr0_EL12 sys_reg(3, 5, 5, 1, 0) 87 #define afsr1_EL12 sys_reg(3, 5, 5, 1, 1) 88 #define esr_EL12 sys_reg(3, 5, 5, 2, 0) 89 #define far_EL12 sys_reg(3, 5, 6, 0, 0) 90 #define mair_EL12 sys_reg(3, 5, 10, 2, 0) 91 #define amair_EL12 sys_reg(3, 5, 10, 3, 0) 92 #define vbar_EL12 sys_reg(3, 5, 12, 0, 0) 93 #define contextidr_EL12 sys_reg(3, 5, 13, 0, 1) 94 #define cntkctl_EL12 sys_reg(3, 5, 14, 1, 0) 95 #define cntp_tval_EL02 sys_reg(3, 5, 14, 2, 0) 96 #define cntp_ctl_EL02 sys_reg(3, 5, 14, 2, 1) 97 #define cntp_cval_EL02 sys_reg(3, 5, 14, 2, 2) 98 #define cntv_tval_EL02 sys_reg(3, 5, 14, 3, 0) 99 #define cntv_ctl_EL02 sys_reg(3, 5, 14, 3, 1) 100 #define cntv_cval_EL02 sys_reg(3, 5, 14, 3, 2) 101 #define spsr_EL12 sys_reg(3, 5, 4, 0, 0) 102 #define elr_EL12 sys_reg(3, 5, 4, 0, 1) 103 104 /** 105 * hyp_alternate_select - Generates patchable code sequences that are 106 * used to switch between two implementations of a function, depending 107 * on the availability of a feature. 108 * 109 * @fname: a symbol name that will be defined as a function returning a 110 * function pointer whose type will match @orig and @alt 111 * @orig: A pointer to the default function, as returned by @fname when 112 * @cond doesn't hold 113 * @alt: A pointer to the alternate function, as returned by @fname 114 * when @cond holds 115 * @cond: a CPU feature (as described in asm/cpufeature.h) 116 */ 117 #define hyp_alternate_select(fname, orig, alt, cond) \ 118 typeof(orig) * __hyp_text fname(void) \ 119 { \ 120 typeof(alt) *val = orig; \ 121 asm volatile(ALTERNATIVE("nop \n", \ 122 "mov %0, %1 \n", \ 123 cond) \ 124 : "+r" (val) : "r" (alt)); \ 125 return val; \ 126 } 127 128 void __vgic_v2_save_state(struct kvm_vcpu *vcpu); 129 void __vgic_v2_restore_state(struct kvm_vcpu *vcpu); 130 int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu); 131 132 void __vgic_v3_save_state(struct kvm_vcpu *vcpu); 133 void __vgic_v3_restore_state(struct kvm_vcpu *vcpu); 134 int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu); 135 136 void __timer_save_state(struct kvm_vcpu *vcpu); 137 void __timer_restore_state(struct kvm_vcpu *vcpu); 138 139 void __sysreg_save_host_state(struct kvm_cpu_context *ctxt); 140 void __sysreg_restore_host_state(struct kvm_cpu_context *ctxt); 141 void __sysreg_save_guest_state(struct kvm_cpu_context *ctxt); 142 void __sysreg_restore_guest_state(struct kvm_cpu_context *ctxt); 143 void __sysreg32_save_state(struct kvm_vcpu *vcpu); 144 void __sysreg32_restore_state(struct kvm_vcpu *vcpu); 145 146 void __debug_save_state(struct kvm_vcpu *vcpu, 147 struct kvm_guest_debug_arch *dbg, 148 struct kvm_cpu_context *ctxt); 149 void __debug_restore_state(struct kvm_vcpu *vcpu, 150 struct kvm_guest_debug_arch *dbg, 151 struct kvm_cpu_context *ctxt); 152 void __debug_cond_save_host_state(struct kvm_vcpu *vcpu); 153 void __debug_cond_restore_host_state(struct kvm_vcpu *vcpu); 154 155 void __fpsimd_save_state(struct user_fpsimd_state *fp_regs); 156 void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs); 157 bool __fpsimd_enabled(void); 158 159 u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt); 160 void __noreturn __hyp_do_panic(unsigned long, ...); 161 162 #endif /* __ARM64_KVM_HYP_H__ */ 163 164