1 /* Intel(R) Ethernet Switch Host Interface Driver 2 * Copyright(c) 2013 - 2016 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19 */ 20 21 #ifndef _FM10K_TYPE_H_ 22 #define _FM10K_TYPE_H_ 23 24 /* forward declaration */ 25 struct fm10k_hw; 26 27 #include <linux/types.h> 28 #include <asm/byteorder.h> 29 #include <linux/etherdevice.h> 30 31 #include "fm10k_mbx.h" 32 33 #define FM10K_DEV_ID_PF 0x15A4 34 #define FM10K_DEV_ID_VF 0x15A5 35 36 #define FM10K_MAX_QUEUES 256 37 #define FM10K_MAX_QUEUES_PF 128 38 #define FM10K_MAX_QUEUES_POOL 16 39 40 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull 41 #define FM10K_STAT_VALID 0x80000000 42 43 /* PCI Bus Info */ 44 #define FM10K_PCIE_LINK_CAP 0x7C 45 #define FM10K_PCIE_LINK_STATUS 0x82 46 #define FM10K_PCIE_LINK_WIDTH 0x3F0 47 #define FM10K_PCIE_LINK_WIDTH_1 0x10 48 #define FM10K_PCIE_LINK_WIDTH_2 0x20 49 #define FM10K_PCIE_LINK_WIDTH_4 0x40 50 #define FM10K_PCIE_LINK_WIDTH_8 0x80 51 #define FM10K_PCIE_LINK_SPEED 0xF 52 #define FM10K_PCIE_LINK_SPEED_2500 0x1 53 #define FM10K_PCIE_LINK_SPEED_5000 0x2 54 #define FM10K_PCIE_LINK_SPEED_8000 0x3 55 56 /* PCIe payload size */ 57 #define FM10K_PCIE_DEV_CAP 0x74 58 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07 59 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00 60 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01 61 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02 62 #define FM10K_PCIE_DEV_CTRL 0x78 63 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0 64 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00 65 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20 66 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40 67 68 /* PCIe MSI-X Capability info */ 69 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2 70 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF 71 #define FM10K_MAX_MSIX_VECTORS 256 72 #define FM10K_MAX_VECTORS_PF 256 73 #define FM10K_MAX_VECTORS_POOL 32 74 75 /* PCIe SR-IOV Info */ 76 #define FM10K_PCIE_SRIOV_CTRL 0x190 77 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10 78 79 #define FM10K_ERR_PARAM -2 80 #define FM10K_ERR_NO_RESOURCES -3 81 #define FM10K_ERR_REQUESTS_PENDING -4 82 #define FM10K_ERR_RESET_REQUESTED -5 83 #define FM10K_ERR_DMA_PENDING -6 84 #define FM10K_ERR_RESET_FAILED -7 85 #define FM10K_ERR_INVALID_MAC_ADDR -8 86 #define FM10K_ERR_INVALID_VALUE -9 87 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF 88 89 /* Start of PF registers */ 90 #define FM10K_CTRL 0x0000 91 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004 92 93 #define FM10K_CTRL_EXT 0x0001 94 #define FM10K_GCR 0x0003 95 #define FM10K_GCR_EXT 0x0005 96 97 /* Interrupt control registers */ 98 #define FM10K_EICR 0x0006 99 #define FM10K_EICR_FAULT_MASK 0x0000003F 100 #define FM10K_EICR_MAILBOX 0x00000040 101 #define FM10K_EICR_SWITCHREADY 0x00000080 102 #define FM10K_EICR_SWITCHNOTREADY 0x00000100 103 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200 104 #define FM10K_EICR_VFLR 0x00000800 105 #define FM10K_EICR_MAXHOLDTIME 0x00001000 106 #define FM10K_EIMR 0x0007 107 #define FM10K_EIMR_PCA_FAULT 0x00000001 108 #define FM10K_EIMR_THI_FAULT 0x00000010 109 #define FM10K_EIMR_FUM_FAULT 0x00000400 110 #define FM10K_EIMR_MAILBOX 0x00001000 111 #define FM10K_EIMR_SWITCHREADY 0x00004000 112 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000 113 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000 114 #define FM10K_EIMR_SRAMERROR 0x00100000 115 #define FM10K_EIMR_VFLR 0x00400000 116 #define FM10K_EIMR_MAXHOLDTIME 0x01000000 117 #define FM10K_EIMR_ALL 0x55555555 118 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0) 119 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1) 120 #define FM10K_FAULT_ADDR_LO 0x0 121 #define FM10K_FAULT_ADDR_HI 0x1 122 #define FM10K_FAULT_SPECINFO 0x2 123 #define FM10K_FAULT_FUNC 0x3 124 #define FM10K_FAULT_SIZE 0x4 125 #define FM10K_FAULT_FUNC_VALID 0x00008000 126 #define FM10K_FAULT_FUNC_PF 0x00004000 127 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00 128 #define FM10K_FAULT_FUNC_VF_SHIFT 8 129 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF 130 131 #define FM10K_PCA_FAULT 0x0008 132 #define FM10K_THI_FAULT 0x0010 133 #define FM10K_FUM_FAULT 0x001C 134 135 /* Rx queue timeout indicator */ 136 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020) 137 138 /* Switch Manager info */ 139 #define FM10K_SM_AREA(_n) ((_n) + 0x0028) 140 141 /* GLORT mapping registers */ 142 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030) 143 #define FM10K_DGLORT_COUNT 8 144 #define FM10K_DGLORTMAP_MASK_SHIFT 16 145 #define FM10K_DGLORTMAP_ANY 0x00000000 146 #define FM10K_DGLORTMAP_NONE 0x0000FFFF 147 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000 148 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038) 149 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4 150 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7 151 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14 152 #define FM10K_DGLORTDEC_QBASE_SHIFT 16 153 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24 154 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000 155 #define FM10K_TUNNEL_CFG 0x0040 156 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16 157 #define FM10K_TUNNEL_CFG_GENEVE 0x0041 158 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050) 159 #define FM10K_SWPRI_MAX 16 160 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800) 161 #define FM10K_RSSRK_SIZE 10 162 #define FM10K_RSSRK_ENTRIES_PER_REG 4 163 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000) 164 #define FM10K_RETA_SIZE 32 165 #define FM10K_RETA_ENTRIES_PER_REG 4 166 #define FM10K_MAX_RSS_INDICES 128 167 168 /* Rate limiting registers */ 169 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000) 170 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF 171 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040) 172 #define FM10K_TC_MAXCREDIT_64K 0x00010000 173 #define FM10K_TC_RATE(_n) ((_n) + 0x2080) 174 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF 175 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000 176 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000 177 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000 178 179 /* DMA control registers */ 180 #define FM10K_DMA_CTRL 0x20C3 181 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001 182 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008 183 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010 184 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080 185 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100 186 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000 187 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000 188 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000 189 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000 190 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000 191 #define FM10K_DMA_CTRL_32_DESC 0x00000000 192 193 #define FM10K_DMA_CTRL2 0x20C4 194 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000 195 196 /* TSO flags configuration 197 * First packet contains all flags except for fin and psh 198 * Middle packet contains only urg and ack 199 * Last packet contains urg, ack, fin, and psh 200 */ 201 #define FM10K_TSO_FLAGS_LOW 0x00300FF6 202 #define FM10K_TSO_FLAGS_HI 0x00000039 203 #define FM10K_DTXTCPFLGL 0x20C5 204 #define FM10K_DTXTCPFLGH 0x20C6 205 206 #define FM10K_TPH_CTRL 0x20C7 207 #define FM10K_MRQC(_n) ((_n) + 0x2100) 208 #define FM10K_MRQC_TCP_IPV4 0x00000001 209 #define FM10K_MRQC_IPV4 0x00000002 210 #define FM10K_MRQC_IPV6 0x00000010 211 #define FM10K_MRQC_TCP_IPV6 0x00000020 212 #define FM10K_MRQC_UDP_IPV4 0x00000040 213 #define FM10K_MRQC_UDP_IPV6 0x00000080 214 215 #define FM10K_TQMAP(_n) ((_n) + 0x2800) 216 #define FM10K_TQMAP_TABLE_SIZE 2048 217 #define FM10K_RQMAP(_n) ((_n) + 0x3000) 218 219 /* Hardware Statistics */ 220 #define FM10K_STATS_TIMEOUT 0x3800 221 #define FM10K_STATS_UR 0x3801 222 #define FM10K_STATS_CA 0x3802 223 #define FM10K_STATS_UM 0x3803 224 #define FM10K_STATS_XEC 0x3804 225 #define FM10K_STATS_VLAN_DROP 0x3805 226 #define FM10K_STATS_LOOPBACK_DROP 0x3806 227 #define FM10K_STATS_NODESC_DROP 0x3807 228 229 /* PCIe state registers */ 230 #define FM10K_PHYADDR 0x381C 231 232 /* Rx ring registers */ 233 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000) 234 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001) 235 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002) 236 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003) 237 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020 238 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200 239 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000 240 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000 241 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004) 242 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005) 243 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006) 244 #define FM10K_RXQCTL_ENABLE 0x00000001 245 #define FM10K_RXQCTL_PF 0x000000FC 246 #define FM10K_RXQCTL_VF_SHIFT 2 247 #define FM10K_RXQCTL_VF 0x00000100 248 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF) 249 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007) 250 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001 251 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200 252 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008) 253 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009) 254 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */ 255 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000 256 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000 257 258 /* Rx Statistics */ 259 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A) 260 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B) 261 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C) 262 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D) 263 264 /* Rx GLORT register */ 265 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E) 266 267 /* Tx ring registers */ 268 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000) 269 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001) 270 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002) 271 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR) 272 * scale which is based on the PCIe speed but the speed information in the PCI 273 * configuration space may not be accurate. The PF already knows the ITR scale 274 * but there is no defined method to pass that information from the PF to the 275 * VF. This is accomplished during VF initialization by temporarily co-opting 276 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for 277 * the VF to retrieve before the VF needs to use the TDLEN register for its 278 * intended purpose, i.e. before the Tx resources are allocated. 279 */ 280 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9 281 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00 282 #define FM10K_TDLEN_ITR_SCALE_GEN1 2 283 #define FM10K_TDLEN_ITR_SCALE_GEN2 1 284 #define FM10K_TDLEN_ITR_SCALE_GEN3 0 285 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003) 286 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020 287 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200 288 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800 289 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000 290 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004) 291 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005) 292 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006) 293 #define FM10K_TXDCTL_ENABLE 0x00004000 294 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16 295 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007) 296 #define FM10K_TXQCTL_PF 0x0000003F 297 #define FM10K_TXQCTL_VF 0x00000040 298 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF) 299 #define FM10K_TXQCTL_PC_SHIFT 7 300 #define FM10K_TXQCTL_PC_MASK 0x00000380 301 #define FM10K_TXQCTL_TC_SHIFT 10 302 #define FM10K_TXQCTL_VID_SHIFT 16 303 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000 304 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000 305 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008) 306 307 /* Tx Statistics */ 308 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009) 309 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A) 310 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B) 311 312 /* Tx Push registers */ 313 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C) 314 #define FM10K_TQDLOC_BASE_32_DESC 0x08 315 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000 316 317 /* Tx GLORT registers */ 318 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D) 319 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E) 320 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001 321 322 /* Interrupt moderation and control registers */ 323 #define FM10K_INT_MAP(_n) ((_n) + 0x10080) 324 #define FM10K_INT_MAP_TIMER0 0x00000000 325 #define FM10K_INT_MAP_TIMER1 0x00000100 326 #define FM10K_INT_MAP_IMMEDIATE 0x00000200 327 #define FM10K_INT_MAP_DISABLE 0x00000300 328 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003) 329 #define FM10K_INT_CTRL 0x12000 330 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400 331 #define FM10K_ITR(_n) ((_n) + 0x12400) 332 #define FM10K_ITR_INTERVAL1_SHIFT 12 333 #define FM10K_ITR_PENDING2 0x10000000 334 #define FM10K_ITR_AUTOMASK 0x20000000 335 #define FM10K_ITR_MASK_SET 0x40000000 336 #define FM10K_ITR_MASK_CLEAR 0x80000000 337 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800) 338 #define FM10K_ITR_REG_COUNT 768 339 #define FM10K_ITR_REG_COUNT_PF 256 340 341 /* Switch manager interrupt registers */ 342 #define FM10K_IP 0x13000 343 #define FM10K_IP_NOTINRESET 0x00000100 344 345 /* VLAN registers */ 346 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000) 347 #define FM10K_VLAN_TABLE_SIZE 128 348 349 /* VLAN specific message offsets */ 350 #define FM10K_VLAN_TABLE_VID_MAX 4096 351 #define FM10K_VLAN_TABLE_VSI_MAX 64 352 #define FM10K_VLAN_LENGTH_SHIFT 16 353 #define FM10K_VLAN_CLEAR BIT(15) 354 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR 355 #define FM10K_VLAN_ALL \ 356 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT) 357 358 /* VF FLR event notification registers */ 359 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844) 360 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846) 361 362 /* Defines for size of uncacheable memories */ 363 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */ 364 #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */ 365 #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START) 366 367 /* Define timeouts for resets and disables */ 368 #define FM10K_QUEUE_DISABLE_TIMEOUT 100 369 #define FM10K_RESET_TIMEOUT 150 370 371 /* Maximum supported combined inner and outer header length for encapsulation */ 372 #define FM10K_TUNNEL_HEADER_LENGTH 184 373 374 /* VF registers */ 375 #define FM10K_VFCTRL 0x00000 376 #define FM10K_VFCTRL_RST 0x00000008 377 #define FM10K_VFINT_MAP 0x00030 378 #define FM10K_VFSYSTIME 0x00040 379 #define FM10K_VFITR(_n) ((_n) + 0x00060) 380 381 enum fm10k_int_source { 382 fm10k_int_mailbox = 0, 383 fm10k_int_pcie_fault = 1, 384 fm10k_int_switch_up_down = 2, 385 fm10k_int_switch_event = 3, 386 fm10k_int_sram = 4, 387 fm10k_int_vflr = 5, 388 fm10k_int_max_hold_time = 6, 389 fm10k_int_sources_max_pf 390 }; 391 392 /* PCIe bus speeds */ 393 enum fm10k_bus_speed { 394 fm10k_bus_speed_unknown = 0, 395 fm10k_bus_speed_2500 = 2500, 396 fm10k_bus_speed_5000 = 5000, 397 fm10k_bus_speed_8000 = 8000, 398 fm10k_bus_speed_reserved 399 }; 400 401 /* PCIe bus widths */ 402 enum fm10k_bus_width { 403 fm10k_bus_width_unknown = 0, 404 fm10k_bus_width_pcie_x1 = 1, 405 fm10k_bus_width_pcie_x2 = 2, 406 fm10k_bus_width_pcie_x4 = 4, 407 fm10k_bus_width_pcie_x8 = 8, 408 fm10k_bus_width_reserved 409 }; 410 411 /* PCIe payload sizes */ 412 enum fm10k_bus_payload { 413 fm10k_bus_payload_unknown = 0, 414 fm10k_bus_payload_128 = 1, 415 fm10k_bus_payload_256 = 2, 416 fm10k_bus_payload_512 = 3, 417 fm10k_bus_payload_reserved 418 }; 419 420 /* Bus parameters */ 421 struct fm10k_bus_info { 422 enum fm10k_bus_speed speed; 423 enum fm10k_bus_width width; 424 enum fm10k_bus_payload payload; 425 }; 426 427 /* Statistics related declarations */ 428 struct fm10k_hw_stat { 429 u64 count; 430 u32 base_l; 431 u32 base_h; 432 }; 433 434 struct fm10k_hw_stats_q { 435 struct fm10k_hw_stat tx_bytes; 436 struct fm10k_hw_stat tx_packets; 437 #define tx_stats_idx tx_packets.base_h 438 struct fm10k_hw_stat rx_bytes; 439 struct fm10k_hw_stat rx_packets; 440 #define rx_stats_idx rx_packets.base_h 441 struct fm10k_hw_stat rx_drops; 442 }; 443 444 struct fm10k_hw_stats { 445 struct fm10k_hw_stat timeout; 446 #define stats_idx timeout.base_h 447 struct fm10k_hw_stat ur; 448 struct fm10k_hw_stat ca; 449 struct fm10k_hw_stat um; 450 struct fm10k_hw_stat xec; 451 struct fm10k_hw_stat vlan_drop; 452 struct fm10k_hw_stat loopback_drop; 453 struct fm10k_hw_stat nodesc_drop; 454 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF]; 455 }; 456 457 /* Establish DGLORT feature priority */ 458 enum fm10k_dglortdec_idx { 459 fm10k_dglort_default = 0, 460 fm10k_dglort_vf_rsvd0 = 1, 461 fm10k_dglort_vf_rss = 2, 462 fm10k_dglort_pf_rsvd0 = 3, 463 fm10k_dglort_pf_queue = 4, 464 fm10k_dglort_pf_vsi = 5, 465 fm10k_dglort_pf_rsvd1 = 6, 466 fm10k_dglort_pf_rss = 7 467 }; 468 469 struct fm10k_dglort_cfg { 470 u16 glort; /* GLORT base */ 471 u16 queue_b; /* Base value for queue */ 472 u8 vsi_b; /* Base value for VSI */ 473 u8 idx; /* index of DGLORTDEC entry */ 474 u8 rss_l; /* RSS indices */ 475 u8 pc_l; /* Priority Class indices */ 476 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */ 477 u8 queue_l; /* Number of bits from GLORT used to determine queue */ 478 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */ 479 u8 inner_rss; /* Boolean value if inner header is used for RSS */ 480 }; 481 482 enum fm10k_pca_fault { 483 PCA_NO_FAULT, 484 PCA_UNMAPPED_ADDR, 485 PCA_BAD_QACCESS_PF, 486 PCA_BAD_QACCESS_VF, 487 PCA_MALICIOUS_REQ, 488 PCA_POISONED_TLP, 489 PCA_TLP_ABORT, 490 __PCA_MAX 491 }; 492 493 enum fm10k_thi_fault { 494 THI_NO_FAULT, 495 THI_MAL_DIS_Q_FAULT, 496 __THI_MAX 497 }; 498 499 enum fm10k_fum_fault { 500 FUM_NO_FAULT, 501 FUM_UNMAPPED_ADDR, 502 FUM_POISONED_TLP, 503 FUM_BAD_VF_QACCESS, 504 FUM_ADD_DECODE_ERR, 505 FUM_RO_ERROR, 506 FUM_QPRC_CRC_ERROR, 507 FUM_CSR_TIMEOUT, 508 FUM_INVALID_TYPE, 509 FUM_INVALID_LENGTH, 510 FUM_INVALID_BE, 511 FUM_INVALID_ALIGN, 512 __FUM_MAX 513 }; 514 515 struct fm10k_fault { 516 u64 address; /* Address at the time fault was detected */ 517 u32 specinfo; /* Extra info on this fault (fault dependent) */ 518 u8 type; /* Fault value dependent on subunit */ 519 u8 func; /* Function number of the fault */ 520 }; 521 522 struct fm10k_mac_ops { 523 /* basic bring-up and tear-down */ 524 s32 (*reset_hw)(struct fm10k_hw *); 525 s32 (*init_hw)(struct fm10k_hw *); 526 s32 (*start_hw)(struct fm10k_hw *); 527 s32 (*stop_hw)(struct fm10k_hw *); 528 s32 (*get_bus_info)(struct fm10k_hw *); 529 s32 (*get_host_state)(struct fm10k_hw *, bool *); 530 s32 (*request_lport_map)(struct fm10k_hw *); 531 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool); 532 s32 (*read_mac_addr)(struct fm10k_hw *); 533 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *, 534 u16, bool, u8); 535 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool); 536 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8); 537 void (*update_int_moderator)(struct fm10k_hw *); 538 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool); 539 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 540 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 541 s32 (*configure_dglort_map)(struct fm10k_hw *, 542 struct fm10k_dglort_cfg *); 543 void (*set_dma_mask)(struct fm10k_hw *, u64); 544 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *); 545 }; 546 547 enum fm10k_mac_type { 548 fm10k_mac_unknown = 0, 549 fm10k_mac_pf, 550 fm10k_mac_vf, 551 fm10k_num_macs 552 }; 553 554 struct fm10k_mac_info { 555 struct fm10k_mac_ops ops; 556 enum fm10k_mac_type type; 557 u8 addr[ETH_ALEN]; 558 u8 perm_addr[ETH_ALEN]; 559 u16 default_vid; 560 u16 max_msix_vectors; 561 u16 max_queues; 562 bool vlan_override; 563 bool get_host_state; 564 bool tx_ready; 565 u32 dglort_map; 566 u8 itr_scale; 567 u64 reset_while_pending; 568 }; 569 570 struct fm10k_swapi_table_info { 571 u32 used; 572 u32 avail; 573 }; 574 575 struct fm10k_swapi_info { 576 u32 status; 577 struct fm10k_swapi_table_info mac; 578 struct fm10k_swapi_table_info nexthop; 579 struct fm10k_swapi_table_info ffu; 580 }; 581 582 enum fm10k_xcast_modes { 583 FM10K_XCAST_MODE_ALLMULTI = 0, 584 FM10K_XCAST_MODE_MULTI = 1, 585 FM10K_XCAST_MODE_PROMISC = 2, 586 FM10K_XCAST_MODE_NONE = 3, 587 FM10K_XCAST_MODE_DISABLE = 4 588 }; 589 590 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */ 591 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */ 592 593 struct fm10k_vf_info { 594 /* mbx must be first field in struct unless all default IOV message 595 * handlers are redone as the assumption is that vf_info starts 596 * at the same offset as the mailbox 597 */ 598 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */ 599 int rate; /* Tx BW cap as defined by OS */ 600 u16 glort; /* resource tag for this VF */ 601 u16 sw_vid; /* Switch API assigned VLAN */ 602 u16 pf_vid; /* PF assigned Default VLAN */ 603 u8 mac[ETH_ALEN]; /* PF Default MAC address */ 604 u8 vsi; /* VSI identifier */ 605 u8 vf_idx; /* which VF this is */ 606 u8 vf_flags; /* flags indicating what modes 607 * are supported for the port 608 */ 609 }; 610 611 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI)) 612 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI)) 613 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC)) 614 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE)) 615 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF) 616 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4) 617 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode)) 618 #define FM10K_VF_FLAG_SET_MODE_NONE \ 619 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE) 620 #define FM10K_VF_FLAG_MULTI_ENABLED \ 621 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \ 622 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \ 623 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC)) 624 625 struct fm10k_iov_ops { 626 /* IOV related bring-up and tear-down */ 627 s32 (*assign_resources)(struct fm10k_hw *, u16, u16); 628 s32 (*configure_tc)(struct fm10k_hw *, u16, int); 629 s32 (*assign_int_moderator)(struct fm10k_hw *, u16); 630 s32 (*assign_default_mac_vlan)(struct fm10k_hw *, 631 struct fm10k_vf_info *); 632 s32 (*reset_resources)(struct fm10k_hw *, 633 struct fm10k_vf_info *); 634 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8); 635 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *); 636 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16); 637 }; 638 639 struct fm10k_iov_info { 640 struct fm10k_iov_ops ops; 641 u16 total_vfs; 642 u16 num_vfs; 643 u16 num_pools; 644 }; 645 646 enum fm10k_devices { 647 fm10k_device_pf, 648 fm10k_device_vf, 649 }; 650 651 struct fm10k_info { 652 enum fm10k_mac_type mac; 653 s32 (*get_invariants)(struct fm10k_hw *); 654 const struct fm10k_mac_ops *mac_ops; 655 const struct fm10k_iov_ops *iov_ops; 656 }; 657 658 struct fm10k_hw { 659 u32 __iomem *hw_addr; 660 void *back; 661 struct fm10k_mac_info mac; 662 struct fm10k_bus_info bus; 663 struct fm10k_bus_info bus_caps; 664 struct fm10k_iov_info iov; 665 struct fm10k_mbx_info mbx; 666 struct fm10k_swapi_info swapi; 667 u16 device_id; 668 u16 vendor_id; 669 u16 subsystem_device_id; 670 u16 subsystem_vendor_id; 671 u8 revision_id; 672 }; 673 674 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 675 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8 676 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8 677 678 /* Transmit Descriptor */ 679 struct fm10k_tx_desc { 680 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 681 __le16 buflen; /* Length of data to be DMAed */ 682 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */ 683 __le16 mss; /* MSS for segmentation offload */ 684 u8 hdrlen; /* Header size for segmentation offload */ 685 u8 flags; /* Status and offload request flags */ 686 }; 687 688 /* Transmit Descriptor Cache Structure */ 689 struct fm10k_tx_desc_cache { 690 struct fm10k_tx_desc tx_desc[256]; 691 }; 692 693 #define FM10K_TXD_FLAG_INT 0x01 694 #define FM10K_TXD_FLAG_TIME 0x02 695 #define FM10K_TXD_FLAG_CSUM 0x04 696 #define FM10K_TXD_FLAG_FTAG 0x10 697 #define FM10K_TXD_FLAG_RS 0x20 698 #define FM10K_TXD_FLAG_LAST 0x40 699 #define FM10K_TXD_FLAG_DONE 0x80 700 701 /* These macros are meant to enable optimal placement of the RS and INT 702 * bits. It will point us to the last descriptor in the cache for either the 703 * start of the packet, or the end of the packet. If the index is actually 704 * at the start of the FIFO it will point to the offset for the last index 705 * in the FIFO to prevent an unnecessary write. 706 */ 707 #define FM10K_TXD_WB_FIFO_SIZE 4 708 709 /* Receive Descriptor - 32B */ 710 union fm10k_rx_desc { 711 struct { 712 __le64 pkt_addr; /* Packet buffer address */ 713 __le64 hdr_addr; /* Header buffer address */ 714 __le64 reserved; /* Empty space, RSS hash */ 715 __le64 timestamp; 716 } q; /* Read, Writeback, 64b quad-words */ 717 struct { 718 __le32 data; /* RSS and header data */ 719 __le32 rss; /* RSS Hash */ 720 __le32 staterr; 721 __le32 vlan_len; 722 __le32 glort; /* sglort/dglort */ 723 } d; /* Writeback, 32b double-words */ 724 struct { 725 __le16 pkt_info; /* RSS, Pkt type */ 726 __le16 hdr_info; /* Splithdr, hdrlen, xC */ 727 __le16 rss_lower; 728 __le16 rss_upper; 729 __le16 status; /* status/error */ 730 __le16 csum_err; /* checksum or extended error value */ 731 __le16 length; /* Packet length */ 732 __le16 vlan; /* VLAN tag */ 733 __le16 dglort; 734 __le16 sglort; 735 } w; /* Writeback, 16b words */ 736 }; 737 738 #define FM10K_RXD_RSSTYPE_MASK 0x000F 739 enum fm10k_rdesc_rss_type { 740 FM10K_RSSTYPE_NONE = 0x0, 741 FM10K_RSSTYPE_IPV4_TCP = 0x1, 742 FM10K_RSSTYPE_IPV4 = 0x2, 743 FM10K_RSSTYPE_IPV6_TCP = 0x3, 744 /* Reserved 0x4 */ 745 FM10K_RSSTYPE_IPV6 = 0x5, 746 /* Reserved 0x6 */ 747 FM10K_RSSTYPE_IPV4_UDP = 0x7, 748 FM10K_RSSTYPE_IPV6_UDP = 0x8 749 /* Reserved 0x9 - 0xF */ 750 }; 751 752 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006 753 enum fm10k_rxdesc_xc { 754 FM10K_XC_UNICAST = 0x0, 755 FM10K_XC_MULTICAST = 0x4, 756 FM10K_XC_BROADCAST = 0x6 757 }; 758 759 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */ 760 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */ 761 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */ 762 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */ 763 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */ 764 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */ 765 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */ 766 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */ 767 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */ 768 769 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */ 770 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */ 771 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */ 772 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */ 773 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */ 774 775 struct fm10k_ftag { 776 __be16 swpri_type_user; 777 __be16 vlan; 778 __be16 sglort; 779 __be16 dglort; 780 }; 781 782 #endif /* _FM10K_TYPE_H */ 783