1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 Google, Inc. 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 /* 17 * IMPORTANT: The following constants must match the ones used and defined in 18 * external/qemu/include/hw/misc/goldfish_pipe.h 19 */ 20 21 #ifndef GOLDFISH_PIPE_QEMU_H 22 #define GOLDFISH_PIPE_QEMU_H 23 24 /* List of bitflags returned in status of CMD_POLL command */ 25 enum PipePollFlags { 26 PIPE_POLL_IN = 1 << 0, 27 PIPE_POLL_OUT = 1 << 1, 28 PIPE_POLL_HUP = 1 << 2 29 }; 30 31 /* Possible status values used to signal errors */ 32 enum PipeErrors { 33 PIPE_ERROR_INVAL = -1, 34 PIPE_ERROR_AGAIN = -2, 35 PIPE_ERROR_NOMEM = -3, 36 PIPE_ERROR_IO = -4 37 }; 38 39 /* Bit-flags used to signal events from the emulator */ 40 enum PipeWakeFlags { 41 /* emulator closed pipe */ 42 PIPE_WAKE_CLOSED = 1 << 0, 43 44 /* pipe can now be read from */ 45 PIPE_WAKE_READ = 1 << 1, 46 47 /* pipe can now be written to */ 48 PIPE_WAKE_WRITE = 1 << 2, 49 50 /* unlock this pipe's DMA buffer */ 51 PIPE_WAKE_UNLOCK_DMA = 1 << 3, 52 53 /* unlock DMA buffer of the pipe shared to this pipe */ 54 PIPE_WAKE_UNLOCK_DMA_SHARED = 1 << 4, 55 }; 56 57 /* Possible pipe closing reasons */ 58 enum PipeCloseReason { 59 /* guest sent a close command */ 60 PIPE_CLOSE_GRACEFUL = 0, 61 62 /* guest rebooted, we're closing the pipes */ 63 PIPE_CLOSE_REBOOT = 1, 64 65 /* close old pipes on snapshot load */ 66 PIPE_CLOSE_LOAD_SNAPSHOT = 2, 67 68 /* some unrecoverable error on the pipe */ 69 PIPE_CLOSE_ERROR = 3, 70 }; 71 72 /* Bit flags for the 'flags' field */ 73 enum PipeFlagsBits { 74 BIT_CLOSED_ON_HOST = 0, /* pipe closed by host */ 75 BIT_WAKE_ON_WRITE = 1, /* want to be woken on writes */ 76 BIT_WAKE_ON_READ = 2, /* want to be woken on reads */ 77 }; 78 79 enum PipeV1Regs { 80 /* write: value = command */ 81 PIPE_V1_REG_COMMAND = 0x00, 82 /* read */ 83 PIPE_V1_REG_STATUS = 0x04, 84 /* read/write: channel id */ 85 PIPE_V1_REG_CHANNEL = 0x08, 86 /* read/write: channel id */ 87 PIPE_V1_REG_CHANNEL_HIGH = 0x30, 88 /* read/write: buffer size */ 89 PIPE_V1_REG_SIZE = 0x0C, 90 /* write: physical address */ 91 PIPE_V1_REG_ADDRESS = 0x10, 92 /* write: physical address */ 93 PIPE_V1_REG_ADDRESS_HIGH = 0x34, 94 /* read: wake flags */ 95 PIPE_V1_REG_WAKES = 0x14, 96 /* read/write: batch data address */ 97 PIPE_V1_REG_PARAMS_ADDR_LOW = 0x18, 98 /* read/write: batch data address */ 99 PIPE_V1_REG_PARAMS_ADDR_HIGH = 0x1C, 100 /* write: batch access */ 101 PIPE_V1_REG_ACCESS_PARAMS = 0x20, 102 /* read: device version */ 103 PIPE_V1_REG_VERSION = 0x24, 104 }; 105 106 enum PipeV2Regs { 107 PIPE_V2_REG_CMD = 0, 108 109 PIPE_V2_REG_SIGNAL_BUFFER_HIGH = 4, 110 PIPE_V2_REG_SIGNAL_BUFFER = 8, 111 PIPE_V2_REG_SIGNAL_BUFFER_COUNT = 12, 112 113 PIPE_V2_REG_OPEN_BUFFER_HIGH = 20, 114 PIPE_V2_REG_OPEN_BUFFER = 24, 115 116 PIPE_V2_REG_VERSION = 36, 117 118 PIPE_V2_REG_GET_SIGNALLED = 48, 119 }; 120 121 enum PipeCmdCode { 122 /* to be used by the pipe device itself */ 123 PIPE_CMD_OPEN = 1, 124 125 PIPE_CMD_CLOSE, 126 PIPE_CMD_POLL, 127 PIPE_CMD_WRITE, 128 PIPE_CMD_WAKE_ON_WRITE, 129 PIPE_CMD_READ, 130 PIPE_CMD_WAKE_ON_READ, 131 132 /* 133 * TODO(zyy): implement a deferred read/write execution to allow 134 * parallel processing of pipe operations on the host. 135 */ 136 PIPE_CMD_WAKE_ON_DONE_IO, 137 PIPE_CMD_DMA_HOST_MAP, 138 PIPE_CMD_DMA_HOST_UNMAP, 139 }; 140 141 #endif /* GOLDFISH_PIPE_QEMU_H */ 142