1 /*
2 * hcd.h - DesignWare HS OTG Controller host-mode declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36 #ifndef __DWC2_HCD_H__
37 #define __DWC2_HCD_H__
38
39 /*
40 * This file contains the structures, constants, and interfaces for the
41 * Host Contoller Driver (HCD)
42 *
43 * The Host Controller Driver (HCD) is responsible for translating requests
44 * from the USB Driver into the appropriate actions on the DWC_otg controller.
45 * It isolates the USBD from the specifics of the controller by providing an
46 * API to the USBD.
47 */
48
49 struct dwc2_qh;
50
51 /**
52 * struct dwc2_host_chan - Software host channel descriptor
53 *
54 * @hc_num: Host channel number, used for register address lookup
55 * @dev_addr: Address of the device
56 * @ep_num: Endpoint of the device
57 * @ep_is_in: Endpoint direction
58 * @speed: Device speed. One of the following values:
59 * - USB_SPEED_LOW
60 * - USB_SPEED_FULL
61 * - USB_SPEED_HIGH
62 * @ep_type: Endpoint type. One of the following values:
63 * - USB_ENDPOINT_XFER_CONTROL: 0
64 * - USB_ENDPOINT_XFER_ISOC: 1
65 * - USB_ENDPOINT_XFER_BULK: 2
66 * - USB_ENDPOINT_XFER_INTR: 3
67 * @max_packet: Max packet size in bytes
68 * @data_pid_start: PID for initial transaction.
69 * 0: DATA0
70 * 1: DATA2
71 * 2: DATA1
72 * 3: MDATA (non-Control EP),
73 * SETUP (Control EP)
74 * @multi_count: Number of additional periodic transactions per
75 * (micro)frame
76 * @xfer_buf: Pointer to current transfer buffer position
77 * @xfer_dma: DMA address of xfer_buf
78 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not
79 * DWORD aligned
80 * @xfer_len: Total number of bytes to transfer
81 * @xfer_count: Number of bytes transferred so far
82 * @start_pkt_count: Packet count at start of transfer
83 * @xfer_started: True if the transfer has been started
84 * @ping: True if a PING request should be issued on this channel
85 * @error_state: True if the error count for this transaction is non-zero
86 * @halt_on_queue: True if this channel should be halted the next time a
87 * request is queued for the channel. This is necessary in
88 * slave mode if no request queue space is available when
89 * an attempt is made to halt the channel.
90 * @halt_pending: True if the host channel has been halted, but the core
91 * is not finished flushing queued requests
92 * @do_split: Enable split for the channel
93 * @complete_split: Enable complete split
94 * @hub_addr: Address of high speed hub for the split
95 * @hub_port: Port of the low/full speed device for the split
96 * @xact_pos: Split transaction position. One of the following values:
97 * - DWC2_HCSPLT_XACTPOS_MID
98 * - DWC2_HCSPLT_XACTPOS_BEGIN
99 * - DWC2_HCSPLT_XACTPOS_END
100 * - DWC2_HCSPLT_XACTPOS_ALL
101 * @requests: Number of requests issued for this channel since it was
102 * assigned to the current transfer (not counting PINGs)
103 * @schinfo: Scheduling micro-frame bitmap
104 * @ntd: Number of transfer descriptors for the transfer
105 * @halt_status: Reason for halting the host channel
106 * @hcint Contents of the HCINT register when the interrupt came
107 * @qh: QH for the transfer being processed by this channel
108 * @hc_list_entry: For linking to list of host channels
109 * @desc_list_addr: Current QH's descriptor list DMA address
110 * @desc_list_sz: Current QH's descriptor list size
111 * @split_order_list_entry: List entry for keeping track of the order of splits
112 *
113 * This structure represents the state of a single host channel when acting in
114 * host mode. It contains the data items needed to transfer packets to an
115 * endpoint via a host channel.
116 */
117 struct dwc2_host_chan {
118 u8 hc_num;
119
120 unsigned dev_addr:7;
121 unsigned ep_num:4;
122 unsigned ep_is_in:1;
123 unsigned speed:4;
124 unsigned ep_type:2;
125 unsigned max_packet:11;
126 unsigned data_pid_start:2;
127 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
128 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
129 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
130 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
131 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
132
133 unsigned multi_count:2;
134
135 u8 *xfer_buf;
136 dma_addr_t xfer_dma;
137 dma_addr_t align_buf;
138 u32 xfer_len;
139 u32 xfer_count;
140 u16 start_pkt_count;
141 u8 xfer_started;
142 u8 do_ping;
143 u8 error_state;
144 u8 halt_on_queue;
145 u8 halt_pending;
146 u8 do_split;
147 u8 complete_split;
148 u8 hub_addr;
149 u8 hub_port;
150 u8 xact_pos;
151 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
152 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
153 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
154 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
155
156 u8 requests;
157 u8 schinfo;
158 u16 ntd;
159 enum dwc2_halt_status halt_status;
160 u32 hcint;
161 struct dwc2_qh *qh;
162 struct list_head hc_list_entry;
163 dma_addr_t desc_list_addr;
164 u32 desc_list_sz;
165 struct list_head split_order_list_entry;
166 };
167
168 struct dwc2_hcd_pipe_info {
169 u8 dev_addr;
170 u8 ep_num;
171 u8 pipe_type;
172 u8 pipe_dir;
173 u16 maxp;
174 u16 maxp_mult;
175 };
176
177 struct dwc2_hcd_iso_packet_desc {
178 u32 offset;
179 u32 length;
180 u32 actual_length;
181 u32 status;
182 };
183
184 struct dwc2_qtd;
185
186 struct dwc2_hcd_urb {
187 void *priv;
188 struct dwc2_qtd *qtd;
189 void *buf;
190 dma_addr_t dma;
191 void *setup_packet;
192 dma_addr_t setup_dma;
193 u32 length;
194 u32 actual_length;
195 u32 status;
196 u32 error_count;
197 u32 packet_count;
198 u32 flags;
199 u16 interval;
200 struct dwc2_hcd_pipe_info pipe_info;
201 struct dwc2_hcd_iso_packet_desc iso_descs[0];
202 };
203
204 /* Phases for control transfers */
205 enum dwc2_control_phase {
206 DWC2_CONTROL_SETUP,
207 DWC2_CONTROL_DATA,
208 DWC2_CONTROL_STATUS,
209 };
210
211 /* Transaction types */
212 enum dwc2_transaction_type {
213 DWC2_TRANSACTION_NONE,
214 DWC2_TRANSACTION_PERIODIC,
215 DWC2_TRANSACTION_NON_PERIODIC,
216 DWC2_TRANSACTION_ALL,
217 };
218
219 /* The number of elements per LS bitmap (per port on multi_tt) */
220 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
221 BITS_PER_LONG)
222
223 /**
224 * struct dwc2_tt - dwc2 data associated with a usb_tt
225 *
226 * @refcount: Number of Queue Heads (QHs) holding a reference.
227 * @usb_tt: Pointer back to the official usb_tt.
228 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted
229 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP
230 * elements (so sizeof(long) times that in bytes).
231 *
232 * This structure is stored in the hcpriv of the official usb_tt.
233 */
234 struct dwc2_tt {
235 int refcount;
236 struct usb_tt *usb_tt;
237 unsigned long periodic_bitmaps[];
238 };
239
240 /**
241 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
242 *
243 * @start_schedule_usecs: The start time on the main bus schedule. Note that
244 * the main bus schedule is tightly packed and this
245 * time should be interpreted as tightly packed (so
246 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
247 * instead of 125 us).
248 * @duration_us: How long this transfer goes.
249 */
250
251 struct dwc2_hs_transfer_time {
252 u32 start_schedule_us;
253 u16 duration_us;
254 };
255
256 /**
257 * struct dwc2_qh - Software queue head structure
258 *
259 * @hsotg: The HCD state structure for the DWC OTG controller
260 * @ep_type: Endpoint type. One of the following values:
261 * - USB_ENDPOINT_XFER_CONTROL
262 * - USB_ENDPOINT_XFER_BULK
263 * - USB_ENDPOINT_XFER_INT
264 * - USB_ENDPOINT_XFER_ISOC
265 * @ep_is_in: Endpoint direction
266 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
267 * @maxp_mult: Multiplier for maxp
268 * @dev_speed: Device speed. One of the following values:
269 * - USB_SPEED_LOW
270 * - USB_SPEED_FULL
271 * - USB_SPEED_HIGH
272 * @data_toggle: Determines the PID of the next data packet for
273 * non-controltransfers. Ignored for control transfers.
274 * One of the following values:
275 * - DWC2_HC_PID_DATA0
276 * - DWC2_HC_PID_DATA1
277 * @ping_state: Ping state
278 * @do_split: Full/low speed endpoint on high-speed hub requires split
279 * @td_first: Index of first activated isochronous transfer descriptor
280 * @td_last: Index of last activated isochronous transfer descriptor
281 * @host_us: Bandwidth in microseconds per transfer as seen by host
282 * @device_us: Bandwidth in microseconds per transfer as seen by device
283 * @host_interval: Interval between transfers as seen by the host. If
284 * the host is high speed and the device is low speed this
285 * will be 8 times device interval.
286 * @device_interval: Interval between transfers as seen by the device.
287 * interval.
288 * @next_active_frame: (Micro)frame _before_ we next need to put something on
289 * the bus. We'll move the qh to active here. If the
290 * host is in high speed mode this will be a uframe. If
291 * the host is in low speed mode this will be a full frame.
292 * @start_active_frame: If we are partway through a split transfer, this will be
293 * what next_active_frame was when we started. Otherwise
294 * it should always be the same as next_active_frame.
295 * @num_hs_transfers: Number of transfers in hs_transfers.
296 * Normally this is 1 but can be more than one for splits.
297 * Always >= 1 unless the host is in low/full speed mode.
298 * @hs_transfers: Transfers that are scheduled as seen by the high speed
299 * bus. Not used if host is in low or full speed mode (but
300 * note that it IS USED if the device is low or full speed
301 * as long as the HOST is in high speed mode).
302 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
303 * schedule that's being used by this device. This
304 * will be on the periodic_bitmap in a
305 * "struct dwc2_tt". Not used if this device is high
306 * speed. Note that this is in "schedule slice" which
307 * is tightly packed.
308 * @ls_duration_us: Duration on the low speed bus schedule.
309 * @ntd: Actual number of transfer descriptors in a list
310 * @dw_align_buf: Used instead of original buffer if its physical address
311 * is not dword-aligned
312 * @dw_align_buf_dma: DMA address for dw_align_buf
313 * @qtd_list: List of QTDs for this QH
314 * @channel: Host channel currently processing transfers for this QH
315 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
316 * schedule
317 * @desc_list: List of transfer descriptors
318 * @desc_list_dma: Physical address of desc_list
319 * @desc_list_sz: Size of descriptors list
320 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
321 * descriptor and indicates original XferSize value for the
322 * descriptor
323 * @unreserve_timer: Timer for releasing periodic reservation.
324 * @dwc2_tt: Pointer to our tt info (or NULL if no tt).
325 * @ttport: Port number within our tt.
326 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
327 * @unreserve_pending: True if we planned to unreserve but haven't yet.
328 * @schedule_low_speed: True if we have a low/full speed component (either the
329 * host is in low/full speed mode or do_split).
330 *
331 * A Queue Head (QH) holds the static characteristics of an endpoint and
332 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
333 * be entered in either the non-periodic or periodic schedule.
334 */
335 struct dwc2_qh {
336 struct dwc2_hsotg *hsotg;
337 u8 ep_type;
338 u8 ep_is_in;
339 u16 maxp;
340 u16 maxp_mult;
341 u8 dev_speed;
342 u8 data_toggle;
343 u8 ping_state;
344 u8 do_split;
345 u8 td_first;
346 u8 td_last;
347 u16 host_us;
348 u16 device_us;
349 u16 host_interval;
350 u16 device_interval;
351 u16 next_active_frame;
352 u16 start_active_frame;
353 s16 num_hs_transfers;
354 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
355 u32 ls_start_schedule_slice;
356 u16 ntd;
357 u8 *dw_align_buf;
358 dma_addr_t dw_align_buf_dma;
359 struct list_head qtd_list;
360 struct dwc2_host_chan *channel;
361 struct list_head qh_list_entry;
362 struct dwc2_dma_desc *desc_list;
363 dma_addr_t desc_list_dma;
364 u32 desc_list_sz;
365 u32 *n_bytes;
366 struct timer_list unreserve_timer;
367 struct dwc2_tt *dwc_tt;
368 int ttport;
369 unsigned tt_buffer_dirty:1;
370 unsigned unreserve_pending:1;
371 unsigned schedule_low_speed:1;
372 };
373
374 /**
375 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
376 *
377 * @control_phase: Current phase for control transfers (Setup, Data, or
378 * Status)
379 * @in_process: Indicates if this QTD is currently processed by HW
380 * @data_toggle: Determines the PID of the next data packet for the
381 * data phase of control transfers. Ignored for other
382 * transfer types. One of the following values:
383 * - DWC2_HC_PID_DATA0
384 * - DWC2_HC_PID_DATA1
385 * @complete_split: Keeps track of the current split type for FS/LS
386 * endpoints on a HS Hub
387 * @isoc_split_pos: Position of the ISOC split in full/low speed
388 * @isoc_frame_index: Index of the next frame descriptor for an isochronous
389 * transfer. A frame descriptor describes the buffer
390 * position and length of the data to be transferred in the
391 * next scheduled (micro)frame of an isochronous transfer.
392 * It also holds status for that transaction. The frame
393 * index starts at 0.
394 * @isoc_split_offset: Position of the ISOC split in the buffer for the
395 * current frame
396 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
397 * @error_count: Holds the number of bus errors that have occurred for
398 * a transaction within this transfer
399 * @n_desc: Number of DMA descriptors for this QTD
400 * @isoc_frame_index_last: Last activated frame (packet) index, used in
401 * descriptor DMA mode only
402 * @urb: URB for this transfer
403 * @qh: Queue head for this QTD
404 * @qtd_list_entry: For linking to the QH's list of QTDs
405 *
406 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
407 * interrupt, or isochronous transfer. A single QTD is created for each URB
408 * (of one of these types) submitted to the HCD. The transfer associated with
409 * a QTD may require one or multiple transactions.
410 *
411 * A QTD is linked to a Queue Head, which is entered in either the
412 * non-periodic or periodic schedule for execution. When a QTD is chosen for
413 * execution, some or all of its transactions may be executed. After
414 * execution, the state of the QTD is updated. The QTD may be retired if all
415 * its transactions are complete or if an error occurred. Otherwise, it
416 * remains in the schedule so more transactions can be executed later.
417 */
418 struct dwc2_qtd {
419 enum dwc2_control_phase control_phase;
420 u8 in_process;
421 u8 data_toggle;
422 u8 complete_split;
423 u8 isoc_split_pos;
424 u16 isoc_frame_index;
425 u16 isoc_split_offset;
426 u16 isoc_td_last;
427 u16 isoc_td_first;
428 u32 ssplit_out_xfer_count;
429 u8 error_count;
430 u8 n_desc;
431 u16 isoc_frame_index_last;
432 struct dwc2_hcd_urb *urb;
433 struct dwc2_qh *qh;
434 struct list_head qtd_list_entry;
435 };
436
437 #ifdef DEBUG
438 struct hc_xfer_info {
439 struct dwc2_hsotg *hsotg;
440 struct dwc2_host_chan *chan;
441 };
442 #endif
443
444 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
445
446 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
dwc2_hsotg_to_hcd(struct dwc2_hsotg * hsotg)447 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
448 {
449 return (struct usb_hcd *)hsotg->priv;
450 }
451
452 /*
453 * Inline used to disable one channel interrupt. Channel interrupts are
454 * disabled when the channel is halted or released by the interrupt handler.
455 * There is no need to handle further interrupts of that type until the
456 * channel is re-assigned. In fact, subsequent handling may cause crashes
457 * because the channel structures are cleaned up when the channel is released.
458 */
disable_hc_int(struct dwc2_hsotg * hsotg,int chnum,u32 intr)459 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
460 {
461 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
462
463 mask &= ~intr;
464 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
465 }
466
467 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
468 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
469 enum dwc2_halt_status halt_status);
470 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
471 struct dwc2_host_chan *chan);
472
473 /*
474 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
475 * are read as 1, they won't clear when written back.
476 */
dwc2_read_hprt0(struct dwc2_hsotg * hsotg)477 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
478 {
479 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
480
481 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
482 return hprt0;
483 }
484
dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info * pipe)485 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
486 {
487 return pipe->ep_num;
488 }
489
dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info * pipe)490 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
491 {
492 return pipe->pipe_type;
493 }
494
dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info * pipe)495 static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe)
496 {
497 return pipe->maxp;
498 }
499
dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info * pipe)500 static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe)
501 {
502 return pipe->maxp_mult;
503 }
504
dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info * pipe)505 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
506 {
507 return pipe->dev_addr;
508 }
509
dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info * pipe)510 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
511 {
512 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
513 }
514
dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info * pipe)515 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
516 {
517 return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
518 }
519
dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info * pipe)520 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
521 {
522 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
523 }
524
dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info * pipe)525 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
526 {
527 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
528 }
529
dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info * pipe)530 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
531 {
532 return pipe->pipe_dir == USB_DIR_IN;
533 }
534
dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info * pipe)535 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
536 {
537 return !dwc2_hcd_is_pipe_in(pipe);
538 }
539
540 int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
541 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
542
543 /* Transaction Execution Functions */
544 enum dwc2_transaction_type dwc2_hcd_select_transactions(
545 struct dwc2_hsotg *hsotg);
546 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
547 enum dwc2_transaction_type tr_type);
548
549 /* Schedule Queue Functions */
550 /* Implemented in hcd_queue.c */
551 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
552 struct dwc2_hcd_urb *urb,
553 gfp_t mem_flags);
554 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
555 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
556 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
557 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
558 int sched_csplit);
559
560 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
561 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
562 struct dwc2_qh *qh);
563
564 /* Unlinks and frees a QTD */
dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg * hsotg,struct dwc2_qtd * qtd,struct dwc2_qh * qh)565 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
566 struct dwc2_qtd *qtd,
567 struct dwc2_qh *qh)
568 {
569 list_del(&qtd->qtd_list_entry);
570 kfree(qtd);
571 qtd = NULL;
572 }
573
574 /* Descriptor DMA support functions */
575 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
576 struct dwc2_qh *qh);
577 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
578 struct dwc2_host_chan *chan, int chnum,
579 enum dwc2_halt_status halt_status);
580
581 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
582 gfp_t mem_flags);
583 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
584
585 /* Check if QH is non-periodic */
586 #define dwc2_qh_is_non_per(_qh_ptr_) \
587 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
588 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
589
590 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
dbg_hc(struct dwc2_host_chan * hc)591 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
dbg_qh(struct dwc2_qh * qh)592 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
dbg_urb(struct urb * urb)593 static inline bool dbg_urb(struct urb *urb) { return true; }
dbg_perio(void)594 static inline bool dbg_perio(void) { return true; }
595 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
dbg_hc(struct dwc2_host_chan * hc)596 static inline bool dbg_hc(struct dwc2_host_chan *hc)
597 {
598 return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
599 hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
600 }
601
dbg_qh(struct dwc2_qh * qh)602 static inline bool dbg_qh(struct dwc2_qh *qh)
603 {
604 return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
605 qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
606 }
607
dbg_urb(struct urb * urb)608 static inline bool dbg_urb(struct urb *urb)
609 {
610 return usb_pipetype(urb->pipe) == PIPE_BULK ||
611 usb_pipetype(urb->pipe) == PIPE_CONTROL;
612 }
613
dbg_perio(void)614 static inline bool dbg_perio(void) { return false; }
615 #endif
616
617 /*
618 * Returns true if frame1 index is greater than frame2 index. The comparison
619 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
620 * frame number when the max index frame number is reached.
621 */
dwc2_frame_idx_num_gt(u16 fr_idx1,u16 fr_idx2)622 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
623 {
624 u16 diff = fr_idx1 - fr_idx2;
625 u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
626
627 return diff && !sign;
628 }
629
630 /*
631 * Returns true if frame1 is less than or equal to frame2. The comparison is
632 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
633 * frame number when the max frame number is reached.
634 */
dwc2_frame_num_le(u16 frame1,u16 frame2)635 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
636 {
637 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
638 }
639
640 /*
641 * Returns true if frame1 is greater than frame2. The comparison is done
642 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
643 * number when the max frame number is reached.
644 */
dwc2_frame_num_gt(u16 frame1,u16 frame2)645 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
646 {
647 return (frame1 != frame2) &&
648 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
649 }
650
651 /*
652 * Increments frame by the amount specified by inc. The addition is done
653 * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
654 */
dwc2_frame_num_inc(u16 frame,u16 inc)655 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
656 {
657 return (frame + inc) & HFNUM_MAX_FRNUM;
658 }
659
dwc2_frame_num_dec(u16 frame,u16 dec)660 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
661 {
662 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
663 }
664
dwc2_full_frame_num(u16 frame)665 static inline u16 dwc2_full_frame_num(u16 frame)
666 {
667 return (frame & HFNUM_MAX_FRNUM) >> 3;
668 }
669
dwc2_micro_frame_num(u16 frame)670 static inline u16 dwc2_micro_frame_num(u16 frame)
671 {
672 return frame & 0x7;
673 }
674
675 /*
676 * Returns the Core Interrupt Status register contents, ANDed with the Core
677 * Interrupt Mask register contents
678 */
dwc2_read_core_intr(struct dwc2_hsotg * hsotg)679 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
680 {
681 return dwc2_readl(hsotg->regs + GINTSTS) &
682 dwc2_readl(hsotg->regs + GINTMSK);
683 }
684
dwc2_hcd_urb_get_status(struct dwc2_hcd_urb * dwc2_urb)685 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
686 {
687 return dwc2_urb->status;
688 }
689
dwc2_hcd_urb_get_actual_length(struct dwc2_hcd_urb * dwc2_urb)690 static inline u32 dwc2_hcd_urb_get_actual_length(
691 struct dwc2_hcd_urb *dwc2_urb)
692 {
693 return dwc2_urb->actual_length;
694 }
695
dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb * dwc2_urb)696 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
697 {
698 return dwc2_urb->error_count;
699 }
700
dwc2_hcd_urb_set_iso_desc_params(struct dwc2_hcd_urb * dwc2_urb,int desc_num,u32 offset,u32 length)701 static inline void dwc2_hcd_urb_set_iso_desc_params(
702 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
703 u32 length)
704 {
705 dwc2_urb->iso_descs[desc_num].offset = offset;
706 dwc2_urb->iso_descs[desc_num].length = length;
707 }
708
dwc2_hcd_urb_get_iso_desc_status(struct dwc2_hcd_urb * dwc2_urb,int desc_num)709 static inline u32 dwc2_hcd_urb_get_iso_desc_status(
710 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
711 {
712 return dwc2_urb->iso_descs[desc_num].status;
713 }
714
dwc2_hcd_urb_get_iso_desc_actual_length(struct dwc2_hcd_urb * dwc2_urb,int desc_num)715 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
716 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
717 {
718 return dwc2_urb->iso_descs[desc_num].actual_length;
719 }
720
dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg * hsotg,struct usb_host_endpoint * ep)721 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
722 struct usb_host_endpoint *ep)
723 {
724 struct dwc2_qh *qh = ep->hcpriv;
725
726 if (qh && !list_empty(&qh->qh_list_entry))
727 return 1;
728
729 return 0;
730 }
731
dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg * hsotg,struct usb_host_endpoint * ep)732 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
733 struct usb_host_endpoint *ep)
734 {
735 struct dwc2_qh *qh = ep->hcpriv;
736
737 if (!qh) {
738 WARN_ON(1);
739 return 0;
740 }
741
742 return qh->host_us;
743 }
744
745 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
746 struct dwc2_host_chan *chan, int chnum,
747 struct dwc2_qtd *qtd);
748
749 /* HCD Core API */
750
751 /**
752 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
753 *
754 * @hsotg: The DWC2 HCD
755 *
756 * Returns IRQ_HANDLED if interrupt is handled
757 * Return IRQ_NONE if interrupt is not handled
758 */
759 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
760
761 /**
762 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
763 *
764 * @hsotg: The DWC2 HCD
765 */
766 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
767
768 /**
769 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
770 * and 0 otherwise
771 *
772 * @hsotg: The DWC2 HCD
773 */
774 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
775
776 /**
777 * dwc2_hcd_dump_state() - Dumps hsotg state
778 *
779 * @hsotg: The DWC2 HCD
780 *
781 * NOTE: This function will be removed once the peripheral controller code
782 * is integrated and the driver is stable
783 */
784 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
785
786 /**
787 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
788 *
789 * @hsotg: The DWC2 HCD
790 *
791 * This can be used to determine average interrupt latency. Frame remaining is
792 * also shown for start transfer and two additional sample points.
793 *
794 * NOTE: This function will be removed once the peripheral controller code
795 * is integrated and the driver is stable
796 */
797 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
798
799 /* URB interface */
800
801 /* Transfer flags */
802 #define URB_GIVEBACK_ASAP 0x1
803 #define URB_SEND_ZERO_PACKET 0x2
804
805 /* Host driver callbacks */
806 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
807 void *context, gfp_t mem_flags,
808 int *ttport);
809
810 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
811 struct dwc2_tt *dwc_tt);
812 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
813 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
814 int status);
815
816 #ifdef DEBUG
817 /*
818 * Macro to sample the remaining PHY clocks left in the current frame. This
819 * may be used during debugging to determine the average time it takes to
820 * execute sections of code. There are two possible sample points, "a" and
821 * "b", so the _letter_ argument must be one of these values.
822 *
823 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
824 * example, "cat /sys/devices/lm0/hcd_frrem".
825 */
826 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \
827 do { \
828 struct hfnum_data _hfnum_; \
829 struct dwc2_qtd *_qtd_; \
830 \
831 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \
832 qtd_list_entry); \
833 if (usb_pipeint(_qtd_->urb->pipe) && \
834 (_qh_)->start_active_frame != 0 && !_qtd_->complete_split) { \
835 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \
836 switch (_hfnum_.b.frnum & 0x7) { \
837 case 7: \
838 (_hcd_)->hfnum_7_samples_##_letter_++; \
839 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \
840 _hfnum_.b.frrem; \
841 break; \
842 case 0: \
843 (_hcd_)->hfnum_0_samples_##_letter_++; \
844 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \
845 _hfnum_.b.frrem; \
846 break; \
847 default: \
848 (_hcd_)->hfnum_other_samples_##_letter_++; \
849 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \
850 _hfnum_.b.frrem; \
851 break; \
852 } \
853 } \
854 } while (0)
855 #else
856 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0)
857 #endif
858
859 #endif /* __DWC2_HCD_H__ */
860