1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define DEFAULT_UAR_PAGE_SHIFT 12
48
49 #define MAX_MSIX_P_PORT 17
50 #define MAX_MSIX 64
51 #define MIN_MSIX_P_PORT 5
52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
54
55 #define MLX4_MAX_100M_UNITS_VAL 255 /*
56 * work around: can't set values
57 * greater then this value when
58 * using 100 Mbps units.
59 */
60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63
64 #define MLX4_ROCE_MAX_GIDS 128
65 #define MLX4_ROCE_PF_GIDS 16
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7,
75 MLX4_FLAG_SECURE_HOST = 1 << 8,
76 };
77
78 enum {
79 MLX4_PORT_CAP_IS_SM = 1 << 1,
80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
81 };
82
83 enum {
84 MLX4_MAX_PORTS = 2,
85 MLX4_MAX_PORT_PKEYS = 128,
86 MLX4_MAX_PORT_GIDS = 128
87 };
88
89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
90 * These qkeys must not be allowed for general use. This is a 64k range,
91 * and to test for violation, we use the mask (protect against future chg).
92 */
93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
95
96 enum {
97 MLX4_BOARD_ID_LEN = 64
98 };
99
100 enum {
101 MLX4_MAX_NUM_PF = 16,
102 MLX4_MAX_NUM_VF = 126,
103 MLX4_MAX_NUM_VF_P_PORT = 64,
104 MLX4_MFUNC_MAX = 128,
105 MLX4_MAX_EQ_NUM = 1024,
106 MLX4_MFUNC_EQ_NUM = 4,
107 MLX4_MFUNC_MAX_EQES = 8,
108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
109 };
110
111 /* Driver supports 3 different device methods to manage traffic steering:
112 * -device managed - High level API for ib and eth flow steering. FW is
113 * managing flow steering tables.
114 * - B0 steering mode - Common low level API for ib and (if supported) eth.
115 * - A0 steering mode - Limited low level API for eth. In case of IB,
116 * B0 mode is in use.
117 */
118 enum {
119 MLX4_STEERING_MODE_A0,
120 MLX4_STEERING_MODE_B0,
121 MLX4_STEERING_MODE_DEVICE_MANAGED
122 };
123
124 enum {
125 MLX4_STEERING_DMFS_A0_DEFAULT,
126 MLX4_STEERING_DMFS_A0_DYNAMIC,
127 MLX4_STEERING_DMFS_A0_STATIC,
128 MLX4_STEERING_DMFS_A0_DISABLE,
129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
130 };
131
mlx4_steering_mode_str(int steering_mode)132 static inline const char *mlx4_steering_mode_str(int steering_mode)
133 {
134 switch (steering_mode) {
135 case MLX4_STEERING_MODE_A0:
136 return "A0 steering";
137
138 case MLX4_STEERING_MODE_B0:
139 return "B0 steering";
140
141 case MLX4_STEERING_MODE_DEVICE_MANAGED:
142 return "Device managed flow steering";
143
144 default:
145 return "Unrecognize steering mode";
146 }
147 }
148
149 enum {
150 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
152 };
153
154 enum {
155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
186 };
187
188 enum {
189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
227 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38,
228 };
229
230 enum {
231 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
232 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
233 };
234
235 enum {
236 MLX4_VF_CAP_FLAG_RESET = 1 << 0
237 };
238
239 /* bit enums for an 8-bit flags field indicating special use
240 * QPs which require special handling in qp_reserve_range.
241 * Currently, this only includes QPs used by the ETH interface,
242 * where we expect to use blueflame. These QPs must not have
243 * bits 6 and 7 set in their qp number.
244 *
245 * This enum may use only bits 0..7.
246 */
247 enum {
248 MLX4_RESERVE_A0_QP = 1 << 6,
249 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
250 };
251
252 enum {
253 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
254 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
255 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
256 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
257 };
258
259 enum {
260 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
261 };
262
263 enum {
264 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
265 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
266 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
267 };
268
269
270 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
271
272 enum {
273 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
274 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
275 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
276 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
277 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
278 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
279 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
280 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
281 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
282 };
283
284 enum {
285 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
286 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
287 };
288
289 enum mlx4_event {
290 MLX4_EVENT_TYPE_COMP = 0x00,
291 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
292 MLX4_EVENT_TYPE_COMM_EST = 0x02,
293 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
294 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
295 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
296 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
297 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
298 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
299 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
300 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
301 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
302 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
303 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
304 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
305 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
306 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
307 MLX4_EVENT_TYPE_CMD = 0x0a,
308 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
309 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
310 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
311 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
312 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
313 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
314 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
315 MLX4_EVENT_TYPE_NONE = 0xff,
316 };
317
318 enum {
319 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
320 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
321 };
322
323 enum {
324 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
325 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
326 };
327
328 enum {
329 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
330 };
331
332 enum slave_port_state {
333 SLAVE_PORT_DOWN = 0,
334 SLAVE_PENDING_UP,
335 SLAVE_PORT_UP,
336 };
337
338 enum slave_port_gen_event {
339 SLAVE_PORT_GEN_EVENT_DOWN = 0,
340 SLAVE_PORT_GEN_EVENT_UP,
341 SLAVE_PORT_GEN_EVENT_NONE,
342 };
343
344 enum slave_port_state_event {
345 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
346 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
347 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
348 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
349 };
350
351 enum {
352 MLX4_PERM_LOCAL_READ = 1 << 10,
353 MLX4_PERM_LOCAL_WRITE = 1 << 11,
354 MLX4_PERM_REMOTE_READ = 1 << 12,
355 MLX4_PERM_REMOTE_WRITE = 1 << 13,
356 MLX4_PERM_ATOMIC = 1 << 14,
357 MLX4_PERM_BIND_MW = 1 << 15,
358 MLX4_PERM_MASK = 0xFC00
359 };
360
361 enum {
362 MLX4_OPCODE_NOP = 0x00,
363 MLX4_OPCODE_SEND_INVAL = 0x01,
364 MLX4_OPCODE_RDMA_WRITE = 0x08,
365 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
366 MLX4_OPCODE_SEND = 0x0a,
367 MLX4_OPCODE_SEND_IMM = 0x0b,
368 MLX4_OPCODE_LSO = 0x0e,
369 MLX4_OPCODE_RDMA_READ = 0x10,
370 MLX4_OPCODE_ATOMIC_CS = 0x11,
371 MLX4_OPCODE_ATOMIC_FA = 0x12,
372 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
373 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
374 MLX4_OPCODE_BIND_MW = 0x18,
375 MLX4_OPCODE_FMR = 0x19,
376 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
377 MLX4_OPCODE_CONFIG_CMD = 0x1f,
378
379 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
380 MLX4_RECV_OPCODE_SEND = 0x01,
381 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
382 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
383
384 MLX4_CQE_OPCODE_ERROR = 0x1e,
385 MLX4_CQE_OPCODE_RESIZE = 0x16,
386 };
387
388 enum {
389 MLX4_STAT_RATE_OFFSET = 5
390 };
391
392 enum mlx4_protocol {
393 MLX4_PROT_IB_IPV6 = 0,
394 MLX4_PROT_ETH,
395 MLX4_PROT_IB_IPV4,
396 MLX4_PROT_FCOE
397 };
398
399 enum {
400 MLX4_MTT_FLAG_PRESENT = 1
401 };
402
403 enum mlx4_qp_region {
404 MLX4_QP_REGION_FW = 0,
405 MLX4_QP_REGION_RSS_RAW_ETH,
406 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
407 MLX4_QP_REGION_ETH_ADDR,
408 MLX4_QP_REGION_FC_ADDR,
409 MLX4_QP_REGION_FC_EXCH,
410 MLX4_NUM_QP_REGION
411 };
412
413 enum mlx4_port_type {
414 MLX4_PORT_TYPE_NONE = 0,
415 MLX4_PORT_TYPE_IB = 1,
416 MLX4_PORT_TYPE_ETH = 2,
417 MLX4_PORT_TYPE_AUTO = 3
418 };
419
420 enum mlx4_special_vlan_idx {
421 MLX4_NO_VLAN_IDX = 0,
422 MLX4_VLAN_MISS_IDX,
423 MLX4_VLAN_REGULAR
424 };
425
426 enum mlx4_steer_type {
427 MLX4_MC_STEER = 0,
428 MLX4_UC_STEER,
429 MLX4_NUM_STEERS
430 };
431
432 enum mlx4_resource_usage {
433 MLX4_RES_USAGE_NONE,
434 MLX4_RES_USAGE_DRIVER,
435 MLX4_RES_USAGE_USER_VERBS,
436 };
437
438 enum {
439 MLX4_NUM_FEXCH = 64 * 1024,
440 };
441
442 enum {
443 MLX4_MAX_FAST_REG_PAGES = 511,
444 };
445
446 enum {
447 /*
448 * Max wqe size for rdma read is 512 bytes, so this
449 * limits our max_sge_rd as the wqe needs to fit:
450 * - ctrl segment (16 bytes)
451 * - rdma segment (16 bytes)
452 * - scatter elements (16 bytes each)
453 */
454 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
455 };
456
457 enum {
458 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
459 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
460 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
461 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
462 };
463
464 /* Port mgmt change event handling */
465 enum {
466 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
467 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
468 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
469 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
470 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
471 };
472
473 union sl2vl_tbl_to_u64 {
474 u8 sl8[8];
475 u64 sl64;
476 };
477
478 enum {
479 MLX4_DEVICE_STATE_UP = 1 << 0,
480 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
481 };
482
483 enum {
484 MLX4_INTERFACE_STATE_UP = 1 << 0,
485 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
486 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2,
487 };
488
489 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
490 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
491
492 enum mlx4_module_id {
493 MLX4_MODULE_ID_SFP = 0x3,
494 MLX4_MODULE_ID_QSFP = 0xC,
495 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
496 MLX4_MODULE_ID_QSFP28 = 0x11,
497 };
498
499 enum { /* rl */
500 MLX4_QP_RATE_LIMIT_NONE = 0,
501 MLX4_QP_RATE_LIMIT_KBS = 1,
502 MLX4_QP_RATE_LIMIT_MBS = 2,
503 MLX4_QP_RATE_LIMIT_GBS = 3
504 };
505
506 struct mlx4_rate_limit_caps {
507 u16 num_rates; /* Number of different rates */
508 u8 min_unit;
509 u16 min_val;
510 u8 max_unit;
511 u16 max_val;
512 };
513
mlx4_fw_ver(u64 major,u64 minor,u64 subminor)514 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
515 {
516 return (major << 32) | (minor << 16) | subminor;
517 }
518
519 struct mlx4_phys_caps {
520 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
521 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
522 u32 num_phys_eqs;
523 u32 base_sqpn;
524 u32 base_proxy_sqpn;
525 u32 base_tunnel_sqpn;
526 };
527
528 struct mlx4_spec_qps {
529 u32 qp0_qkey;
530 u32 qp0_proxy;
531 u32 qp0_tunnel;
532 u32 qp1_proxy;
533 u32 qp1_tunnel;
534 };
535
536 struct mlx4_caps {
537 u64 fw_ver;
538 u32 function;
539 int num_ports;
540 int vl_cap[MLX4_MAX_PORTS + 1];
541 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
542 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
543 u64 def_mac[MLX4_MAX_PORTS + 1];
544 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
545 int gid_table_len[MLX4_MAX_PORTS + 1];
546 int pkey_table_len[MLX4_MAX_PORTS + 1];
547 int trans_type[MLX4_MAX_PORTS + 1];
548 int vendor_oui[MLX4_MAX_PORTS + 1];
549 int wavelength[MLX4_MAX_PORTS + 1];
550 u64 trans_code[MLX4_MAX_PORTS + 1];
551 int local_ca_ack_delay;
552 int num_uars;
553 u32 uar_page_size;
554 int bf_reg_size;
555 int bf_regs_per_page;
556 int max_sq_sg;
557 int max_rq_sg;
558 int num_qps;
559 int max_wqes;
560 int max_sq_desc_sz;
561 int max_rq_desc_sz;
562 int max_qp_init_rdma;
563 int max_qp_dest_rdma;
564 int max_tc_eth;
565 struct mlx4_spec_qps *spec_qps;
566 int num_srqs;
567 int max_srq_wqes;
568 int max_srq_sge;
569 int reserved_srqs;
570 int num_cqs;
571 int max_cqes;
572 int reserved_cqs;
573 int num_sys_eqs;
574 int num_eqs;
575 int reserved_eqs;
576 int num_comp_vectors;
577 int num_mpts;
578 int max_fmr_maps;
579 int num_mtts;
580 int fmr_reserved_mtts;
581 int reserved_mtts;
582 int reserved_mrws;
583 int reserved_uars;
584 int num_mgms;
585 int num_amgms;
586 int reserved_mcgs;
587 int num_qp_per_mgm;
588 int steering_mode;
589 int dmfs_high_steer_mode;
590 int fs_log_max_ucast_qp_range_size;
591 int num_pds;
592 int reserved_pds;
593 int max_xrcds;
594 int reserved_xrcds;
595 int mtt_entry_sz;
596 u32 max_msg_sz;
597 u32 page_size_cap;
598 u64 flags;
599 u64 flags2;
600 u32 bmme_flags;
601 u32 reserved_lkey;
602 u16 stat_rate_support;
603 u8 port_width_cap[MLX4_MAX_PORTS + 1];
604 int max_gso_sz;
605 int max_rss_tbl_sz;
606 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
607 int reserved_qps;
608 int reserved_qps_base[MLX4_NUM_QP_REGION];
609 int log_num_macs;
610 int log_num_vlans;
611 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
612 u8 supported_type[MLX4_MAX_PORTS + 1];
613 u8 suggested_type[MLX4_MAX_PORTS + 1];
614 u8 default_sense[MLX4_MAX_PORTS + 1];
615 u32 port_mask[MLX4_MAX_PORTS + 1];
616 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
617 u32 max_counters;
618 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
619 u16 sqp_demux;
620 u32 eqe_size;
621 u32 cqe_size;
622 u8 eqe_factor;
623 u32 userspace_caps; /* userspace must be aware of these */
624 u32 function_caps; /* VFs must be aware of these */
625 u16 hca_core_clock;
626 u64 phys_port_id[MLX4_MAX_PORTS + 1];
627 int tunnel_offload_mode;
628 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
629 u8 phv_bit[MLX4_MAX_PORTS + 1];
630 u8 alloc_res_qp_mask;
631 u32 dmfs_high_rate_qpn_base;
632 u32 dmfs_high_rate_qpn_range;
633 u32 vf_caps;
634 bool wol_port[MLX4_MAX_PORTS + 1];
635 struct mlx4_rate_limit_caps rl_caps;
636 };
637
638 struct mlx4_buf_list {
639 void *buf;
640 dma_addr_t map;
641 };
642
643 struct mlx4_buf {
644 struct mlx4_buf_list direct;
645 struct mlx4_buf_list *page_list;
646 int nbufs;
647 int npages;
648 int page_shift;
649 };
650
651 struct mlx4_mtt {
652 u32 offset;
653 int order;
654 int page_shift;
655 };
656
657 enum {
658 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
659 };
660
661 struct mlx4_db_pgdir {
662 struct list_head list;
663 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
664 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
665 unsigned long *bits[2];
666 __be32 *db_page;
667 dma_addr_t db_dma;
668 };
669
670 struct mlx4_ib_user_db_page;
671
672 struct mlx4_db {
673 __be32 *db;
674 union {
675 struct mlx4_db_pgdir *pgdir;
676 struct mlx4_ib_user_db_page *user_page;
677 } u;
678 dma_addr_t dma;
679 int index;
680 int order;
681 };
682
683 struct mlx4_hwq_resources {
684 struct mlx4_db db;
685 struct mlx4_mtt mtt;
686 struct mlx4_buf buf;
687 };
688
689 struct mlx4_mr {
690 struct mlx4_mtt mtt;
691 u64 iova;
692 u64 size;
693 u32 key;
694 u32 pd;
695 u32 access;
696 int enabled;
697 };
698
699 enum mlx4_mw_type {
700 MLX4_MW_TYPE_1 = 1,
701 MLX4_MW_TYPE_2 = 2,
702 };
703
704 struct mlx4_mw {
705 u32 key;
706 u32 pd;
707 enum mlx4_mw_type type;
708 int enabled;
709 };
710
711 struct mlx4_fmr {
712 struct mlx4_mr mr;
713 struct mlx4_mpt_entry *mpt;
714 __be64 *mtts;
715 dma_addr_t dma_handle;
716 int max_pages;
717 int max_maps;
718 int maps;
719 u8 page_shift;
720 };
721
722 struct mlx4_uar {
723 unsigned long pfn;
724 int index;
725 struct list_head bf_list;
726 unsigned free_bf_bmap;
727 void __iomem *map;
728 void __iomem *bf_map;
729 };
730
731 struct mlx4_bf {
732 unsigned int offset;
733 int buf_size;
734 struct mlx4_uar *uar;
735 void __iomem *reg;
736 };
737
738 struct mlx4_cq {
739 void (*comp) (struct mlx4_cq *);
740 void (*event) (struct mlx4_cq *, enum mlx4_event);
741
742 struct mlx4_uar *uar;
743
744 u32 cons_index;
745
746 u16 irq;
747 __be32 *set_ci_db;
748 __be32 *arm_db;
749 int arm_sn;
750
751 int cqn;
752 unsigned vector;
753
754 atomic_t refcount;
755 struct completion free;
756 struct {
757 struct list_head list;
758 void (*comp)(struct mlx4_cq *);
759 void *priv;
760 } tasklet_ctx;
761 int reset_notify_added;
762 struct list_head reset_notify;
763 u8 usage;
764 };
765
766 struct mlx4_qp {
767 void (*event) (struct mlx4_qp *, enum mlx4_event);
768
769 int qpn;
770
771 atomic_t refcount;
772 struct completion free;
773 u8 usage;
774 };
775
776 struct mlx4_srq {
777 void (*event) (struct mlx4_srq *, enum mlx4_event);
778
779 int srqn;
780 int max;
781 int max_gs;
782 int wqe_shift;
783
784 atomic_t refcount;
785 struct completion free;
786 };
787
788 struct mlx4_av {
789 __be32 port_pd;
790 u8 reserved1;
791 u8 g_slid;
792 __be16 dlid;
793 u8 reserved2;
794 u8 gid_index;
795 u8 stat_rate;
796 u8 hop_limit;
797 __be32 sl_tclass_flowlabel;
798 u8 dgid[16];
799 };
800
801 struct mlx4_eth_av {
802 __be32 port_pd;
803 u8 reserved1;
804 u8 smac_idx;
805 u16 reserved2;
806 u8 reserved3;
807 u8 gid_index;
808 u8 stat_rate;
809 u8 hop_limit;
810 __be32 sl_tclass_flowlabel;
811 u8 dgid[16];
812 u8 s_mac[6];
813 u8 reserved4[2];
814 __be16 vlan;
815 u8 mac[ETH_ALEN];
816 };
817
818 union mlx4_ext_av {
819 struct mlx4_av ib;
820 struct mlx4_eth_av eth;
821 };
822
823 /* Counters should be saturate once they reach their maximum value */
824 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
825 if ((value) > U32_MAX) \
826 counter = cpu_to_be32(U32_MAX); \
827 else \
828 counter = cpu_to_be32(value); \
829 } while (0)
830
831 struct mlx4_counter {
832 u8 reserved1[3];
833 u8 counter_mode;
834 __be32 num_ifc;
835 u32 reserved2[2];
836 __be64 rx_frames;
837 __be64 rx_bytes;
838 __be64 tx_frames;
839 __be64 tx_bytes;
840 };
841
842 struct mlx4_quotas {
843 int qp;
844 int cq;
845 int srq;
846 int mpt;
847 int mtt;
848 int counter;
849 int xrcd;
850 };
851
852 struct mlx4_vf_dev {
853 u8 min_port;
854 u8 n_ports;
855 };
856
857 enum mlx4_pci_status {
858 MLX4_PCI_STATUS_DISABLED,
859 MLX4_PCI_STATUS_ENABLED,
860 };
861
862 struct mlx4_dev_persistent {
863 struct pci_dev *pdev;
864 struct mlx4_dev *dev;
865 int nvfs[MLX4_MAX_PORTS + 1];
866 int num_vfs;
867 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
868 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
869 struct work_struct catas_work;
870 struct workqueue_struct *catas_wq;
871 struct mutex device_state_mutex; /* protect HW state */
872 u8 state;
873 struct mutex interface_state_mutex; /* protect SW state */
874 u8 interface_state;
875 struct mutex pci_status_mutex; /* sync pci state */
876 enum mlx4_pci_status pci_status;
877 };
878
879 struct mlx4_dev {
880 struct mlx4_dev_persistent *persist;
881 unsigned long flags;
882 unsigned long num_slaves;
883 struct mlx4_caps caps;
884 struct mlx4_phys_caps phys_caps;
885 struct mlx4_quotas quotas;
886 struct radix_tree_root qp_table_tree;
887 u8 rev_id;
888 u8 port_random_macs;
889 char board_id[MLX4_BOARD_ID_LEN];
890 int numa_node;
891 int oper_log_mgm_entry_size;
892 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
893 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
894 struct mlx4_vf_dev *dev_vfs;
895 u8 uar_page_shift;
896 };
897
898 struct mlx4_clock_params {
899 u64 offset;
900 u8 bar;
901 u8 size;
902 };
903
904 struct mlx4_eqe {
905 u8 reserved1;
906 u8 type;
907 u8 reserved2;
908 u8 subtype;
909 union {
910 u32 raw[6];
911 struct {
912 __be32 cqn;
913 } __packed comp;
914 struct {
915 u16 reserved1;
916 __be16 token;
917 u32 reserved2;
918 u8 reserved3[3];
919 u8 status;
920 __be64 out_param;
921 } __packed cmd;
922 struct {
923 __be32 qpn;
924 } __packed qp;
925 struct {
926 __be32 srqn;
927 } __packed srq;
928 struct {
929 __be32 cqn;
930 u32 reserved1;
931 u8 reserved2[3];
932 u8 syndrome;
933 } __packed cq_err;
934 struct {
935 u32 reserved1[2];
936 __be32 port;
937 } __packed port_change;
938 struct {
939 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
940 u32 reserved;
941 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
942 } __packed comm_channel_arm;
943 struct {
944 u8 port;
945 u8 reserved[3];
946 __be64 mac;
947 } __packed mac_update;
948 struct {
949 __be32 slave_id;
950 } __packed flr_event;
951 struct {
952 __be16 current_temperature;
953 __be16 warning_threshold;
954 } __packed warming;
955 struct {
956 u8 reserved[3];
957 u8 port;
958 union {
959 struct {
960 __be16 mstr_sm_lid;
961 __be16 port_lid;
962 __be32 changed_attr;
963 u8 reserved[3];
964 u8 mstr_sm_sl;
965 __be64 gid_prefix;
966 } __packed port_info;
967 struct {
968 __be32 block_ptr;
969 __be32 tbl_entries_mask;
970 } __packed tbl_change_info;
971 struct {
972 u8 sl2vl_table[8];
973 } __packed sl2vl_tbl_change_info;
974 } params;
975 } __packed port_mgmt_change;
976 struct {
977 u8 reserved[3];
978 u8 port;
979 u32 reserved1[5];
980 } __packed bad_cable;
981 } event;
982 u8 slave_id;
983 u8 reserved3[2];
984 u8 owner;
985 } __packed;
986
987 struct mlx4_init_port_param {
988 int set_guid0;
989 int set_node_guid;
990 int set_si_guid;
991 u16 mtu;
992 int port_width_cap;
993 u16 vl_cap;
994 u16 max_gid;
995 u16 max_pkey;
996 u64 guid0;
997 u64 node_guid;
998 u64 si_guid;
999 };
1000
1001 #define MAD_IFC_DATA_SZ 192
1002 /* MAD IFC Mailbox */
1003 struct mlx4_mad_ifc {
1004 u8 base_version;
1005 u8 mgmt_class;
1006 u8 class_version;
1007 u8 method;
1008 __be16 status;
1009 __be16 class_specific;
1010 __be64 tid;
1011 __be16 attr_id;
1012 __be16 resv;
1013 __be32 attr_mod;
1014 __be64 mkey;
1015 __be16 dr_slid;
1016 __be16 dr_dlid;
1017 u8 reserved[28];
1018 u8 data[MAD_IFC_DATA_SZ];
1019 } __packed;
1020
1021 #define mlx4_foreach_port(port, dev, type) \
1022 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1023 if ((type) == (dev)->caps.port_mask[(port)])
1024
1025 #define mlx4_foreach_ib_transport_port(port, dev) \
1026 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1027 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1028 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
1029
1030 #define MLX4_INVALID_SLAVE_ID 0xFF
1031 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1032
1033 void handle_port_mgmt_change_event(struct work_struct *work);
1034
mlx4_master_func_num(struct mlx4_dev * dev)1035 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1036 {
1037 return dev->caps.function;
1038 }
1039
mlx4_is_master(struct mlx4_dev * dev)1040 static inline int mlx4_is_master(struct mlx4_dev *dev)
1041 {
1042 return dev->flags & MLX4_FLAG_MASTER;
1043 }
1044
mlx4_num_reserved_sqps(struct mlx4_dev * dev)1045 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1046 {
1047 return dev->phys_caps.base_sqpn + 8 +
1048 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1049 }
1050
mlx4_is_qp_reserved(struct mlx4_dev * dev,u32 qpn)1051 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1052 {
1053 return (qpn < dev->phys_caps.base_sqpn + 8 +
1054 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1055 qpn >= dev->phys_caps.base_sqpn) ||
1056 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1057 }
1058
mlx4_is_guest_proxy(struct mlx4_dev * dev,int slave,u32 qpn)1059 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1060 {
1061 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1062
1063 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1064 return 1;
1065
1066 return 0;
1067 }
1068
mlx4_is_mfunc(struct mlx4_dev * dev)1069 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1070 {
1071 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1072 }
1073
mlx4_is_slave(struct mlx4_dev * dev)1074 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1075 {
1076 return dev->flags & MLX4_FLAG_SLAVE;
1077 }
1078
mlx4_is_eth(struct mlx4_dev * dev,int port)1079 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1080 {
1081 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1082 }
1083
1084 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1085 struct mlx4_buf *buf);
1086 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
mlx4_buf_offset(struct mlx4_buf * buf,int offset)1087 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1088 {
1089 if (buf->nbufs == 1)
1090 return buf->direct.buf + offset;
1091 else
1092 return buf->page_list[offset >> PAGE_SHIFT].buf +
1093 (offset & (PAGE_SIZE - 1));
1094 }
1095
1096 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1097 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1098 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1099 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1100
1101 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1102 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1103 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1104 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1105
1106 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1107 struct mlx4_mtt *mtt);
1108 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1109 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1110
1111 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1112 int npages, int page_shift, struct mlx4_mr *mr);
1113 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1114 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1115 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1116 struct mlx4_mw *mw);
1117 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1118 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1119 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1120 int start_index, int npages, u64 *page_list);
1121 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1122 struct mlx4_buf *buf);
1123
1124 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
1125 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1126
1127 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1128 int size);
1129 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1130 int size);
1131
1132 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1133 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1134 unsigned vector, int collapsed, int timestamp_en);
1135 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1136 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1137 int *base, u8 flags, u8 usage);
1138 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1139
1140 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1141 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1142
1143 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1144 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1145 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1146 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1147 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1148
1149 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1150 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1151
1152 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1153 int block_mcast_loopback, enum mlx4_protocol prot);
1154 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1155 enum mlx4_protocol prot);
1156 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1157 u8 port, int block_mcast_loopback,
1158 enum mlx4_protocol protocol, u64 *reg_id);
1159 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1160 enum mlx4_protocol protocol, u64 reg_id);
1161
1162 enum {
1163 MLX4_DOMAIN_UVERBS = 0x1000,
1164 MLX4_DOMAIN_ETHTOOL = 0x2000,
1165 MLX4_DOMAIN_RFS = 0x3000,
1166 MLX4_DOMAIN_NIC = 0x5000,
1167 };
1168
1169 enum mlx4_net_trans_rule_id {
1170 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1171 MLX4_NET_TRANS_RULE_ID_IB,
1172 MLX4_NET_TRANS_RULE_ID_IPV6,
1173 MLX4_NET_TRANS_RULE_ID_IPV4,
1174 MLX4_NET_TRANS_RULE_ID_TCP,
1175 MLX4_NET_TRANS_RULE_ID_UDP,
1176 MLX4_NET_TRANS_RULE_ID_VXLAN,
1177 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1178 };
1179
1180 extern const u16 __sw_id_hw[];
1181
map_hw_to_sw_id(u16 header_id)1182 static inline int map_hw_to_sw_id(u16 header_id)
1183 {
1184
1185 int i;
1186 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1187 if (header_id == __sw_id_hw[i])
1188 return i;
1189 }
1190 return -EINVAL;
1191 }
1192
1193 enum mlx4_net_trans_promisc_mode {
1194 MLX4_FS_REGULAR = 1,
1195 MLX4_FS_ALL_DEFAULT,
1196 MLX4_FS_MC_DEFAULT,
1197 MLX4_FS_MIRROR_RX_PORT,
1198 MLX4_FS_MIRROR_SX_PORT,
1199 MLX4_FS_UC_SNIFFER,
1200 MLX4_FS_MC_SNIFFER,
1201 MLX4_FS_MODE_NUM, /* should be last */
1202 };
1203
1204 struct mlx4_spec_eth {
1205 u8 dst_mac[ETH_ALEN];
1206 u8 dst_mac_msk[ETH_ALEN];
1207 u8 src_mac[ETH_ALEN];
1208 u8 src_mac_msk[ETH_ALEN];
1209 u8 ether_type_enable;
1210 __be16 ether_type;
1211 __be16 vlan_id_msk;
1212 __be16 vlan_id;
1213 };
1214
1215 struct mlx4_spec_tcp_udp {
1216 __be16 dst_port;
1217 __be16 dst_port_msk;
1218 __be16 src_port;
1219 __be16 src_port_msk;
1220 };
1221
1222 struct mlx4_spec_ipv4 {
1223 __be32 dst_ip;
1224 __be32 dst_ip_msk;
1225 __be32 src_ip;
1226 __be32 src_ip_msk;
1227 };
1228
1229 struct mlx4_spec_ib {
1230 __be32 l3_qpn;
1231 __be32 qpn_msk;
1232 u8 dst_gid[16];
1233 u8 dst_gid_msk[16];
1234 };
1235
1236 struct mlx4_spec_vxlan {
1237 __be32 vni;
1238 __be32 vni_mask;
1239
1240 };
1241
1242 struct mlx4_spec_list {
1243 struct list_head list;
1244 enum mlx4_net_trans_rule_id id;
1245 union {
1246 struct mlx4_spec_eth eth;
1247 struct mlx4_spec_ib ib;
1248 struct mlx4_spec_ipv4 ipv4;
1249 struct mlx4_spec_tcp_udp tcp_udp;
1250 struct mlx4_spec_vxlan vxlan;
1251 };
1252 };
1253
1254 enum mlx4_net_trans_hw_rule_queue {
1255 MLX4_NET_TRANS_Q_FIFO,
1256 MLX4_NET_TRANS_Q_LIFO,
1257 };
1258
1259 struct mlx4_net_trans_rule {
1260 struct list_head list;
1261 enum mlx4_net_trans_hw_rule_queue queue_mode;
1262 bool exclusive;
1263 bool allow_loopback;
1264 enum mlx4_net_trans_promisc_mode promisc_mode;
1265 u8 port;
1266 u16 priority;
1267 u32 qpn;
1268 };
1269
1270 struct mlx4_net_trans_rule_hw_ctrl {
1271 __be16 prio;
1272 u8 type;
1273 u8 flags;
1274 u8 rsvd1;
1275 u8 funcid;
1276 u8 vep;
1277 u8 port;
1278 __be32 qpn;
1279 __be32 rsvd2;
1280 };
1281
1282 struct mlx4_net_trans_rule_hw_ib {
1283 u8 size;
1284 u8 rsvd1;
1285 __be16 id;
1286 u32 rsvd2;
1287 __be32 l3_qpn;
1288 __be32 qpn_mask;
1289 u8 dst_gid[16];
1290 u8 dst_gid_msk[16];
1291 } __packed;
1292
1293 struct mlx4_net_trans_rule_hw_eth {
1294 u8 size;
1295 u8 rsvd;
1296 __be16 id;
1297 u8 rsvd1[6];
1298 u8 dst_mac[6];
1299 u16 rsvd2;
1300 u8 dst_mac_msk[6];
1301 u16 rsvd3;
1302 u8 src_mac[6];
1303 u16 rsvd4;
1304 u8 src_mac_msk[6];
1305 u8 rsvd5;
1306 u8 ether_type_enable;
1307 __be16 ether_type;
1308 __be16 vlan_tag_msk;
1309 __be16 vlan_tag;
1310 } __packed;
1311
1312 struct mlx4_net_trans_rule_hw_tcp_udp {
1313 u8 size;
1314 u8 rsvd;
1315 __be16 id;
1316 __be16 rsvd1[3];
1317 __be16 dst_port;
1318 __be16 rsvd2;
1319 __be16 dst_port_msk;
1320 __be16 rsvd3;
1321 __be16 src_port;
1322 __be16 rsvd4;
1323 __be16 src_port_msk;
1324 } __packed;
1325
1326 struct mlx4_net_trans_rule_hw_ipv4 {
1327 u8 size;
1328 u8 rsvd;
1329 __be16 id;
1330 __be32 rsvd1;
1331 __be32 dst_ip;
1332 __be32 dst_ip_msk;
1333 __be32 src_ip;
1334 __be32 src_ip_msk;
1335 } __packed;
1336
1337 struct mlx4_net_trans_rule_hw_vxlan {
1338 u8 size;
1339 u8 rsvd;
1340 __be16 id;
1341 __be32 rsvd1;
1342 __be32 vni;
1343 __be32 vni_mask;
1344 } __packed;
1345
1346 struct _rule_hw {
1347 union {
1348 struct {
1349 u8 size;
1350 u8 rsvd;
1351 __be16 id;
1352 };
1353 struct mlx4_net_trans_rule_hw_eth eth;
1354 struct mlx4_net_trans_rule_hw_ib ib;
1355 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1356 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1357 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1358 };
1359 };
1360
1361 enum {
1362 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1363 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1364 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1365 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1366 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1367 };
1368
1369 enum {
1370 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1371 };
1372
1373 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1374 enum mlx4_net_trans_promisc_mode mode);
1375 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1376 enum mlx4_net_trans_promisc_mode mode);
1377 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1378 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1379 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1380 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1381 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1382
1383 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1384 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1385 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1386 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1387 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1388 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1389 int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
1390 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
1391 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1392 u8 promisc);
1393 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1394 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1395 u8 ignore_fcs_value);
1396 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1397 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1398 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1399 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1400 bool *vlan_offload_disabled);
1401 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
1402 struct _rule_hw *eth_header);
1403 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1404 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1405 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1406 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1407
1408 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1409 int npages, u64 iova, u32 *lkey, u32 *rkey);
1410 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1411 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1412 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1413 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1414 u32 *lkey, u32 *rkey);
1415 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1416 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1417 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1418 int mlx4_test_async(struct mlx4_dev *dev);
1419 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1420 const u32 offset[], u32 value[],
1421 size_t array_len, u8 port);
1422 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1423 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1424 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1425 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1426 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1427
1428 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1429 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1430
1431 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1432 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1433 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1434
1435 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
1436 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1437 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1438
1439 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1440 int port);
1441 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1442 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1443 int mlx4_flow_attach(struct mlx4_dev *dev,
1444 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1445 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1446 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1447 enum mlx4_net_trans_promisc_mode flow_type);
1448 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1449 enum mlx4_net_trans_rule_id id);
1450 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1451
1452 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1453 int port, int qpn, u16 prio, u64 *reg_id);
1454
1455 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1456 int i, int val);
1457
1458 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1459
1460 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1461 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1462 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1463 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1464 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1465 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1466 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1467
1468 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1469 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1470
1471 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1472 int *slave_id);
1473 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1474 u8 *gid);
1475
1476 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1477 u32 max_range_qpn);
1478
1479 u64 mlx4_read_clock(struct mlx4_dev *dev);
1480
1481 struct mlx4_active_ports {
1482 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1483 };
1484 /* Returns a bitmap of the physical ports which are assigned to slave */
1485 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1486
1487 /* Returns the physical port that represents the virtual port of the slave, */
1488 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1489 /* mapping is returned. */
1490 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1491
1492 struct mlx4_slaves_pport {
1493 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1494 };
1495 /* Returns a bitmap of all slaves that are assigned to port. */
1496 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1497 int port);
1498
1499 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1500 /* the ports that are set in crit_ports. */
1501 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1502 struct mlx4_dev *dev,
1503 const struct mlx4_active_ports *crit_ports);
1504
1505 /* Returns the slave's virtual port that represents the physical port. */
1506 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1507
1508 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1509
1510 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1511 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1512 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1513 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1514 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1515 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1516 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1517 int enable);
1518 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1519 struct mlx4_mpt_entry ***mpt_entry);
1520 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1521 struct mlx4_mpt_entry **mpt_entry);
1522 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1523 u32 pdn);
1524 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1525 struct mlx4_mpt_entry *mpt_entry,
1526 u32 access);
1527 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1528 struct mlx4_mpt_entry **mpt_entry);
1529 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1530 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1531 u64 iova, u64 size, int npages,
1532 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1533
1534 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1535 u16 offset, u16 size, u8 *data);
1536 int mlx4_max_tc(struct mlx4_dev *dev);
1537
1538 /* Returns true if running in low memory profile (kdump kernel) */
mlx4_low_memory_profile(void)1539 static inline bool mlx4_low_memory_profile(void)
1540 {
1541 return is_kdump_kernel();
1542 }
1543
1544 /* ACCESS REG commands */
1545 enum mlx4_access_reg_method {
1546 MLX4_ACCESS_REG_QUERY = 0x1,
1547 MLX4_ACCESS_REG_WRITE = 0x2,
1548 };
1549
1550 /* ACCESS PTYS Reg command */
1551 enum mlx4_ptys_proto {
1552 MLX4_PTYS_IB = 1<<0,
1553 MLX4_PTYS_EN = 1<<2,
1554 };
1555
1556 enum mlx4_ptys_flags {
1557 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5,
1558 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
1559 };
1560
1561 struct mlx4_ptys_reg {
1562 u8 flags;
1563 u8 local_port;
1564 u8 resrvd2;
1565 u8 proto_mask;
1566 __be32 resrvd3[2];
1567 __be32 eth_proto_cap;
1568 __be16 ib_width_cap;
1569 __be16 ib_speed_cap;
1570 __be32 resrvd4;
1571 __be32 eth_proto_admin;
1572 __be16 ib_width_admin;
1573 __be16 ib_speed_admin;
1574 __be32 resrvd5;
1575 __be32 eth_proto_oper;
1576 __be16 ib_width_oper;
1577 __be16 ib_speed_oper;
1578 __be32 resrvd6;
1579 __be32 eth_proto_lp_adv;
1580 } __packed;
1581
1582 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1583 enum mlx4_access_reg_method method,
1584 struct mlx4_ptys_reg *ptys_reg);
1585
1586 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1587 struct mlx4_clock_params *params);
1588
mlx4_to_hw_uar_index(struct mlx4_dev * dev,int index)1589 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1590 {
1591 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1592 }
1593
mlx4_get_num_reserved_uar(struct mlx4_dev * dev)1594 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1595 {
1596 /* The first 128 UARs are used for EQ doorbells */
1597 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1598 }
1599 #endif /* MLX4_DEVICE_H */
1600