1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53
54 enum {
55 MLX5_BOARD_ID_LEN = 64,
56 MLX5_MAX_NAME_LEN = 16,
57 };
58
59 enum {
60 /* one minute for the sake of bringup. Generally, commands must always
61 * complete and we may need to increase this timeout value
62 */
63 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
64 MLX5_CMD_WQ_MAX_NAME = 32,
65 };
66
67 enum {
68 CMD_OWNER_SW = 0x0,
69 CMD_OWNER_HW = 0x1,
70 CMD_STATUS_SUCCESS = 0,
71 };
72
73 enum mlx5_sqp_t {
74 MLX5_SQP_SMI = 0,
75 MLX5_SQP_GSI = 1,
76 MLX5_SQP_IEEE_1588 = 2,
77 MLX5_SQP_SNIFFER = 3,
78 MLX5_SQP_SYNC_UMR = 4,
79 };
80
81 enum {
82 MLX5_MAX_PORTS = 2,
83 };
84
85 enum {
86 MLX5_EQ_VEC_PAGES = 0,
87 MLX5_EQ_VEC_CMD = 1,
88 MLX5_EQ_VEC_ASYNC = 2,
89 MLX5_EQ_VEC_PFAULT = 3,
90 MLX5_EQ_VEC_COMP_BASE,
91 };
92
93 enum {
94 MLX5_MAX_IRQ_NAME = 32
95 };
96
97 enum {
98 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
99 MLX5_ATOMIC_MODE_CX = 2 << 16,
100 MLX5_ATOMIC_MODE_8B = 3 << 16,
101 MLX5_ATOMIC_MODE_16B = 4 << 16,
102 MLX5_ATOMIC_MODE_32B = 5 << 16,
103 MLX5_ATOMIC_MODE_64B = 6 << 16,
104 MLX5_ATOMIC_MODE_128B = 7 << 16,
105 MLX5_ATOMIC_MODE_256B = 8 << 16,
106 };
107
108 enum {
109 MLX5_REG_QETCR = 0x4005,
110 MLX5_REG_QTCT = 0x400a,
111 MLX5_REG_DCBX_PARAM = 0x4020,
112 MLX5_REG_DCBX_APP = 0x4021,
113 MLX5_REG_FPGA_CAP = 0x4022,
114 MLX5_REG_FPGA_CTRL = 0x4023,
115 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PMLP = 0x5002,
129 MLX5_REG_PCAM = 0x507f,
130 MLX5_REG_NODE_DESC = 0x6001,
131 MLX5_REG_HOST_ENDIANNESS = 0x7004,
132 MLX5_REG_MCIA = 0x9014,
133 MLX5_REG_MLCR = 0x902b,
134 MLX5_REG_MPCNT = 0x9051,
135 MLX5_REG_MTPPS = 0x9053,
136 MLX5_REG_MTPPSE = 0x9054,
137 MLX5_REG_MCQI = 0x9061,
138 MLX5_REG_MCC = 0x9062,
139 MLX5_REG_MCDA = 0x9063,
140 MLX5_REG_MCAM = 0x907f,
141 };
142
143 enum mlx5_dcbx_oper_mode {
144 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
145 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
146 };
147
148 enum {
149 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
150 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
151 };
152
153 enum mlx5_page_fault_resume_flags {
154 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
155 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
156 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
157 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
158 };
159
160 enum dbg_rsc_type {
161 MLX5_DBG_RSC_QP,
162 MLX5_DBG_RSC_EQ,
163 MLX5_DBG_RSC_CQ,
164 };
165
166 enum port_state_policy {
167 MLX5_POLICY_DOWN = 0,
168 MLX5_POLICY_UP = 1,
169 MLX5_POLICY_FOLLOW = 2,
170 MLX5_POLICY_INVALID = 0xffffffff
171 };
172
173 struct mlx5_field_desc {
174 struct dentry *dent;
175 int i;
176 };
177
178 struct mlx5_rsc_debug {
179 struct mlx5_core_dev *dev;
180 void *object;
181 enum dbg_rsc_type type;
182 struct dentry *root;
183 struct mlx5_field_desc fields[0];
184 };
185
186 enum mlx5_dev_event {
187 MLX5_DEV_EVENT_SYS_ERROR,
188 MLX5_DEV_EVENT_PORT_UP,
189 MLX5_DEV_EVENT_PORT_DOWN,
190 MLX5_DEV_EVENT_PORT_INITIALIZED,
191 MLX5_DEV_EVENT_LID_CHANGE,
192 MLX5_DEV_EVENT_PKEY_CHANGE,
193 MLX5_DEV_EVENT_GUID_CHANGE,
194 MLX5_DEV_EVENT_CLIENT_REREG,
195 MLX5_DEV_EVENT_PPS,
196 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
197 };
198
199 enum mlx5_port_status {
200 MLX5_PORT_UP = 1,
201 MLX5_PORT_DOWN = 2,
202 };
203
204 enum mlx5_eq_type {
205 MLX5_EQ_TYPE_COMP,
206 MLX5_EQ_TYPE_ASYNC,
207 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
208 MLX5_EQ_TYPE_PF,
209 #endif
210 };
211
212 struct mlx5_bfreg_info {
213 u32 *sys_pages;
214 int num_low_latency_bfregs;
215 unsigned int *count;
216
217 /*
218 * protect bfreg allocation data structs
219 */
220 struct mutex lock;
221 u32 ver;
222 bool lib_uar_4k;
223 u32 num_sys_pages;
224 };
225
226 struct mlx5_cmd_first {
227 __be32 data[4];
228 };
229
230 struct mlx5_cmd_msg {
231 struct list_head list;
232 struct cmd_msg_cache *parent;
233 u32 len;
234 struct mlx5_cmd_first first;
235 struct mlx5_cmd_mailbox *next;
236 };
237
238 struct mlx5_cmd_debug {
239 struct dentry *dbg_root;
240 struct dentry *dbg_in;
241 struct dentry *dbg_out;
242 struct dentry *dbg_outlen;
243 struct dentry *dbg_status;
244 struct dentry *dbg_run;
245 void *in_msg;
246 void *out_msg;
247 u8 status;
248 u16 inlen;
249 u16 outlen;
250 };
251
252 struct cmd_msg_cache {
253 /* protect block chain allocations
254 */
255 spinlock_t lock;
256 struct list_head head;
257 unsigned int max_inbox_size;
258 unsigned int num_ent;
259 };
260
261 enum {
262 MLX5_NUM_COMMAND_CACHES = 5,
263 };
264
265 struct mlx5_cmd_stats {
266 u64 sum;
267 u64 n;
268 struct dentry *root;
269 struct dentry *avg;
270 struct dentry *count;
271 /* protect command average calculations */
272 spinlock_t lock;
273 };
274
275 struct mlx5_cmd {
276 void *cmd_alloc_buf;
277 dma_addr_t alloc_dma;
278 int alloc_size;
279 void *cmd_buf;
280 dma_addr_t dma;
281 u16 cmdif_rev;
282 u8 log_sz;
283 u8 log_stride;
284 int max_reg_cmds;
285 int events;
286 u32 __iomem *vector;
287
288 /* protect command queue allocations
289 */
290 spinlock_t alloc_lock;
291
292 /* protect token allocations
293 */
294 spinlock_t token_lock;
295 u8 token;
296 unsigned long bitmask;
297 char wq_name[MLX5_CMD_WQ_MAX_NAME];
298 struct workqueue_struct *wq;
299 struct semaphore sem;
300 struct semaphore pages_sem;
301 int mode;
302 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
303 struct dma_pool *pool;
304 struct mlx5_cmd_debug dbg;
305 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
306 int checksum_disabled;
307 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
308 };
309
310 struct mlx5_port_caps {
311 int gid_table_len;
312 int pkey_table_len;
313 u8 ext_port_cap;
314 bool has_smi;
315 };
316
317 struct mlx5_cmd_mailbox {
318 void *buf;
319 dma_addr_t dma;
320 struct mlx5_cmd_mailbox *next;
321 };
322
323 struct mlx5_buf_list {
324 void *buf;
325 dma_addr_t map;
326 };
327
328 struct mlx5_buf {
329 struct mlx5_buf_list direct;
330 int npages;
331 int size;
332 u8 page_shift;
333 };
334
335 struct mlx5_frag_buf {
336 struct mlx5_buf_list *frags;
337 int npages;
338 int size;
339 u8 page_shift;
340 };
341
342 struct mlx5_eq_tasklet {
343 struct list_head list;
344 struct list_head process_list;
345 struct tasklet_struct task;
346 /* lock on completion tasklet list */
347 spinlock_t lock;
348 };
349
350 struct mlx5_eq_pagefault {
351 struct work_struct work;
352 /* Pagefaults lock */
353 spinlock_t lock;
354 struct workqueue_struct *wq;
355 mempool_t *pool;
356 };
357
358 struct mlx5_eq {
359 struct mlx5_core_dev *dev;
360 __be32 __iomem *doorbell;
361 u32 cons_index;
362 struct mlx5_buf buf;
363 int size;
364 unsigned int irqn;
365 u8 eqn;
366 int nent;
367 u64 mask;
368 struct list_head list;
369 int index;
370 struct mlx5_rsc_debug *dbg;
371 enum mlx5_eq_type type;
372 union {
373 struct mlx5_eq_tasklet tasklet_ctx;
374 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
375 struct mlx5_eq_pagefault pf_ctx;
376 #endif
377 };
378 };
379
380 struct mlx5_core_psv {
381 u32 psv_idx;
382 struct psv_layout {
383 u32 pd;
384 u16 syndrome;
385 u16 reserved;
386 u16 bg;
387 u16 app_tag;
388 u32 ref_tag;
389 } psv;
390 };
391
392 struct mlx5_core_sig_ctx {
393 struct mlx5_core_psv psv_memory;
394 struct mlx5_core_psv psv_wire;
395 struct ib_sig_err err_item;
396 bool sig_status_checked;
397 bool sig_err_exists;
398 u32 sigerr_count;
399 };
400
401 enum {
402 MLX5_MKEY_MR = 1,
403 MLX5_MKEY_MW,
404 };
405
406 struct mlx5_core_mkey {
407 u64 iova;
408 u64 size;
409 u32 key;
410 u32 pd;
411 u32 type;
412 };
413
414 #define MLX5_24BIT_MASK ((1 << 24) - 1)
415
416 enum mlx5_res_type {
417 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
418 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
419 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
420 MLX5_RES_SRQ = 3,
421 MLX5_RES_XSRQ = 4,
422 MLX5_RES_XRQ = 5,
423 };
424
425 struct mlx5_core_rsc_common {
426 enum mlx5_res_type res;
427 atomic_t refcount;
428 struct completion free;
429 };
430
431 struct mlx5_core_srq {
432 struct mlx5_core_rsc_common common; /* must be first */
433 u32 srqn;
434 int max;
435 size_t max_gs;
436 size_t max_avail_gather;
437 int wqe_shift;
438 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
439
440 atomic_t refcount;
441 struct completion free;
442 };
443
444 struct mlx5_eq_table {
445 void __iomem *update_ci;
446 void __iomem *update_arm_ci;
447 struct list_head comp_eqs_list;
448 struct mlx5_eq pages_eq;
449 struct mlx5_eq async_eq;
450 struct mlx5_eq cmd_eq;
451 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
452 struct mlx5_eq pfault_eq;
453 #endif
454 int num_comp_vectors;
455 /* protect EQs list
456 */
457 spinlock_t lock;
458 };
459
460 struct mlx5_uars_page {
461 void __iomem *map;
462 bool wc;
463 u32 index;
464 struct list_head list;
465 unsigned int bfregs;
466 unsigned long *reg_bitmap; /* for non fast path bf regs */
467 unsigned long *fp_bitmap;
468 unsigned int reg_avail;
469 unsigned int fp_avail;
470 struct kref ref_count;
471 struct mlx5_core_dev *mdev;
472 };
473
474 struct mlx5_bfreg_head {
475 /* protect blue flame registers allocations */
476 struct mutex lock;
477 struct list_head list;
478 };
479
480 struct mlx5_bfreg_data {
481 struct mlx5_bfreg_head reg_head;
482 struct mlx5_bfreg_head wc_head;
483 };
484
485 struct mlx5_sq_bfreg {
486 void __iomem *map;
487 struct mlx5_uars_page *up;
488 bool wc;
489 u32 index;
490 unsigned int offset;
491 };
492
493 struct mlx5_core_health {
494 struct health_buffer __iomem *health;
495 __be32 __iomem *health_counter;
496 struct timer_list timer;
497 u32 prev;
498 int miss_counter;
499 bool sick;
500 /* wq spinlock to synchronize draining */
501 spinlock_t wq_lock;
502 struct workqueue_struct *wq;
503 unsigned long flags;
504 struct work_struct work;
505 struct delayed_work recover_work;
506 };
507
508 struct mlx5_cq_table {
509 /* protect radix tree
510 */
511 spinlock_t lock;
512 struct radix_tree_root tree;
513 };
514
515 struct mlx5_qp_table {
516 /* protect radix tree
517 */
518 spinlock_t lock;
519 struct radix_tree_root tree;
520 };
521
522 struct mlx5_srq_table {
523 /* protect radix tree
524 */
525 spinlock_t lock;
526 struct radix_tree_root tree;
527 };
528
529 struct mlx5_mkey_table {
530 /* protect radix tree
531 */
532 rwlock_t lock;
533 struct radix_tree_root tree;
534 };
535
536 struct mlx5_vf_context {
537 int enabled;
538 u64 port_guid;
539 u64 node_guid;
540 enum port_state_policy policy;
541 };
542
543 struct mlx5_core_sriov {
544 struct mlx5_vf_context *vfs_ctx;
545 int num_vfs;
546 int enabled_vfs;
547 };
548
549 struct mlx5_irq_info {
550 cpumask_var_t mask;
551 char name[MLX5_MAX_IRQ_NAME];
552 };
553
554 struct mlx5_fc_stats {
555 struct rb_root counters;
556 struct list_head addlist;
557 /* protect addlist add/splice operations */
558 spinlock_t addlist_lock;
559
560 struct workqueue_struct *wq;
561 struct delayed_work work;
562 unsigned long next_query;
563 unsigned long sampling_interval; /* jiffies */
564 };
565
566 struct mlx5_mpfs;
567 struct mlx5_eswitch;
568 struct mlx5_lag;
569 struct mlx5_pagefault;
570
571 struct mlx5_rl_entry {
572 u32 rate;
573 u16 index;
574 u16 refcount;
575 };
576
577 struct mlx5_rl_table {
578 /* protect rate limit table */
579 struct mutex rl_lock;
580 u16 max_size;
581 u32 max_rate;
582 u32 min_rate;
583 struct mlx5_rl_entry *rl_entry;
584 };
585
586 enum port_module_event_status_type {
587 MLX5_MODULE_STATUS_PLUGGED = 0x1,
588 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
589 MLX5_MODULE_STATUS_ERROR = 0x3,
590 MLX5_MODULE_STATUS_NUM = 0x3,
591 };
592
593 enum port_module_event_error_type {
594 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
595 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
596 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
597 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
598 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
599 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
600 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
601 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
602 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
603 MLX5_MODULE_EVENT_ERROR_NUM,
604 };
605
606 struct mlx5_port_module_event_stats {
607 u64 status_counters[MLX5_MODULE_STATUS_NUM];
608 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
609 };
610
611 struct mlx5_priv {
612 char name[MLX5_MAX_NAME_LEN];
613 struct mlx5_eq_table eq_table;
614 struct mlx5_irq_info *irq_info;
615
616 /* pages stuff */
617 struct workqueue_struct *pg_wq;
618 struct rb_root page_root;
619 int fw_pages;
620 atomic_t reg_pages;
621 struct list_head free_list;
622 int vfs_pages;
623
624 struct mlx5_core_health health;
625
626 struct mlx5_srq_table srq_table;
627
628 /* start: qp staff */
629 struct mlx5_qp_table qp_table;
630 struct dentry *qp_debugfs;
631 struct dentry *eq_debugfs;
632 struct dentry *cq_debugfs;
633 struct dentry *cmdif_debugfs;
634 /* end: qp staff */
635
636 /* start: cq staff */
637 struct mlx5_cq_table cq_table;
638 /* end: cq staff */
639
640 /* start: mkey staff */
641 struct mlx5_mkey_table mkey_table;
642 /* end: mkey staff */
643
644 /* start: alloc staff */
645 /* protect buffer alocation according to numa node */
646 struct mutex alloc_mutex;
647 int numa_node;
648
649 struct mutex pgdir_mutex;
650 struct list_head pgdir_list;
651 /* end: alloc staff */
652 struct dentry *dbg_root;
653
654 /* protect mkey key part */
655 spinlock_t mkey_lock;
656 u8 mkey_key;
657
658 struct list_head dev_list;
659 struct list_head ctx_list;
660 spinlock_t ctx_lock;
661
662 struct list_head waiting_events_list;
663 bool is_accum_events;
664
665 struct mlx5_flow_steering *steering;
666 struct mlx5_mpfs *mpfs;
667 struct mlx5_eswitch *eswitch;
668 struct mlx5_core_sriov sriov;
669 struct mlx5_lag *lag;
670 unsigned long pci_dev_data;
671 struct mlx5_fc_stats fc_stats;
672 struct mlx5_rl_table rl_table;
673
674 struct mlx5_port_module_event_stats pme_stats;
675
676 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
677 void (*pfault)(struct mlx5_core_dev *dev,
678 void *context,
679 struct mlx5_pagefault *pfault);
680 void *pfault_ctx;
681 struct srcu_struct pfault_srcu;
682 #endif
683 struct mlx5_bfreg_data bfregs;
684 struct mlx5_uars_page *uar;
685 };
686
687 enum mlx5_device_state {
688 MLX5_DEVICE_STATE_UP,
689 MLX5_DEVICE_STATE_INTERNAL_ERROR,
690 };
691
692 enum mlx5_interface_state {
693 MLX5_INTERFACE_STATE_UP = BIT(0),
694 };
695
696 enum mlx5_pci_status {
697 MLX5_PCI_STATUS_DISABLED,
698 MLX5_PCI_STATUS_ENABLED,
699 };
700
701 enum mlx5_pagefault_type_flags {
702 MLX5_PFAULT_REQUESTOR = 1 << 0,
703 MLX5_PFAULT_WRITE = 1 << 1,
704 MLX5_PFAULT_RDMA = 1 << 2,
705 };
706
707 /* Contains the details of a pagefault. */
708 struct mlx5_pagefault {
709 u32 bytes_committed;
710 u32 token;
711 u8 event_subtype;
712 u8 type;
713 union {
714 /* Initiator or send message responder pagefault details. */
715 struct {
716 /* Received packet size, only valid for responders. */
717 u32 packet_size;
718 /*
719 * Number of resource holding WQE, depends on type.
720 */
721 u32 wq_num;
722 /*
723 * WQE index. Refers to either the send queue or
724 * receive queue, according to event_subtype.
725 */
726 u16 wqe_index;
727 } wqe;
728 /* RDMA responder pagefault details */
729 struct {
730 u32 r_key;
731 /*
732 * Received packet size, minimal size page fault
733 * resolution required for forward progress.
734 */
735 u32 packet_size;
736 u32 rdma_op_len;
737 u64 rdma_va;
738 } rdma;
739 };
740
741 struct mlx5_eq *eq;
742 struct work_struct work;
743 };
744
745 struct mlx5_td {
746 /* protects tirs list changes while tirs refresh */
747 struct mutex list_lock;
748 struct list_head tirs_list;
749 u32 tdn;
750 };
751
752 struct mlx5e_resources {
753 u32 pdn;
754 struct mlx5_td td;
755 struct mlx5_core_mkey mkey;
756 struct mlx5_sq_bfreg bfreg;
757 };
758
759 #define MLX5_MAX_RESERVED_GIDS 8
760
761 struct mlx5_rsvd_gids {
762 unsigned int start;
763 unsigned int count;
764 struct ida ida;
765 };
766
767 struct mlx5_core_dev {
768 struct pci_dev *pdev;
769 /* sync pci state */
770 struct mutex pci_status_mutex;
771 enum mlx5_pci_status pci_status;
772 u8 rev_id;
773 char board_id[MLX5_BOARD_ID_LEN];
774 struct mlx5_cmd cmd;
775 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
776 struct {
777 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
778 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
779 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
780 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
781 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
782 } caps;
783 phys_addr_t iseg_base;
784 struct mlx5_init_seg __iomem *iseg;
785 enum mlx5_device_state state;
786 /* sync interface state */
787 struct mutex intf_state_mutex;
788 unsigned long intf_state;
789 void (*event) (struct mlx5_core_dev *dev,
790 enum mlx5_dev_event event,
791 unsigned long param);
792 struct mlx5_priv priv;
793 struct mlx5_profile *profile;
794 atomic_t num_qps;
795 u32 issi;
796 struct mlx5e_resources mlx5e_res;
797 struct {
798 struct mlx5_rsvd_gids reserved_gids;
799 u32 roce_en;
800 } roce;
801 #ifdef CONFIG_MLX5_FPGA
802 struct mlx5_fpga_device *fpga;
803 #endif
804 #ifdef CONFIG_RFS_ACCEL
805 struct cpu_rmap *rmap;
806 #endif
807 };
808
809 struct mlx5_db {
810 __be32 *db;
811 union {
812 struct mlx5_db_pgdir *pgdir;
813 struct mlx5_ib_user_db_page *user_page;
814 } u;
815 dma_addr_t dma;
816 int index;
817 };
818
819 enum {
820 MLX5_COMP_EQ_SIZE = 1024,
821 };
822
823 enum {
824 MLX5_PTYS_IB = 1 << 0,
825 MLX5_PTYS_EN = 1 << 2,
826 };
827
828 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
829
830 enum {
831 MLX5_CMD_ENT_STATE_PENDING_COMP,
832 };
833
834 struct mlx5_cmd_work_ent {
835 unsigned long state;
836 struct mlx5_cmd_msg *in;
837 struct mlx5_cmd_msg *out;
838 void *uout;
839 int uout_size;
840 mlx5_cmd_cbk_t callback;
841 struct delayed_work cb_timeout_work;
842 void *context;
843 int idx;
844 struct completion done;
845 struct mlx5_cmd *cmd;
846 struct work_struct work;
847 struct mlx5_cmd_layout *lay;
848 int ret;
849 int page_queue;
850 u8 status;
851 u8 token;
852 u64 ts1;
853 u64 ts2;
854 u16 op;
855 bool polling;
856 };
857
858 struct mlx5_pas {
859 u64 pa;
860 u8 log_sz;
861 };
862
863 enum phy_port_state {
864 MLX5_AAA_111
865 };
866
867 struct mlx5_hca_vport_context {
868 u32 field_select;
869 bool sm_virt_aware;
870 bool has_smi;
871 bool has_raw;
872 enum port_state_policy policy;
873 enum phy_port_state phys_state;
874 enum ib_port_state vport_state;
875 u8 port_physical_state;
876 u64 sys_image_guid;
877 u64 port_guid;
878 u64 node_guid;
879 u32 cap_mask1;
880 u32 cap_mask1_perm;
881 u32 cap_mask2;
882 u32 cap_mask2_perm;
883 u16 lid;
884 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
885 u8 lmc;
886 u8 subnet_timeout;
887 u16 sm_lid;
888 u8 sm_sl;
889 u16 qkey_violation_counter;
890 u16 pkey_violation_counter;
891 bool grh_required;
892 };
893
mlx5_buf_offset(struct mlx5_buf * buf,int offset)894 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
895 {
896 return buf->direct.buf + offset;
897 }
898
899 #define STRUCT_FIELD(header, field) \
900 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
901 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
902
pci2mlx5_core_dev(struct pci_dev * pdev)903 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
904 {
905 return pci_get_drvdata(pdev);
906 }
907
908 extern struct dentry *mlx5_debugfs_root;
909
fw_rev_maj(struct mlx5_core_dev * dev)910 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
911 {
912 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
913 }
914
fw_rev_min(struct mlx5_core_dev * dev)915 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
916 {
917 return ioread32be(&dev->iseg->fw_rev) >> 16;
918 }
919
fw_rev_sub(struct mlx5_core_dev * dev)920 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
921 {
922 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
923 }
924
cmdif_rev(struct mlx5_core_dev * dev)925 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
926 {
927 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
928 }
929
mlx5_base_mkey(const u32 key)930 static inline u32 mlx5_base_mkey(const u32 key)
931 {
932 return key & 0xffffff00u;
933 }
934
935 int mlx5_cmd_init(struct mlx5_core_dev *dev);
936 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
937 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
938 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
939
940 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
941 int out_size);
942 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
943 void *out, int out_size, mlx5_cmd_cbk_t callback,
944 void *context);
945 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
946 void *out, int out_size);
947 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
948
949 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
950 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
951 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
952 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
953 int mlx5_health_init(struct mlx5_core_dev *dev);
954 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
955 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
956 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
957 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
958 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
959 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
960 struct mlx5_buf *buf, int node);
961 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
962 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
963 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
964 struct mlx5_frag_buf *buf, int node);
965 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
966 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
967 gfp_t flags, int npages);
968 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
969 struct mlx5_cmd_mailbox *head);
970 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
971 struct mlx5_srq_attr *in);
972 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
973 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
974 struct mlx5_srq_attr *out);
975 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
976 u16 lwm, int is_srq);
977 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
978 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
979 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
980 struct mlx5_core_mkey *mkey,
981 u32 *in, int inlen,
982 u32 *out, int outlen,
983 mlx5_cmd_cbk_t callback, void *context);
984 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
985 struct mlx5_core_mkey *mkey,
986 u32 *in, int inlen);
987 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
988 struct mlx5_core_mkey *mkey);
989 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
990 u32 *out, int outlen);
991 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
992 u32 *mkey);
993 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
994 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
995 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
996 u16 opmod, u8 port);
997 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
998 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
999 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1000 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1001 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1002 s32 npages);
1003 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1004 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1005 void mlx5_register_debugfs(void);
1006 void mlx5_unregister_debugfs(void);
1007 int mlx5_eq_init(struct mlx5_core_dev *dev);
1008 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1009 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1010 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1011 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1012 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1013 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1014 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1015 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1016 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1017 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1018 int nent, u64 mask, const char *name,
1019 enum mlx5_eq_type type);
1020 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1021 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1022 void mlx5_stop_eqs(struct mlx5_core_dev *dev);
1023 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1024 unsigned int *irqn);
1025 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1026 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1027
1028 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1029 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1030 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1031 int size_in, void *data_out, int size_out,
1032 u16 reg_num, int arg, int write);
1033
1034 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1035 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1036 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1037 u32 *out, int outlen);
1038 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1039 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1040 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1041 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1042 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1043 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1044 int node);
1045 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1046
1047 const char *mlx5_command_str(int command);
1048 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1049 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1050 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1051 int npsvs, u32 *sig_index);
1052 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1053 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1054 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1055 struct mlx5_odp_caps *odp_caps);
1056 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1057 u8 port_num, void *out, size_t sz);
1058 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1059 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1060 u32 wq_num, u8 type, int error);
1061 #endif
1062
1063 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1064 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1065 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1066 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1067 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1068 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1069 bool map_wc, bool fast_path);
1070 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1071
1072 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1073 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1074 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1075 const u8 *mac, bool vlan, u16 vlan_id);
1076
fw_initializing(struct mlx5_core_dev * dev)1077 static inline int fw_initializing(struct mlx5_core_dev *dev)
1078 {
1079 return ioread32be(&dev->iseg->initializing) >> 31;
1080 }
1081
mlx5_mkey_to_idx(u32 mkey)1082 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1083 {
1084 return mkey >> 8;
1085 }
1086
mlx5_idx_to_mkey(u32 mkey_idx)1087 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1088 {
1089 return mkey_idx << 8;
1090 }
1091
mlx5_mkey_variant(u32 mkey)1092 static inline u8 mlx5_mkey_variant(u32 mkey)
1093 {
1094 return mkey & 0xff;
1095 }
1096
1097 enum {
1098 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1099 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1100 };
1101
1102 enum {
1103 MR_CACHE_LAST_STD_ENTRY = 20,
1104 MLX5_IMR_MTT_CACHE_ENTRY,
1105 MLX5_IMR_KSM_CACHE_ENTRY,
1106 MAX_MR_CACHE_ENTRIES
1107 };
1108
1109 enum {
1110 MLX5_INTERFACE_PROTOCOL_IB = 0,
1111 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1112 };
1113
1114 struct mlx5_interface {
1115 void * (*add)(struct mlx5_core_dev *dev);
1116 void (*remove)(struct mlx5_core_dev *dev, void *context);
1117 int (*attach)(struct mlx5_core_dev *dev, void *context);
1118 void (*detach)(struct mlx5_core_dev *dev, void *context);
1119 void (*event)(struct mlx5_core_dev *dev, void *context,
1120 enum mlx5_dev_event event, unsigned long param);
1121 void (*pfault)(struct mlx5_core_dev *dev,
1122 void *context,
1123 struct mlx5_pagefault *pfault);
1124 void * (*get_dev)(void *context);
1125 int protocol;
1126 struct list_head list;
1127 };
1128
1129 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1130 int mlx5_register_interface(struct mlx5_interface *intf);
1131 void mlx5_unregister_interface(struct mlx5_interface *intf);
1132 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1133
1134 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1135 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1136 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1137 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1138 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1139 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1140
1141 #ifndef CONFIG_MLX5_CORE_IPOIB
1142 static inline
mlx5_rdma_netdev_alloc(struct mlx5_core_dev * mdev,struct ib_device * ibdev,const char * name,void (* setup)(struct net_device *))1143 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1144 struct ib_device *ibdev,
1145 const char *name,
1146 void (*setup)(struct net_device *))
1147 {
1148 return ERR_PTR(-EOPNOTSUPP);
1149 }
1150
mlx5_rdma_netdev_free(struct net_device * netdev)1151 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1152 #else
1153 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1154 struct ib_device *ibdev,
1155 const char *name,
1156 void (*setup)(struct net_device *));
1157 void mlx5_rdma_netdev_free(struct net_device *netdev);
1158 #endif /* CONFIG_MLX5_CORE_IPOIB */
1159
1160 struct mlx5_profile {
1161 u64 mask;
1162 u8 log_max_qp;
1163 struct {
1164 int size;
1165 int limit;
1166 } mr_cache[MAX_MR_CACHE_ENTRIES];
1167 };
1168
1169 enum {
1170 MLX5_PCI_DEV_IS_VF = 1 << 0,
1171 };
1172
mlx5_core_is_pf(struct mlx5_core_dev * dev)1173 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1174 {
1175 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1176 }
1177
mlx5_get_gid_table_len(u16 param)1178 static inline int mlx5_get_gid_table_len(u16 param)
1179 {
1180 if (param > 4) {
1181 pr_warn("gid table length is zero\n");
1182 return 0;
1183 }
1184
1185 return 8 * (1 << param);
1186 }
1187
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1188 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1189 {
1190 return !!(dev->priv.rl_table.max_size);
1191 }
1192
1193 enum {
1194 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1195 };
1196
1197 static inline const struct cpumask *
mlx5_get_vector_affinity_hint(struct mlx5_core_dev * dev,int vector)1198 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector)
1199 {
1200 return dev->priv.irq_info[vector + MLX5_EQ_VEC_COMP_BASE].mask;
1201 }
1202
1203 #endif /* MLX5_DRIVER_H */
1204